Some code smell fixes from sonarlint
This commit is contained in:
145
src/mem/mem.c
145
src/mem/mem.c
@@ -54,28 +54,30 @@
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# define BLOCK_INVALID 0
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#endif
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mem_mapping_t ram_low_mapping, /* 0..640K mapping */
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ram_mid_mapping, /* 640..1024K mapping */
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ram_mid_mapping2, /* 640..1024K mapping, second part, for SiS 471 in relocate mode */
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ram_remapped_mapping, /* 640..1024K mapping */
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ram_remapped_mapping2, /* 640..1024K second mapping, for SiS 471 mode */
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ram_high_mapping, /* 1024K+ mapping */
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ram_2gb_mapping, /* 1024M+ mapping */
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ram_split_mapping,
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bios_mapping,
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bios_high_mapping;
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mem_mapping_t ram_low_mapping; /* 0..640K mapping */
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mem_mapping_t ram_mid_mapping; /* 640..1024K mapping */
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mem_mapping_t ram_mid_mapping2; /* 640..1024K mapping, second part, for SiS 471 in relocate mode */
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mem_mapping_t ram_remapped_mapping; /* 640..1024K mapping */
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mem_mapping_t ram_remapped_mapping2; /* 640..1024K second mapping, for SiS 471 mode */
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mem_mapping_t ram_high_mapping; /* 1024K+ mapping */
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mem_mapping_t ram_2gb_mapping; /* 1024M+ mapping */
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mem_mapping_t ram_split_mapping;
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mem_mapping_t bios_mapping;
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mem_mapping_t bios_high_mapping;
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page_t *pages, /* RAM page table */
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**page_lookup; /* pagetable lookup */
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uint32_t pages_sz; /* #pages in table */
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page_t *pages; /* RAM page table */
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page_t **page_lookup; /* pagetable lookup */
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uint32_t pages_sz; /* #pages in table */
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uint8_t *ram, *ram2; /* the virtual RAM */
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uint8_t *ram;
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uint8_t *ram2; /* the virtual RAM */
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uint8_t page_ff[4096];
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uint32_t rammask;
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uint32_t addr_space_size;
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uint8_t *rom; /* the virtual ROM */
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uint32_t biosmask, biosaddr;
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uint32_t biosmask;
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uint32_t biosaddr;
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uint32_t pccache;
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uint8_t *pccache2;
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@@ -91,18 +93,18 @@ uintptr_t *writelookup2;
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uint32_t mem_logical_addr;
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int shadowbios = 0,
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shadowbios_write;
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int readlnum = 0,
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writelnum = 0;
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int shadowbios = 0;
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int shadowbios_write;
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int readlnum = 0;
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int writelnum = 0;
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int cachesize = 256;
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uint32_t get_phys_virt,
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get_phys_phys;
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uint32_t get_phys_virt;
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uint32_t get_phys_phys;
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int mem_a20_key = 0,
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mem_a20_alt = 0,
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mem_a20_state = 0;
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int mem_a20_key = 0;
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int mem_a20_alt = 0;
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int mem_a20_state = 0;
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int mmuflush = 0;
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int mmu_perm = 4;
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@@ -121,7 +123,8 @@ uint8_t high_page = 0; /* if a high (> 4 gb) page was detected */
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static uint8_t *page_lookupp; /* pagetable mmu_perm lookup */
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static uint8_t *readlookupp;
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static uint8_t *writelookupp;
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static mem_mapping_t *base_mapping, *last_mapping;
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static mem_mapping_t *base_mapping;
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static mem_mapping_t *last_mapping;
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static mem_mapping_t *read_mapping[MEM_MAPPINGS_NO];
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static mem_mapping_t *write_mapping[MEM_MAPPINGS_NO];
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static mem_mapping_t *read_mapping_bus[MEM_MAPPINGS_NO];
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@@ -129,9 +132,11 @@ static mem_mapping_t *write_mapping_bus[MEM_MAPPINGS_NO];
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static uint8_t *_mem_exec[MEM_MAPPINGS_NO];
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static uint8_t ff_pccache[4] = { 0xff, 0xff, 0xff, 0xff };
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static mem_state_t _mem_state[MEM_MAPPINGS_NO];
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static uint32_t remap_start_addr, remap_start_addr2;
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static uint32_t remap_start_addr;
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static uint32_t remap_start_addr2;
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#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
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static size_t ram_size = 0, ram2_size = 0;
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static size_t ram_size = 0;
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static size_t ram2_size = 0;
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#else
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static size_t ram_size = 0;
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#endif
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@@ -166,13 +171,11 @@ mem_addr_is_ram(uint32_t addr)
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void
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resetreadlookup(void)
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{
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int c;
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/* Initialize the page lookup table. */
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memset(page_lookup, 0x00, (1 << 20) * sizeof(page_t *));
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/* Initialize the tables for lower (<= 1024K) RAM. */
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for (c = 0; c < 256; c++) {
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for (uint16_t c = 0; c < 256; c++) {
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readlookup[c] = 0xffffffff;
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writelookup[c] = 0xffffffff;
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}
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@@ -193,9 +196,7 @@ resetreadlookup(void)
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void
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flushmmucache(void)
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{
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int c;
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for (c = 0; c < 256; c++) {
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for (uint16_t c = 0; c < 256; c++) {
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if (readlookup[c] != (int) 0xffffffff) {
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readlookup2[readlookup[c]] = LOOKUP_INV;
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readlookupp[readlookup[c]] = 4;
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@@ -222,9 +223,7 @@ flushmmucache(void)
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void
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flushmmucache_nopc(void)
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{
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int c;
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for (c = 0; c < 256; c++) {
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for (uint16_t c = 0; c < 256; c++) {
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if (readlookup[c] != (int) 0xffffffff) {
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readlookup2[readlookup[c]] = LOOKUP_INV;
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readlookupp[readlookup[c]] = 4;
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@@ -244,12 +243,11 @@ void
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mem_flush_write_page(uint32_t addr, uint32_t virt)
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{
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page_t *page_target = &pages[addr >> 12];
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int c;
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#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
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uint32_t a;
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#endif
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for (c = 0; c < 256; c++) {
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for (uint16_t c = 0; c < 256; c++) {
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if (writelookup[c] != (int) 0xffffffff) {
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#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
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uintptr_t target = (uintptr_t) &ram[(uintptr_t) (addr & ~0xfff) - (virt & ~0xfff)];
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@@ -280,7 +278,9 @@ mem_flush_write_page(uint32_t addr, uint32_t virt)
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static __inline uint64_t
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mmutranslatereal_normal(uint32_t addr, int rw)
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{
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uint32_t temp, temp2, temp3;
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uint32_t temp;
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uint32_t temp2;
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uint32_t temp3;
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uint32_t addr2;
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if (cpu_state.abrt)
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@@ -345,8 +345,13 @@ mmutranslatereal_normal(uint32_t addr, int rw)
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static __inline uint64_t
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mmutranslatereal_pae(uint32_t addr, int rw)
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{
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uint64_t temp, temp2, temp3, temp4;
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uint64_t addr2, addr3, addr4;
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uint64_t temp;
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uint64_t temp2;
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uint64_t temp3;
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uint64_t temp4;
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uint64_t addr2;
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uint64_t addr3;
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uint64_t addr4;
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if (cpu_state.abrt)
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return 0xffffffffffffffffULL;
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@@ -449,7 +454,9 @@ mmutranslatereal32(uint32_t addr, int rw)
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static __inline uint64_t
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mmutranslate_noabrt_normal(uint32_t addr, int rw)
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{
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uint32_t temp, temp2, temp3;
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uint32_t temp;
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uint32_t temp2;
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uint32_t temp3;
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uint32_t addr2;
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if (cpu_state.abrt)
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@@ -481,8 +488,13 @@ mmutranslate_noabrt_normal(uint32_t addr, int rw)
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static __inline uint64_t
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mmutranslate_noabrt_pae(uint32_t addr, int rw)
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{
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uint64_t temp, temp2, temp3, temp4;
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uint64_t addr2, addr3, addr4;
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uint64_t temp;
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uint64_t temp2;
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uint64_t temp3;
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uint64_t temp4;
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uint64_t addr2;
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uint64_t addr3;
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uint64_t addr4;
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if (cpu_state.abrt)
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return 0xffffffffffffffffULL;
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@@ -885,7 +897,6 @@ uint16_t
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readmemwl(uint32_t addr)
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{
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mem_mapping_t *map;
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int i;
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uint64_t a;
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addr64a[0] = addr;
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@@ -901,7 +912,7 @@ readmemwl(uint32_t addr)
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cycles -= timing_misaligned;
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if ((addr & 0xfff) > 0xffe) {
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if (cr0 >> 31) {
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for (i = 0; i < 2; i++) {
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for (uint8_t i = 0; i < 2; i++) {
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a = mmutranslate_read(addr + i);
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addr64a[i] = (uint32_t) a;
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@@ -944,7 +955,6 @@ void
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writememwl(uint32_t addr, uint16_t val)
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{
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mem_mapping_t *map;
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int i;
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uint64_t a;
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addr64a[0] = addr;
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@@ -960,7 +970,7 @@ writememwl(uint32_t addr, uint16_t val)
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cycles -= timing_misaligned;
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if ((addr & 0xfff) > 0xffe) {
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if (cr0 >> 31) {
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for (i = 0; i < 2; i++) {
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for (uint8_t i = 0; i < 2; i++) {
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/* Do not translate a page that has a valid lookup, as that is by definition valid
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and the whole purpose of the lookup is to avoid repeat identical translations. */
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if (!page_lookup[(addr + i) >> 12] || !page_lookup[(addr + i) >> 12]->write_b) {
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@@ -1563,7 +1573,8 @@ writememql(uint32_t addr, uint64_t val)
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void
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do_mmutranslate(uint32_t addr, uint32_t *a64, int num, int write)
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{
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int i, cond = 1;
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int i;
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int cond = 1;
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uint32_t last_addr = addr + (num - 1);
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uint64_t a = 0x0000000000000000ULL;
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@@ -1631,7 +1642,8 @@ uint16_t
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mem_readw_phys(uint32_t addr)
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{
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mem_mapping_t *map = read_mapping_bus[addr >> MEM_GRANULARITY_BITS];
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uint16_t ret, *p;
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uint16_t ret;
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uint16_t *p;
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mem_logical_addr = 0xffffffff;
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@@ -1652,7 +1664,8 @@ uint32_t
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mem_readl_phys(uint32_t addr)
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{
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mem_mapping_t *map = read_mapping_bus[addr >> MEM_GRANULARITY_BITS];
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uint32_t ret, *p;
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uint32_t ret;
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uint32_t *p;
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mem_logical_addr = 0xffffffff;
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@@ -2530,13 +2543,11 @@ mem_mapping_enable(mem_mapping_t *map)
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void
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mem_set_access(uint8_t bitmap, int mode, uint32_t base, uint32_t size, uint16_t access)
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{
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uint32_t c;
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uint16_t mask, smstate = 0x0000;
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uint16_t mask;
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uint16_t smstate = 0x0000;
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const uint16_t smstates[4] = { 0x0000, (MEM_READ_SMRAM | MEM_WRITE_SMRAM),
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MEM_READ_SMRAM_EX, (MEM_READ_DISABLED_EX | MEM_WRITE_DISABLED_EX) };
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int i;
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if (mode)
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mask = 0x2d6b;
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else
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@@ -2558,8 +2569,8 @@ mem_set_access(uint8_t bitmap, int mode, uint32_t base, uint32_t size, uint16_t
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} else
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smstate = access & 0x6f7b;
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for (c = 0; c < size; c += MEM_GRANULARITY_SIZE) {
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for (i = 0; i < 4; i++) {
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for (uint32_t c = 0; c < size; c += MEM_GRANULARITY_SIZE) {
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for (uint8_t i = 0; i < 4; i++) {
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if (bitmap & (1 << i)) {
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_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] & mask) | smstate;
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}
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@@ -2597,7 +2608,8 @@ mem_a20_init(void)
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void
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mem_close(void)
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{
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mem_mapping_t *map = base_mapping, *next;
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mem_mapping_t *map = base_mapping;
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mem_mapping_t *next;
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while (map != NULL) {
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next = map->next;
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@@ -2628,7 +2640,6 @@ mem_init_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size)
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void
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mem_reset(void)
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{
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uint32_t c;
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size_t m;
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memset(page_ff, 0xff, sizeof(page_ff));
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@@ -2744,7 +2755,7 @@ mem_reset(void)
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memset(byte_code_present_mask, 0, (mem_size * 1024) / 8);
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#endif
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for (c = 0; c < pages_sz; c++) {
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for (uint32_t c = 0; c < pages_sz; c++) {
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if ((c << 12) >= (mem_size << 10))
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pages[c].mem = page_ff;
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else {
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@@ -2857,11 +2868,13 @@ mem_remap_top(int kb)
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{
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uint32_t c;
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uint32_t start = (mem_size >= 1024) ? mem_size : 1024;
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int offset, size = mem_size - 640;
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int offset;
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int size = mem_size - 640;
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int set = 1;
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static int old_kb = 0;
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int sis_mode = 0;
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uint32_t start_addr = 0, addr = 0;
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uint32_t start_addr = 0;
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uint32_t addr = 0;
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mem_log("MEM: remapping top %iKB (mem=%i)\n", kb, mem_size);
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if (mem_size <= 640)
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@@ -2983,12 +2996,10 @@ mem_remap_top(int kb)
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void
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mem_reset_page_blocks(void)
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{
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uint32_t c;
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if (pages == NULL)
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return;
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for (c = 0; c < pages_sz; c++) {
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for (uint32_t c = 0; c < pages_sz; c++) {
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pages[c].write_b = mem_write_ramb_page;
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pages[c].write_w = mem_write_ramw_page;
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pages[c].write_l = mem_write_raml_page;
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@@ -3019,12 +3030,12 @@ mem_a20_recalc(void)
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state = mem_a20_key | mem_a20_alt;
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if (state && !mem_a20_state) {
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rammask = (cpu_16bitbus) ? 0xffffff : 0xffffffff;
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rammask = cpu_16bitbus ? 0xffffff : 0xffffffff;
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if (is6117)
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rammask |= 0x03000000;
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flushmmucache();
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} else if (!state && mem_a20_state) {
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rammask = (cpu_16bitbus) ? 0xefffff : 0xffefffff;
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rammask = cpu_16bitbus ? 0xefffff : 0xffefffff;
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if (is6117)
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rammask |= 0x03000000;
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flushmmucache();
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Block a user