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SDL renderer improvements and fixes and added SDL OpenGL option;

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Various performance improvements;
Fixed USB UHCI HCHalt;
Cirrus Logic CL-GD 5422/24 fixes and removed them from the Dev branch;
The Storage controllers sections of Settings now has its own corresponding section of the configuration file;
Fixed the AT clock divisors for some Pentium OverDrive CPU's;
Added the ACPI RTC status (no ACPI RTC alarm event yet).
This commit is contained in:
OBattler
2020-11-26 18:20:24 +01:00
parent 21d6f2e9f1
commit 6e233f4ac8
53 changed files with 618 additions and 279 deletions
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89
src/mem/mem.c
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@@ -273,7 +273,7 @@ mem_flush_write_page(uint32_t addr, uint32_t virt)
#define rammap(x) ((uint32_t *)(_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 2) & MEM_GRANULARITY_QMASK]
#define rammap64(x) ((uint64_t *)(_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 3) & MEM_GRANULARITY_PMASK]
static uint64_t
static __inline uint64_t
mmutranslatereal_normal(uint32_t addr, int rw)
{
uint32_t temp,temp2,temp3;
@@ -335,7 +335,7 @@ mmutranslatereal_normal(uint32_t addr, int rw)
}
static uint64_t
static __inline uint64_t
mmutranslatereal_pae(uint32_t addr, int rw)
{
uint64_t temp,temp2,temp3,temp4;
@@ -428,7 +428,7 @@ mmutranslatereal32(uint32_t addr, int rw)
}
static uint64_t
static __inline uint64_t
mmutranslate_noabrt_normal(uint32_t addr, int rw)
{
uint32_t temp,temp2,temp3;
@@ -461,7 +461,7 @@ mmutranslate_noabrt_normal(uint32_t addr, int rw)
}
static uint64_t
static __inline uint64_t
mmutranslate_noabrt_pae(uint32_t addr, int rw)
{
uint64_t temp,temp2,temp3,temp4;
@@ -571,7 +571,7 @@ addreadlookup(uint32_t virt, uint32_t phys)
readlookup[readlnext++] = virt >> 12;
readlnext &= (cachesize-1);
sub_cycles(9);
cycles -= 9;
}
@@ -624,7 +624,7 @@ addwritelookup(uint32_t virt, uint32_t phys)
writelookup[writelnext++] = virt >> 12;
writelnext &= (cachesize - 1);
sub_cycles(9);
cycles -= 9;
}
@@ -664,15 +664,19 @@ uint8_t
read_mem_b(uint32_t addr)
{
mem_mapping_t *map;
uint8_t ret = 0xff;
int old_cycles = cycles;
mem_logical_addr = addr;
addr &= rammask;
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_b)
return map->read_b(addr, map->p);
ret = map->read_b(addr, map->p);
return 0xff;
resub_cycles(old_cycles);
return ret;
}
@@ -680,22 +684,26 @@ uint16_t
read_mem_w(uint32_t addr)
{
mem_mapping_t *map;
uint16_t ret = 0xffff;
int old_cycles = cycles;
mem_logical_addr = addr;
addr &= rammask;
if (addr & 1)
return read_mem_b(addr) | (read_mem_b(addr + 1) << 8);
ret = read_mem_b(addr) | (read_mem_b(addr + 1) << 8);
else {
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->read_w)
ret = map->read_w(addr, map->p);
else if (map && map->read_b)
ret = map->read_b(addr, map->p) | (map->read_b(addr + 1, map->p) << 8);
}
if (map && map->read_w)
return map->read_w(addr, map->p);
resub_cycles(old_cycles);
if (map && map->read_b)
return map->read_b(addr, map->p) | (map->read_b(addr + 1, map->p) << 8);
return 0xffff;
return ret;
}
@@ -703,6 +711,7 @@ void
write_mem_b(uint32_t addr, uint8_t val)
{
mem_mapping_t *map;
int old_cycles = cycles;
mem_logical_addr = addr;
addr &= rammask;
@@ -710,6 +719,8 @@ write_mem_b(uint32_t addr, uint8_t val)
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map && map->write_b)
map->write_b(addr, val, map->p);
resub_cycles(old_cycles);
}
@@ -717,6 +728,7 @@ void
write_mem_w(uint32_t addr, uint16_t val)
{
mem_mapping_t *map;
int old_cycles = cycles;
mem_logical_addr = addr;
addr &= rammask;
@@ -724,18 +736,19 @@ write_mem_w(uint32_t addr, uint16_t val)
if (addr & 1) {
write_mem_b(addr, val);
write_mem_b(addr + 1, val >> 8);
return;
}
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map) {
if (map->write_w)
map->write_w(addr, val, map->p);
else if (map->write_b) {
map->write_b(addr, val, map->p);
map->write_b(addr + 1, val >> 8, map->p);
} else {
map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (map) {
if (map->write_w)
map->write_w(addr, val, map->p);
else if (map->write_b) {
map->write_b(addr, val, map->p);
map->write_b(addr + 1, val >> 8, map->p);
}
}
}
resub_cycles(old_cycles);
}
@@ -802,7 +815,7 @@ readmemwl(uint32_t addr)
if (addr64 & 1) {
if (!cpu_cyrix_alignment || (addr64 & 7) == 7)
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr64 & 0xfff) > 0xffe) {
if (cr0 >> 31) {
if (mmutranslate_read(addr) == 0xffffffffffffffffULL)
@@ -846,7 +859,7 @@ writememwl(uint32_t addr, uint16_t val)
if (addr & 1) {
if (!cpu_cyrix_alignment || (addr & 7) == 7)
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr & 0xFFF) > 0xFFE) {
if (cr0 >> 31) {
if (mmutranslate_write(addr) == 0xffffffff)
@@ -899,7 +912,7 @@ readmemll(uint32_t addr)
if (addr & 3) {
if (!cpu_cyrix_alignment || (addr & 7) > 4)
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr & 0xfff) > 0xffc) {
if (cr0>>31) {
if (mmutranslate_read(addr) == 0xffffffffffffffffULL)
@@ -949,7 +962,7 @@ writememll(uint32_t addr, uint32_t val)
if (addr & 3) {
if (!cpu_cyrix_alignment || (addr & 7) > 4)
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr & 0xFFF) > 0xFFC) {
if (cr0>>31) {
if (mmutranslate_write(addr) == 0xffffffffffffffffULL)
@@ -1005,7 +1018,7 @@ readmemql(uint32_t addr)
mem_logical_addr = addr;
if (addr & 7) {
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr & 0xFFF) > 0xFF8) {
if (cr0>>31) {
if (mmutranslate_read(addr) == 0xffffffffffffffffULL)
@@ -1045,7 +1058,7 @@ writememql(uint32_t addr, uint64_t val)
mem_logical_addr = addr;
if (addr & 7) {
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr & 0xFFF) > 0xFF8) {
if (cr0>>31) {
if (mmutranslate_write(addr) == 0xffffffffffffffffULL)
@@ -1122,7 +1135,7 @@ readmemwl(uint32_t seg, uint32_t addr)
if (addr2 & 1) {
if (!cpu_cyrix_alignment || (addr2 & 7) == 7)
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr2 & 0xfff) > 0xffe) {
if (cr0 >> 31) {
if (mmutranslate_read(addr2) == 0xffffffffffffffffULL)
@@ -1174,7 +1187,7 @@ writememwl(uint32_t seg, uint32_t addr, uint16_t val)
if (addr2 & 1) {
if (!cpu_cyrix_alignment || (addr2 & 7) == 7)
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr2 & 0xFFF) > 0xffe) {
if (cr0 >> 31) {
if (mmutranslate_write(addr2) == 0xffffffffffffffffULL) return;
@@ -1234,7 +1247,7 @@ readmemll(uint32_t seg, uint32_t addr)
if (addr2 & 3) {
if (!cpu_cyrix_alignment || (addr2 & 7) > 4)
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr2 & 0xfff) > 0xffc) {
if (cr0 >> 31) {
if (mmutranslate_read(addr2) == 0xffffffffffffffffULL) return 0xffffffff;
@@ -1284,7 +1297,7 @@ writememll(uint32_t seg, uint32_t addr, uint32_t val)
if (addr2 & 3) {
if (!cpu_cyrix_alignment || (addr2 & 7) > 4)
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr2 & 0xfff) > 0xffc) {
if (cr0 >> 31) {
if (mmutranslate_write(addr2) == 0xffffffffffffffffULL) return;
@@ -1344,7 +1357,7 @@ readmemql(uint32_t seg, uint32_t addr)
uint32_t addr2 = mem_logical_addr = seg + addr;
if (addr2 & 7) {
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr2 & 0xfff) > 0xff8) {
if (cr0 >> 31) {
if (mmutranslate_read(addr2) == 0xffffffffffffffffULL) return 0xffffffffffffffffULL;
@@ -1382,7 +1395,7 @@ writememql(uint32_t seg, uint32_t addr, uint64_t val)
uint32_t addr2 = mem_logical_addr = seg + addr;
if (addr2 & 7) {
sub_cycles(timing_misaligned);
cycles -= timing_misaligned;
if ((addr2 & 0xfff) > 0xff8) {
if (cr0 >> 31) {
if (mmutranslate_write(addr2) == 0xffffffffffffffffULL) return;