diff --git a/src/network/net_eeprom_nmc93cxx.c b/src/network/net_eeprom_nmc93cxx.c index 22d2bdd08..d51cc94e7 100644 --- a/src/network/net_eeprom_nmc93cxx.c +++ b/src/network/net_eeprom_nmc93cxx.c @@ -30,10 +30,10 @@ #include <86box/plat_unused.h> struct nmc93cxx_eeprom_t { - uint8_t tick; - uint8_t address; - uint8_t command; - uint8_t writable; + uint8_t tick; + uint8_t address; + uint8_t command; + uint8_t writable; uint8_t eecs; uint8_t eesk; @@ -42,7 +42,7 @@ struct nmc93cxx_eeprom_t { uint8_t addrbits; uint16_t size; uint16_t data; - char filename[1024]; + char filename[1024]; uint16_t contents[]; }; @@ -67,76 +67,75 @@ nmc93cxx_eeprom_log(int lvl, const char *fmt, ...) #endif static const char *opstring[] = { - "extended", "write", "read", "erase" + "extended", "write", "read", "erase" }; static void * -nmc93cxx_eeprom_init_params(UNUSED(const device_t *info), void* params) +nmc93cxx_eeprom_init_params(UNUSED(const device_t *info), void *params) { - uint16_t nwords = 64; - uint8_t addrbits = 6; - uint8_t filldefault = 1; - nmc93cxx_eeprom_params_t *params_details = (nmc93cxx_eeprom_params_t*) params; - nmc93cxx_eeprom_t* eeprom = NULL; + uint16_t nwords = 64; + uint8_t addrbits = 6; + uint8_t filldefault = 1; + nmc93cxx_eeprom_params_t *params_details = (nmc93cxx_eeprom_params_t *) params; + nmc93cxx_eeprom_t *eeprom = NULL; if (!params) return NULL; nwords = params_details->nwords; switch (nwords) { - case 16: - case 64: - addrbits = 6; - break; - case 128: - case 256: - addrbits = 8; - break; - default: - nwords = 64; - addrbits = 6; - break; + case 16: + case 64: + addrbits = 6; + break; + case 128: + case 256: + addrbits = 8; + break; + default: + nwords = 64; + addrbits = 6; + break; } eeprom = calloc(1, sizeof(nmc93cxx_eeprom_t) + ((nwords + 1) * 2)); if (!eeprom) return NULL; - eeprom->size = nwords; + eeprom->size = nwords; eeprom->addrbits = addrbits; /* Output DO is tristate, read results in 1. */ eeprom->eedo = 1; - if (params_details->filename) - { - FILE* file = nvr_fopen(params_details->filename, "rb"); + if (params_details->filename) { + FILE *fp = nvr_fopen(params_details->filename, "rb"); strncpy(eeprom->filename, params_details->filename, 1024); - if (file) { - filldefault = !fread(eeprom->contents, sizeof(uint16_t), nwords, file); - fclose(file); + if (fp) { + filldefault = !fread(eeprom->contents, sizeof(uint16_t), nwords, fp); + fclose(fp); } } - if (filldefault) - { + if (filldefault) { memcpy(eeprom->contents, params_details->default_content, nwords * sizeof(uint16_t)); } return eeprom; } -void nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *eeprom, int eecs, int eesk, int eedi) +void +nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *eeprom, int eecs, int eesk, int eedi) { - uint8_t tick = eeprom->tick; - uint8_t eedo = eeprom->eedo; + uint8_t tick = eeprom->tick; + uint8_t eedo = eeprom->eedo; uint16_t address = eeprom->address; - uint8_t command = eeprom->command; + uint8_t command = eeprom->command; nmc93cxx_eeprom_log(1, "CS=%u SK=%u DI=%u DO=%u, tick = %u\n", - eecs, eesk, eedi, eedo, tick); + eecs, eesk, eedi, eedo, tick); if (!eeprom->eecs && eecs) { /* Start chip select cycle. */ nmc93cxx_eeprom_log(1, "Cycle start, waiting for 1st start bit (0)\n"); - tick = 0; + tick = 0; command = 0x0; address = 0x0; } else if (eeprom->eecs && !eecs) { @@ -200,7 +199,7 @@ void nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *eeprom, int eecs, int eesk, int ee address = ((address << 1) | eedi); if (tick == 2 + 2 + eeprom->addrbits) { nmc93cxx_eeprom_log(1, "%s command, address = 0x%02x (value 0x%04x)\n", - opstring[command], address, eeprom->contents[address]); + opstring[command], address, eeprom->contents[address]); if (command == 2) { eedo = 0; } @@ -245,26 +244,26 @@ void nmc93cxx_eeprom_write(nmc93cxx_eeprom_t *eeprom, int eecs, int eesk, int ee } } /* Save status of EEPROM. */ - eeprom->tick = tick; - eeprom->eecs = eecs; - eeprom->eesk = eesk; - eeprom->eedo = eedo; + eeprom->tick = tick; + eeprom->eecs = eecs; + eeprom->eesk = eesk; + eeprom->eedo = eedo; eeprom->address = address; eeprom->command = command; } -uint16_t nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *eeprom) +uint16_t +nmc93cxx_eeprom_read(nmc93cxx_eeprom_t *eeprom) { /* Return status of pin DO (0 or 1). */ return eeprom->eedo; } - static void nmc93cxx_eeprom_close(void *priv) { - nmc93cxx_eeprom_t* eeprom = (nmc93cxx_eeprom_t*)priv; - FILE* fp = nvr_fopen(eeprom->filename, "wb"); + nmc93cxx_eeprom_t *eeprom = (nmc93cxx_eeprom_t *) priv; + FILE *fp = nvr_fopen(eeprom->filename, "wb"); if (fp) { fwrite(eeprom->contents, 2, eeprom->size, fp); fclose(fp); @@ -272,7 +271,8 @@ nmc93cxx_eeprom_close(void *priv) free(priv); } -uint16_t *nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *eeprom) +uint16_t * +nmc93cxx_eeprom_data(nmc93cxx_eeprom_t *eeprom) { /* Get EEPROM data array. */ return &eeprom->contents[0]; diff --git a/src/network/net_l80225.c b/src/network/net_l80225.c index 801adaa8b..6493edec6 100644 --- a/src/network/net_l80225.c +++ b/src/network/net_l80225.c @@ -15,7 +15,7 @@ #include <86box/network.h> uint16_t -l80225_mii_readw(uint16_t* regs, uint16_t addr) +l80225_mii_readw(uint16_t *regs, uint16_t addr) { switch (addr) { case 0x1: @@ -35,7 +35,7 @@ l80225_mii_readw(uint16_t* regs, uint16_t addr) } void -l80225_mii_writew(uint16_t* regs, uint16_t addr, uint16_t val) +l80225_mii_writew(uint16_t *regs, uint16_t addr, uint16_t val) { regs[addr] = val; } diff --git a/src/network/net_rtl8139.c b/src/network/net_rtl8139.c index 9173e69a0..c184bdafa 100644 --- a/src/network/net_rtl8139.c +++ b/src/network/net_rtl8139.c @@ -44,25 +44,28 @@ #include <86box/net_rtl8139.h> #include <86box/plat_unused.h> -#define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */ +#define PCI_PERIOD 30 /* 30 ns period = 33.333333 Mhz frequency */ #define SET_MASKED(input, mask, curr) \ - ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) ) + (((input) & ~(mask)) | ((curr) & (mask))) /* arg % size for size which is a power of 2 */ #define MOD2(input, size) \ - ( ( input ) & ( size - 1 ) ) + ((input) & (size - 1)) #define ETHER_TYPE_LEN 2 -#define VLAN_TCI_LEN 2 -#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) +#define VLAN_TCI_LEN 2 +#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN) -#if defined (DEBUG_RTL8139) -# define DPRINTF(fmt, ...) \ - do { pclog("RTL8139: " fmt, ## __VA_ARGS__); } while (0) +#if defined(DEBUG_RTL8139) +# define DPRINTF(fmt, ...) \ + do { \ + pclog("RTL8139: " fmt, ##__VA_ARGS__); \ + } while (0) #else -static inline __attribute__ ((format (printf, 1, 2))) int DPRINTF(UNUSED(const char *fmt), ...) +static inline __attribute__((format(printf, 1, 2))) int +DPRINTF(UNUSED(const char *fmt), ...) { return 0; } @@ -73,63 +76,63 @@ typedef struct RTL8139State RTL8139State; /* Symbolic offsets to registers. */ enum RTL8139_registers { - MAC0 = 0, /* Ethernet hardware address. */ - MAR0 = 8, /* Multicast filter. */ - TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */ - /* Dump Tally Conter control register(64bit). C+ mode only */ - TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ - RxBuf = 0x30, - ChipCmd = 0x37, - RxBufPtr = 0x38, - RxBufAddr = 0x3A, - IntrMask = 0x3C, - IntrStatus = 0x3E, - TxConfig = 0x40, - RxConfig = 0x44, - Timer = 0x48, /* A general-purpose counter. */ - RxMissed = 0x4C, /* 24 bits valid, write clears. */ - Cfg9346 = 0x50, - Config0 = 0x51, - Config1 = 0x52, - FlashReg = 0x54, - MediaStatus = 0x58, - Config3 = 0x59, - Config4 = 0x5A, /* absent on RTL-8139A */ - HltClk = 0x5B, - MultiIntr = 0x5C, - PCIRevisionID = 0x5E, - TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ - BasicModeCtrl = 0x62, + MAC0 = 0, /* Ethernet hardware address. */ + MAR0 = 8, /* Multicast filter. */ + TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). C mode only */ + /* Dump Tally Conter control register(64bit). C+ mode only */ + TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */ + RxBuf = 0x30, + ChipCmd = 0x37, + RxBufPtr = 0x38, + RxBufAddr = 0x3A, + IntrMask = 0x3C, + IntrStatus = 0x3E, + TxConfig = 0x40, + RxConfig = 0x44, + Timer = 0x48, /* A general-purpose counter. */ + RxMissed = 0x4C, /* 24 bits valid, write clears. */ + Cfg9346 = 0x50, + Config0 = 0x51, + Config1 = 0x52, + FlashReg = 0x54, + MediaStatus = 0x58, + Config3 = 0x59, + Config4 = 0x5A, /* absent on RTL-8139A */ + HltClk = 0x5B, + MultiIntr = 0x5C, + PCIRevisionID = 0x5E, + TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/ + BasicModeCtrl = 0x62, BasicModeStatus = 0x64, - NWayAdvert = 0x66, - NWayLPAR = 0x68, - NWayExpansion = 0x6A, + NWayAdvert = 0x66, + NWayLPAR = 0x68, + NWayExpansion = 0x6A, /* Undocumented registers, but required for proper operation. */ - FIFOTMS = 0x70, /* FIFO Control and test. */ - CSCR = 0x74, /* Chip Status and Configuration Register. */ - PARA78 = 0x78, - PARA7c = 0x7c, /* Magic transceiver parameter register. */ - Config5 = 0xD8, /* absent on RTL-8139A */ + FIFOTMS = 0x70, /* FIFO Control and test. */ + CSCR = 0x74, /* Chip Status and Configuration Register. */ + PARA78 = 0x78, + PARA7c = 0x7c, /* Magic transceiver parameter register. */ + Config5 = 0xD8, /* absent on RTL-8139A */ /* C+ mode */ - TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ + TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */ RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */ CpCmd = 0xE0, /* C+ Command register (C+ mode only) */ - IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ - RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ - RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ - TxThresh = 0xEC, /* Early Tx threshold */ + IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */ + RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */ + RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */ + TxThresh = 0xEC, /* Early Tx threshold */ }; enum ClearBitMasks { MultiIntrClear = 0xF000, - ChipCmdClear = 0xE2, - Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1), + ChipCmdClear = 0xE2, + Config1Clear = (1 << 7) | (1 << 6) | (1 << 3) | (1 << 2) | (1 << 1), }; enum ChipCmdBits { - CmdReset = 0x10, - CmdRxEnb = 0x08, - CmdTxEnb = 0x04, + CmdReset = 0x10, + CmdRxEnb = 0x08, + CmdTxEnb = 0x04, RxBufEmpty = 0x01, }; @@ -143,102 +146,100 @@ enum CplusCmdBits { /* Interrupt register bits, using my own meaningful names. */ enum IntrStatusBits { - PCIErr = 0x8000, + PCIErr = 0x8000, PCSTimeout = 0x4000, RxFIFOOver = 0x40, RxUnderrun = 0x20, /* Packet Underrun / Link Change */ RxOverflow = 0x10, - TxErr = 0x08, - TxOK = 0x04, - RxErr = 0x02, - RxOK = 0x01, + TxErr = 0x08, + TxOK = 0x04, + RxErr = 0x02, + RxOK = 0x01, RxAckBits = RxFIFOOver | RxOverflow | RxOK, }; enum TxStatusBits { - TxHostOwns = 0x2000, - TxUnderrun = 0x4000, - TxStatOK = 0x8000, + TxHostOwns = 0x2000, + TxUnderrun = 0x4000, + TxStatOK = 0x8000, TxOutOfWindow = 0x20000000, - TxAborted = 0x40000000, + TxAborted = 0x40000000, TxCarrierLost = 0x80000000, }; enum RxStatusBits { RxMulticast = 0x8000, - RxPhysical = 0x4000, + RxPhysical = 0x4000, RxBroadcast = 0x2000, RxBadSymbol = 0x0020, - RxRunt = 0x0010, - RxTooLong = 0x0008, - RxCRCErr = 0x0004, - RxBadAlign = 0x0002, - RxStatusOK = 0x0001, + RxRunt = 0x0010, + RxTooLong = 0x0008, + RxCRCErr = 0x0004, + RxBadAlign = 0x0002, + RxStatusOK = 0x0001, }; /* Bits in RxConfig. */ enum rx_mode_bits { - AcceptErr = 0x20, - AcceptRunt = 0x10, + AcceptErr = 0x20, + AcceptRunt = 0x10, AcceptBroadcast = 0x08, AcceptMulticast = 0x04, - AcceptMyPhys = 0x02, - AcceptAllPhys = 0x01, + AcceptMyPhys = 0x02, + AcceptAllPhys = 0x01, }; /* Bits in TxConfig. */ enum tx_config_bits { - /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ - TxIFGShift = 24, - TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ - TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ - TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ - TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ + /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */ + TxIFGShift = 24, + TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */ + TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */ + TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */ + TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */ - TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ - TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ - TxClearAbt = (1 << 0), /* Clear abort (WO) */ - TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ - TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ + TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */ + TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */ + TxClearAbt = (1 << 0), /* Clear abort (WO) */ + TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */ + TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */ TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */ }; - /* Transmit Status of All Descriptors (TSAD) Register */ enum TSAD_bits { - TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3 - TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2 - TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1 - TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0 - TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3 - TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2 - TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1 - TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0 - TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3 - TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2 - TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1 - TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0 - TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3 - TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2 - TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1 - TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0 + TSAD_TOK3 = 1 << 15, // TOK bit of Descriptor 3 + TSAD_TOK2 = 1 << 14, // TOK bit of Descriptor 2 + TSAD_TOK1 = 1 << 13, // TOK bit of Descriptor 1 + TSAD_TOK0 = 1 << 12, // TOK bit of Descriptor 0 + TSAD_TUN3 = 1 << 11, // TUN bit of Descriptor 3 + TSAD_TUN2 = 1 << 10, // TUN bit of Descriptor 2 + TSAD_TUN1 = 1 << 9, // TUN bit of Descriptor 1 + TSAD_TUN0 = 1 << 8, // TUN bit of Descriptor 0 + TSAD_TABT3 = 1 << 07, // TABT bit of Descriptor 3 + TSAD_TABT2 = 1 << 06, // TABT bit of Descriptor 2 + TSAD_TABT1 = 1 << 05, // TABT bit of Descriptor 1 + TSAD_TABT0 = 1 << 04, // TABT bit of Descriptor 0 + TSAD_OWN3 = 1 << 03, // OWN bit of Descriptor 3 + TSAD_OWN2 = 1 << 02, // OWN bit of Descriptor 2 + TSAD_OWN1 = 1 << 01, // OWN bit of Descriptor 1 + TSAD_OWN0 = 1 << 00, // OWN bit of Descriptor 0 }; - /* Bits in Config1 */ enum Config1Bits { - Cfg1_PM_Enable = 0x01, - Cfg1_VPD_Enable = 0x02, - Cfg1_PIO = 0x04, - Cfg1_MMIO = 0x08, - LWAKE = 0x10, /* not on 8139, 8139A */ + Cfg1_PM_Enable = 0x01, + Cfg1_VPD_Enable = 0x02, + Cfg1_PIO = 0x04, + Cfg1_MMIO = 0x08, + LWAKE = 0x10, /* not on 8139, 8139A */ Cfg1_Driver_Load = 0x20, - Cfg1_LED0 = 0x40, - Cfg1_LED1 = 0x80, - SLEEP = (1 << 1), /* only on 8139, 8139A */ - PWRDN = (1 << 0), /* only on 8139, 8139A */ + Cfg1_LED0 = 0x40, + Cfg1_LED1 = 0x80, + SLEEP = (1 << 1), /* only on 8139, 8139A */ + PWRDN = (1 << 0), /* only on 8139, 8139A */ }; /* Bits in Config3 */ @@ -255,7 +256,7 @@ enum Config3Bits { /* Bits in Config4 */ enum Config4Bits { - LWPTN = (1 << 2), /* not on 8139, 8139A */ + LWPTN = (1 << 2), /* not on 8139, 8139A */ }; /* Bits in Config5 */ @@ -272,14 +273,14 @@ enum Config5Bits { enum RxConfigBits { /* rx fifo threshold */ RxCfgFIFOShift = 13, - RxCfgFIFONone = (7 << RxCfgFIFOShift), + RxCfgFIFONone = (7 << RxCfgFIFOShift), /* Max DMA burst */ - RxCfgDMAShift = 8, + RxCfgDMAShift = 8, RxCfgDMAUnlimited = (7 << RxCfgDMAShift), /* rx ring buffer length */ - RxCfgRcv8K = 0, + RxCfgRcv8K = 0, RxCfgRcv16K = (1 << 11), RxCfgRcv32K = (1 << 12), RxCfgRcv64K = (1 << 11) | (1 << 12), @@ -299,20 +300,20 @@ enum CSCRBits { CSCR_LinkDownCmd = 0x0f3c0, #endif enum CSCRBits { - CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ - CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ - CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ - CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ - CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ - CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ - CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ - CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ - CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/ + CSCR_Testfun = 1 << 15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */ + CSCR_LD = 1 << 9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/ + CSCR_HEART_BIT = 1 << 8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/ + CSCR_JBEN = 1 << 7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/ + CSCR_F_LINK_100 = 1 << 6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/ + CSCR_F_Connect = 1 << 5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/ + CSCR_Con_status = 1 << 3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/ + CSCR_Con_status_En = 1 << 2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/ + CSCR_PASS_SCR = 1 << 0, /* Bypass Scramble, def 0*/ }; enum Cfg9346Bits { - Cfg9346_Normal = 0x00, - Cfg9346_Autoload = 0x40, + Cfg9346_Normal = 0x00, + Cfg9346_Autoload = 0x40, Cfg9346_Programming = 0x80, Cfg9346_ConfigWrite = 0xC0, }; @@ -332,12 +333,12 @@ typedef enum { enum chip_flags { HasHltClk = (1 << 0), - HasLWake = (1 << 1), + HasLWake = (1 << 1), }; #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \ - (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22) -#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) + (b30 << 30 | b29 << 29 | b28 << 28 | b27 << 27 | b26 << 26 | b23 << 23 | b22 << 22) +#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1) #define RTL8139_PCI_REVID_8139 0x10 #define RTL8139_PCI_REVID_8139CPLUS 0x20 @@ -346,16 +347,16 @@ enum chip_flags { /* Size is 64 * 16bit words */ #define EEPROM_9346_ADDR_BITS 6 -#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) +#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS) #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1) enum Chip9346Operation { - Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ - Chip9346_op_read = 0x80, /* 10 AAAAAA */ - Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ - Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ - Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ - Chip9346_op_write_all = 0x10, /* 00 01zzzz */ + Chip9346_op_mask = 0xc0, /* 10 zzzzzz */ + Chip9346_op_read = 0x80, /* 10 AAAAAA */ + Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */ + Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */ + Chip9346_op_write_enable = 0x30, /* 00 11zzzz */ + Chip9346_op_write_all = 0x10, /* 00 01zzzz */ Chip9346_op_write_disable = 0x00, /* 00 00zzzz */ }; @@ -385,24 +386,24 @@ typedef struct EEprom9346 { #pragma pack(push, 1) typedef struct RTL8139TallyCounters { /* Tally counters */ - uint64_t TxOk; - uint64_t RxOk; - uint64_t TxERR; - uint32_t RxERR; - uint16_t MissPkt; - uint16_t FAE; - uint32_t Tx1Col; - uint32_t TxMCol; - uint64_t RxOkPhy; - uint64_t RxOkBrd; - uint32_t RxOkMul; - uint16_t TxAbt; - uint16_t TxUndrn; + uint64_t TxOk; + uint64_t RxOk; + uint64_t TxERR; + uint32_t RxERR; + uint16_t MissPkt; + uint16_t FAE; + uint32_t Tx1Col; + uint32_t TxMCol; + uint64_t RxOkPhy; + uint64_t RxOkBrd; + uint32_t RxOkMul; + uint16_t TxAbt; + uint16_t TxUndrn; } RTL8139TallyCounters; #pragma pack(pop) /* Clears all tally counters */ -static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters); +static void RTL8139TallyCounters_clear(RTL8139TallyCounters *counters); struct RTL8139State { /*< private >*/ @@ -432,15 +433,15 @@ struct RTL8139State { uint16_t CSCR; - uint8_t Cfg9346; - uint8_t Config0; - uint8_t Config1; - uint8_t Config3; - uint8_t Config4; - uint8_t Config5; + uint8_t Cfg9346; + uint8_t Config0; + uint8_t Config1; + uint8_t Config3; + uint8_t Config4; + uint8_t Config5; - uint8_t clock_enabled; - uint8_t bChipCmdState; + uint8_t clock_enabled; + uint8_t bChipCmdState; uint16_t MultiIntr; @@ -452,36 +453,36 @@ struct RTL8139State { uint16_t CpCmd; - uint8_t TxThresh; - uint8_t pci_latency; + uint8_t TxThresh; + uint8_t pci_latency; netcard_t *nic; /* C ring mode */ - uint32_t currTxDesc; + uint32_t currTxDesc; /* C+ mode */ - uint32_t cplus_enabled; + uint32_t cplus_enabled; - uint32_t currCPlusRxDesc; - uint32_t currCPlusTxDesc; + uint32_t currCPlusRxDesc; + uint32_t currCPlusTxDesc; - uint32_t RxRingAddrLO; - uint32_t RxRingAddrHI; + uint32_t RxRingAddrLO; + uint32_t RxRingAddrHI; EEprom9346 eeprom; - uint32_t TCTR; - uint32_t TimerInt; - int64_t TCTR_base; + uint32_t TCTR; + uint32_t TimerInt; + int64_t TCTR_base; /* Tally counters */ RTL8139TallyCounters tally_counters; /* Non-persistent data */ - uint8_t *cplus_txbuffer; - int cplus_txbuffer_len; - int cplus_txbuffer_offset; + uint8_t *cplus_txbuffer; + int cplus_txbuffer_len; + int cplus_txbuffer_offset; /* PCI interrupt timer */ pc_timer_t timer; @@ -500,34 +501,32 @@ prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) { DPRINTF("eeprom command 0x%02x\n", command); - switch (command & Chip9346_op_mask) - { + switch (command & Chip9346_op_mask) { case Chip9346_op_read: - { - eeprom->address = command & EEPROM_9346_ADDR_MASK; - eeprom->output = eeprom->contents[eeprom->address]; - eeprom->eedo = 0; - eeprom->tick = 0; - eeprom->mode = Chip9346_data_read; - DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", - eeprom->address, eeprom->output); - } - break; + { + eeprom->address = command & EEPROM_9346_ADDR_MASK; + eeprom->output = eeprom->contents[eeprom->address]; + eeprom->eedo = 0; + eeprom->tick = 0; + eeprom->mode = Chip9346_data_read; + DPRINTF("eeprom read from address 0x%02x data=0x%04x\n", + eeprom->address, eeprom->output); + } + break; case Chip9346_op_write: - { - eeprom->address = command & EEPROM_9346_ADDR_MASK; - eeprom->input = 0; - eeprom->tick = 0; - eeprom->mode = Chip9346_none; /* Chip9346_data_write */ - DPRINTF("eeprom begin write to address 0x%02x\n", - eeprom->address); - } - break; + { + eeprom->address = command & EEPROM_9346_ADDR_MASK; + eeprom->input = 0; + eeprom->tick = 0; + eeprom->mode = Chip9346_none; /* Chip9346_data_write */ + DPRINTF("eeprom begin write to address 0x%02x\n", + eeprom->address); + } + break; default: eeprom->mode = Chip9346_none; - switch (command & Chip9346_op_ext_mask) - { + switch (command & Chip9346_op_ext_mask) { case Chip9346_op_write_enable: DPRINTF("eeprom write enabled\n"); break; @@ -548,19 +547,18 @@ prom9346_decode_command(EEprom9346 *eeprom, uint8_t command) static void prom9346_shift_clock(EEprom9346 *eeprom) { - int bit = eeprom->eedi?1:0; + int bit = eeprom->eedi ? 1 : 0; - ++ eeprom->tick; + ++eeprom->tick; DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, - eeprom->eedo); + eeprom->eedo); - switch (eeprom->mode) - { + switch (eeprom->mode) { case Chip9346_enter_command_mode: if (bit) { - eeprom->mode = Chip9346_read_command; - eeprom->tick = 0; + eeprom->mode = Chip9346_read_command; + eeprom->tick = 0; eeprom->input = 0; DPRINTF("eeprom: +++ synchronized, begin command read\n"); } @@ -574,27 +572,27 @@ prom9346_shift_clock(EEprom9346 *eeprom) break; case Chip9346_data_read: - eeprom->eedo = (eeprom->output & 0x8000)?1:0; + eeprom->eedo = (eeprom->output & 0x8000) ? 1 : 0; eeprom->output <<= 1; if (eeprom->tick == 16) { #if 1 - // the FreeBSD drivers (rl and re) don't explicitly toggle - // CS between reads (or does setting Cfg9346 to 0 count too?), - // so we need to enter wait-for-command state here - eeprom->mode = Chip9346_enter_command_mode; - eeprom->input = 0; - eeprom->tick = 0; + // the FreeBSD drivers (rl and re) don't explicitly toggle + // CS between reads (or does setting Cfg9346 to 0 count too?), + // so we need to enter wait-for-command state here + eeprom->mode = Chip9346_enter_command_mode; + eeprom->input = 0; + eeprom->tick = 0; - DPRINTF("eeprom: +++ end of read, awaiting next command\n"); + DPRINTF("eeprom: +++ end of read, awaiting next command\n"); #else - // original behaviour - ++eeprom->address; - eeprom->address &= EEPROM_9346_ADDR_MASK; - eeprom->output = eeprom->contents[eeprom->address]; - eeprom->tick = 0; + // original behaviour + ++eeprom->address; + eeprom->address &= EEPROM_9346_ADDR_MASK; + eeprom->output = eeprom->contents[eeprom->address]; + eeprom->tick = 0; - DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", - eeprom->address, eeprom->output); + DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n", + eeprom->address, eeprom->output); #endif } break; @@ -603,12 +601,12 @@ prom9346_shift_clock(EEprom9346 *eeprom) eeprom->input = (eeprom->input << 1) | (bit & 1); if (eeprom->tick == 16) { DPRINTF("eeprom write to address 0x%02x data=0x%04x\n", - eeprom->address, eeprom->input); + eeprom->address, eeprom->input); eeprom->contents[eeprom->address] = eeprom->input; - eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ - eeprom->tick = 0; - eeprom->input = 0; + eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */ + eeprom->tick = 0; + eeprom->input = 0; } break; @@ -620,8 +618,8 @@ prom9346_shift_clock(EEprom9346 *eeprom) } DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input); - eeprom->mode = Chip9346_enter_command_mode; - eeprom->tick = 0; + eeprom->mode = Chip9346_enter_command_mode; + eeprom->tick = 0; eeprom->input = 0; } break; @@ -645,23 +643,23 @@ prom9346_get_wire(RTL8139State *s) static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi) { - EEprom9346 *eeprom = &s->eeprom; - uint8_t old_eecs = eeprom->eecs; - uint8_t old_eesk = eeprom->eesk; + EEprom9346 *eeprom = &s->eeprom; + uint8_t old_eecs = eeprom->eecs; + uint8_t old_eesk = eeprom->eesk; eeprom->eecs = eecs; eeprom->eesk = eesk; eeprom->eedi = eedi; DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs, - eeprom->eesk, eeprom->eedi, eeprom->eedo); + eeprom->eesk, eeprom->eedi, eeprom->eedo); if (!old_eecs && eecs) { /* Synchronize start */ - eeprom->tick = 0; - eeprom->input = 0; + eeprom->tick = 0; + eeprom->input = 0; eeprom->output = 0; - eeprom->mode = Chip9346_enter_command_mode; + eeprom->mode = Chip9346_enter_command_mode; DPRINTF("=== eeprom: begin access, enter command mode\n"); } @@ -681,11 +679,12 @@ static void rtl8139_update_irq(RTL8139State *s) { uint8_t d = s->pci_slot; - int isr; + int isr; + isr = (s->IntrStatus & s->IntrMask) & 0xffff; DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus, - s->IntrMask); + s->IntrMask); if (isr != 0) pci_set_irq(d, PCI_INTA, &s->irq_state); @@ -736,14 +735,14 @@ rtl8139_write_buffer(RTL8139State *s, const void *buf, int size) if (size > wrapped) { dma_bm_write(s->RxBuf + s->RxBufAddr, - buf, size-wrapped, 1); + buf, size - wrapped, 1); } /* reset buffer pointer */ s->RxBufAddr = 0; dma_bm_write(s->RxBuf + s->RxBufAddr, - buf + (size-wrapped), wrapped, 1); + buf + (size - wrapped), wrapped, 1); s->RxBufAddr = wrapped; @@ -843,21 +842,19 @@ net_crc32_le(const uint8_t *p, int len) return crc; } - #define ETH_ALEN 6 static int rtl8139_do_receive(void *priv, uint8_t *buf, int size_) { - RTL8139State *s = (RTL8139State*) priv; + RTL8139State *s = (RTL8139State *) priv; /* size is the length of the buffer passed to the driver */ - size_t size = size_; + size_t size = size_; const uint8_t *dot1q_buf = NULL; uint32_t packet_header = 0; - uint8_t buf1[60 + VLAN_HLEN]; + uint8_t buf1[60 + VLAN_HLEN]; - static const uint8_t broadcast_macaddr[6] = - { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + static const uint8_t broadcast_macaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; DPRINTF(">>> received len=%zu\n", size); @@ -883,10 +880,9 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) DPRINTF(">>> packet received in promiscuous mode\n"); } else { - if (!memcmp(buf, broadcast_macaddr, 6)) { + if (!memcmp(buf, broadcast_macaddr, 6)) { /* broadcast address */ - if (!(s->RxConfig & AcceptBroadcast)) - { + if (!(s->RxConfig & AcceptBroadcast)) { DPRINTF(">>> broadcast packet rejected\n"); /* update tally counter */ @@ -969,8 +965,7 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) } } - if (rtl8139_cp_receiver_enabled(s)) - { + if (rtl8139_cp_receiver_enabled(s)) { if (!rtl8139_cp_rx_valid(s)) { return size; } @@ -980,27 +975,30 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) /* begin C+ receiver mode */ /* w0 ownership flag */ -#define CP_RX_OWN (1<<31) +#define CP_RX_OWN (1 << 31) /* w0 end of ring flag */ -#define CP_RX_EOR (1<<30) +#define CP_RX_EOR (1 << 30) /* w0 bits 0...12 : buffer size */ -#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1) +#define CP_RX_BUFFER_SIZE_MASK ((1 << 13) - 1) /* w1 tag available flag */ -#define CP_RX_TAVA (1<<16) +#define CP_RX_TAVA (1 << 16) /* w1 bits 0...15 : VLAN tag */ -#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1) -/* w2 low 32bit of Rx buffer ptr */ -/* w3 high 32bit of Rx buffer ptr */ +#define CP_RX_VLAN_TAG_MASK ((1 << 16) - 1) + /* w2 low 32bit of Rx buffer ptr */ + /* w3 high 32bit of Rx buffer ptr */ - int descriptor = s->currCPlusRxDesc; + int descriptor = s->currCPlusRxDesc; uint32_t cplus_rx_ring_desc; cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI); cplus_rx_ring_desc += 16 * descriptor; DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at " - "%08x %08x = ""0x%8X""\n", descriptor, s->RxRingAddrHI, - s->RxRingAddrLO, cplus_rx_ring_desc); + "%08x %08x = " + "0x%8X" + "\n", + descriptor, s->RxRingAddrHI, + s->RxRingAddrLO, cplus_rx_ring_desc); uint32_t val; uint32_t rxdw0; @@ -1008,21 +1006,21 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) uint32_t rxbufLO; uint32_t rxbufHI; - dma_bm_read(cplus_rx_ring_desc, (uint8_t*)&val, 4, 4); + dma_bm_read(cplus_rx_ring_desc, (uint8_t *) &val, 4, 4); rxdw0 = val; - dma_bm_read(cplus_rx_ring_desc+4, (uint8_t*)&val, 4, 4); + dma_bm_read(cplus_rx_ring_desc + 4, (uint8_t *) &val, 4, 4); rxdw1 = val; - dma_bm_read(cplus_rx_ring_desc+8, (uint8_t*)&val, 4, 4); + dma_bm_read(cplus_rx_ring_desc + 8, (uint8_t *) &val, 4, 4); rxbufLO = val; - dma_bm_read(cplus_rx_ring_desc+12, (uint8_t*)&val, 4, 4); + dma_bm_read(cplus_rx_ring_desc + 12, (uint8_t *) &val, 4, 4); rxbufHI = val; DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n", - descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); + descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI); if (!(rxdw0 & CP_RX_OWN)) { DPRINTF("C+ Rx mode : descriptor %d is owned by host\n", - descriptor); + descriptor); s->IntrStatus |= RxOverflow; ++s->RxMissed; @@ -1038,8 +1036,7 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK; /* write VLAN info to descriptor variables. */ - if (s->CpCmd & CPlusRxVLAN && - bswap16(*((uint16_t*)&buf[ETH_ALEN * 2])) == 0x8100) { + if (s->CpCmd & CPlusRxVLAN && bswap16(*((uint16_t *) &buf[ETH_ALEN * 2])) == 0x8100) { dot1q_buf = &buf[ETH_ALEN * 2]; size -= VLAN_HLEN; /* if too small buffer, use the tailroom added duing expansion */ @@ -1049,10 +1046,11 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) rxdw1 &= ~CP_RX_VLAN_TAG_MASK; /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */ - rxdw1 |= CP_RX_TAVA | *((uint16_t*)(&dot1q_buf[ETHER_TYPE_LEN])); + rxdw1 |= CP_RX_TAVA | *((uint16_t *) (&dot1q_buf[ETHER_TYPE_LEN])); - DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n", - bswap16(*((uint16_t*)&dot1q_buf[ETHER_TYPE_LEN]))); + DPRINTF("C+ Rx mode : extracted vlan tag with tci: " + "%u\n", + bswap16(*((uint16_t *) &dot1q_buf[ETHER_TYPE_LEN]))); } else { /* reset VLAN tag flag */ rxdw1 &= ~CP_RX_TAVA; @@ -1060,9 +1058,9 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) /* TODO: scatter the packet over available receive ring descriptors space */ - if (size+4 > rx_space) { + if (size + 4 > rx_space) { DPRINTF("C+ Rx mode : descriptor %d size %d received %zu + 4\n", - descriptor, rx_space, size); + descriptor, rx_space, size); s->IntrStatus |= RxOverflow; ++s->RxMissed; @@ -1081,8 +1079,8 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) if (dot1q_buf) { dma_bm_write(rx_addr, buf, 2 * ETH_ALEN, 1); dma_bm_write(rx_addr + 2 * ETH_ALEN, - buf + 2 * ETH_ALEN + VLAN_HLEN, - size - 2 * ETH_ALEN, 1); + buf + 2 * ETH_ALEN + VLAN_HLEN, + size - 2 * ETH_ALEN, 1); } else { dma_bm_write(rx_addr, buf, size, 1); } @@ -1093,28 +1091,28 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) /* write checksum */ val = (net_crc32_le(buf, size_)); - dma_bm_write(rx_addr+size, (uint8_t *)&val, 4, 4); + dma_bm_write(rx_addr + size, (uint8_t *) &val, 4, 4); /* first segment of received packet flag */ -#define CP_RX_STATUS_FS (1<<29) +#define CP_RX_STATUS_FS (1 << 29) /* last segment of received packet flag */ -#define CP_RX_STATUS_LS (1<<28) +#define CP_RX_STATUS_LS (1 << 28) /* multicast packet flag */ -#define CP_RX_STATUS_MAR (1<<26) +#define CP_RX_STATUS_MAR (1 << 26) /* physical-matching packet flag */ -#define CP_RX_STATUS_PAM (1<<25) +#define CP_RX_STATUS_PAM (1 << 25) /* broadcast packet flag */ -#define CP_RX_STATUS_BAR (1<<24) +#define CP_RX_STATUS_BAR (1 << 24) /* runt packet flag */ -#define CP_RX_STATUS_RUNT (1<<19) +#define CP_RX_STATUS_RUNT (1 << 19) /* crc error flag */ -#define CP_RX_STATUS_CRC (1<<18) +#define CP_RX_STATUS_CRC (1 << 18) /* IP checksum error flag */ -#define CP_RX_STATUS_IPF (1<<15) +#define CP_RX_STATUS_IPF (1 << 15) /* UDP checksum error flag */ -#define CP_RX_STATUS_UDPF (1<<14) +#define CP_RX_STATUS_UDPF (1 << 14) /* TCP checksum error flag */ -#define CP_RX_STATUS_TCPF (1<<13) +#define CP_RX_STATUS_TCPF (1 << 13) /* transfer ownership to target */ rxdw0 &= ~CP_RX_OWN; @@ -1135,13 +1133,13 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) /* set received size */ rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK; - rxdw0 |= (size+4); + rxdw0 |= (size + 4); /* update ring data */ val = rxdw0; - dma_bm_write(cplus_rx_ring_desc, (uint8_t *)&val, 4, 4); + dma_bm_write(cplus_rx_ring_desc, (uint8_t *) &val, 4, 4); val = rxdw1; - dma_bm_write(cplus_rx_ring_desc+4, (uint8_t *)&val, 4, 4); + dma_bm_write(cplus_rx_ring_desc + 4, (uint8_t *) &val, 4, 4); /* update tally counter */ ++s->tally_counters.RxOk; @@ -1167,8 +1165,8 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) if (avail != 0 && RX_ALIGN(size + 8) >= avail) { DPRINTF("rx overflow: rx buffer length %d head 0x%04x " - "read 0x%04x === available 0x%04x need 0x%04zx\n", - s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); + "read 0x%04x === available 0x%04x need 0x%04zx\n", + s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8); s->IntrStatus |= RxOverflow; ++s->RxMissed; @@ -1178,18 +1176,18 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) packet_header |= RxStatusOK; - packet_header |= (((size+4) << 16) & 0xffff0000); + packet_header |= (((size + 4) << 16) & 0xffff0000); /* write header */ uint32_t val = packet_header; - rtl8139_write_buffer(s, (uint8_t *)&val, 4); + rtl8139_write_buffer(s, (uint8_t *) &val, 4); rtl8139_write_buffer(s, buf, size); /* write checksum */ val = (net_crc32_le(buf, size)); - rtl8139_write_buffer(s, (uint8_t *)&val, 4); + rtl8139_write_buffer(s, (uint8_t *) &val, 4); /* correct buffer write pointer */ s->RxBufAddr = MOD2(RX_ALIGN(s->RxBufAddr), s->RxBufferSize); @@ -1197,7 +1195,7 @@ rtl8139_do_receive(void *priv, uint8_t *buf, int size_) /* now we can signal we have received something */ DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n", - s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); + s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); } s->IntrStatus |= RxOK; @@ -1213,14 +1211,14 @@ static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize) { s->RxBufferSize = bufferSize; - s->RxBufPtr = 0; - s->RxBufAddr = 0; + s->RxBufPtr = 0; + s->RxBufAddr = 0; } static void rtl8139_reset_phy(RTL8139State *s) { - s->BasicModeStatus = 0x7809; + s->BasicModeStatus = 0x7809; s->BasicModeStatus |= 0x0020; /* autonegotiation completed */ /* preserve link state */ s->BasicModeStatus |= (net_cards_conf[s->nic->card_num].link_state & NET_LINK_DOWN) ? 0 : 0x04; @@ -1232,15 +1230,14 @@ rtl8139_reset_phy(RTL8139State *s) s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD; } - static void -rtl8139_reset(void* priv) +rtl8139_reset(void *priv) { - RTL8139State *s = (RTL8139State*) priv; + RTL8139State *s = (RTL8139State *) priv; /* reset interrupt mask */ s->IntrStatus = 0; - s->IntrMask = 0; + s->IntrMask = 0; rtl8139_update_irq(s); @@ -1249,7 +1246,7 @@ rtl8139_reset(void* priv) s->TxStatus[i] = TxHostOwns; } - s->currTxDesc = 0; + s->currTxDesc = 0; s->currCPlusRxDesc = 0; s->currCPlusTxDesc = 0; @@ -1279,7 +1276,7 @@ rtl8139_reset(void* priv) s->Config3 = 0x1; /* fast back-to-back compatible */ s->Config5 = 0x0; - s->CpCmd = 0x0; /* reset C+ mode */ + s->CpCmd = 0x0; /* reset C+ mode */ s->cplus_enabled = 0; #if 0 @@ -1291,8 +1288,8 @@ rtl8139_reset(void* priv) rtl8139_reset_phy(s); /* also reset timer and disable timer interrupt */ - s->TCTR = 0; - s->TimerInt = 0; + s->TCTR = 0; + s->TimerInt = 0; s->TCTR_base = 0; #if 0 rtl8139_set_next_tctr_time(s); @@ -1303,20 +1300,20 @@ rtl8139_reset(void* priv) } static void -RTL8139TallyCounters_clear(RTL8139TallyCounters* counters) +RTL8139TallyCounters_clear(RTL8139TallyCounters *counters) { - counters->TxOk = 0; - counters->RxOk = 0; - counters->TxERR = 0; - counters->RxERR = 0; + counters->TxOk = 0; + counters->RxOk = 0; + counters->TxERR = 0; + counters->RxERR = 0; counters->MissPkt = 0; - counters->FAE = 0; - counters->Tx1Col = 0; - counters->TxMCol = 0; + counters->FAE = 0; + counters->Tx1Col = 0; + counters->TxMCol = 0; counters->RxOkPhy = 0; counters->RxOkBrd = 0; counters->RxOkMul = 0; - counters->TxAbt = 0; + counters->TxAbt = 0; counters->TxUndrn = 0; } @@ -1325,7 +1322,7 @@ RTL8139TallyCounters_dma_write(RTL8139State *s, uint32_t tc_addr) { RTL8139TallyCounters *tally_counters = &s->tally_counters; - dma_bm_write(tc_addr, (uint8_t*)tally_counters, sizeof(RTL8139TallyCounters), 1); + dma_bm_write(tc_addr, (uint8_t *) tally_counters, sizeof(RTL8139TallyCounters), 1); } static void @@ -1510,14 +1507,14 @@ rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val) /* mask unwritable bits */ val = SET_MASKED(val, 0x31, s->Cfg9346); - uint32_t opmode = val & 0xc0; + uint32_t opmode = val & 0xc0; uint32_t eeprom_val = val & 0xf; if (opmode == 0x80) { /* eeprom access */ - int eecs = (eeprom_val & 0x08)?1:0; - int eesk = (eeprom_val & 0x04)?1:0; - int eedi = (eeprom_val & 0x02)?1:0; + int eecs = (eeprom_val & 0x08) ? 1 : 0; + int eesk = (eeprom_val & 0x04) ? 1 : 0; + int eedi = (eeprom_val & 0x02) ? 1 : 0; prom9346_set_wire(s, eecs, eesk, eedi); } else if (opmode == 0x40) { /* Reset. */ @@ -1539,7 +1536,7 @@ rtl8139_Cfg9346_read(RTL8139State *s) /* eeprom access */ int eedo = prom9346_get_wire(s); if (eedo) { - ret |= 0x01; + ret |= 0x01; } else { ret &= ~0x01; } @@ -1747,23 +1744,22 @@ rtl8139_RxConfig_read(RTL8139State *s) void rtl8139_network_rx_put(netcard_t *card, uint8_t *bufp, int len) { - (void)network_rx_put(card, bufp, len); + (void) network_rx_put(card, bufp, len); } static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, - UNUSED(int do_interrupt), const uint8_t *dot1q_buf) + UNUSED(int do_interrupt), const uint8_t *dot1q_buf) { void (*network_func)(netcard_t *, uint8_t *, int) = (TxLoopBack == (s->TxConfig & TxLoopBack)) ? rtl8139_network_rx_put : network_tx; - if (!size) - { + if (!size) { DPRINTF("+++ empty ethernet frame\n"); return; } if (dot1q_buf && size >= ETH_ALEN * 2) { network_func(s->nic, buf, ETH_ALEN * 2); - network_func(s->nic, (uint8_t*)dot1q_buf, VLAN_HLEN ); + network_func(s->nic, (uint8_t *) dot1q_buf, VLAN_HLEN); network_func(s->nic, buf + ETH_ALEN * 2, size - ETH_ALEN * 2); return; } @@ -1775,25 +1771,27 @@ rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size, static int rtl8139_transmit_one(RTL8139State *s, int descriptor) { - int txsize = s->TxStatus[descriptor] & 0x1fff; + int txsize = s->TxStatus[descriptor] & 0x1fff; uint8_t txbuffer[0x2000]; if (!rtl8139_transmitter_enabled(s)) { DPRINTF("+++ cannot transmit from descriptor %d: transmitter " - "disabled\n", descriptor); + "disabled\n", + descriptor); return 0; } if (s->TxStatus[descriptor] & TxHostOwns) { DPRINTF("+++ cannot transmit from descriptor %d: owned by host " - "(%08x)\n", descriptor, s->TxStatus[descriptor]); + "(%08x)\n", + descriptor, s->TxStatus[descriptor]); return 0; } DPRINTF("+++ transmitting from descriptor %d\n", descriptor); DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n", - txsize, s->TxAddr[descriptor]); + txsize, s->TxAddr[descriptor]); dma_bm_read(s->TxAddr[descriptor], txbuffer, txsize, 1); @@ -1804,7 +1802,7 @@ rtl8139_transmit_one(RTL8139State *s, int descriptor) rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL); DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize, - descriptor); + descriptor); /* update interrupt */ s->IntrStatus |= TxOK; @@ -1821,17 +1819,17 @@ ones_complement_sum(uint8_t *data, size_t len) { uint32_t result = 0; - for (; len > 1; data+=2, len-=2) { - result += *(uint16_t*)data; + for (; len > 1; data += 2, len -= 2) { + result += *(uint16_t *) data; } /* add the remainder byte */ if (len) { - uint8_t odd[2] = {*data, 0}; - result += *(uint16_t*)odd; + uint8_t odd[2] = { *data, 0 }; + result += *(uint16_t *) odd; } - while (result>>16) + while (result >> 16) result = (result & 0xffff) + (result >> 16); return result; @@ -1840,7 +1838,7 @@ ones_complement_sum(uint8_t *data, size_t len) static uint16_t ip_checksum(void *data, size_t len) { - return ~ones_complement_sum((uint8_t*)data, len); + return ~ones_complement_sum((uint8_t *) data, len); } /* TODO: Replace these with equivalents in 86Box if applicable. */ @@ -1857,15 +1855,15 @@ struct ip_header { }; typedef struct tcp_header { - uint16_t th_sport; /* source port */ - uint16_t th_dport; /* destination port */ - uint32_t th_seq; /* sequence number */ - uint32_t th_ack; /* acknowledgment number */ - uint16_t th_offset_flags; /* data offset, reserved 6 bits, */ - /* TCP protocol flags */ - uint16_t th_win; /* window */ - uint16_t th_sum; /* checksum */ - uint16_t th_urp; /* urgent pointer */ + uint16_t th_sport; /* source port */ + uint16_t th_dport; /* destination port */ + uint32_t th_seq; /* sequence number */ + uint32_t th_ack; /* acknowledgment number */ + uint16_t th_offset_flags; /* data offset, reserved 6 bits, */ + /* TCP protocol flags */ + uint16_t th_win; /* window */ + uint16_t th_sum; /* checksum */ + uint16_t th_urp; /* urgent pointer */ } tcp_header; typedef struct ip_pseudo_header { @@ -1883,24 +1881,23 @@ typedef struct udp_header { uint16_t uh_sum; /* udp checksum */ } udp_header; -#define ETH_HLEN 14 -#define ETH_P_IP (0x0800) -#define IP_PROTO_TCP (6) -#define IP_PROTO_UDP (17) +#define ETH_HLEN 14 +#define ETH_P_IP (0x0800) +#define IP_PROTO_TCP (6) +#define IP_PROTO_UDP (17) #define IP_HEADER_VERSION_4 (4) -#define TH_PUSH 0x08 -#define TH_FIN 0x01 +#define TH_PUSH 0x08 +#define TH_FIN 0x01 -#define IP_HDR_GET_LEN(p) \ - ((*(uint8_t*)((p + __builtin_offsetof(struct ip_header, ip_ver_len))) & 0x0F) << 2) +#define IP_HDR_GET_LEN(p) \ + ((*(uint8_t *) ((p + __builtin_offsetof(struct ip_header, ip_ver_len))) & 0x0F) << 2) -#define IP_HEADER_VERSION(ip) \ +#define IP_HEADER_VERSION(ip) \ (((ip)->ip_ver_len >> 4) & 0xf) #define TCP_HEADER_DATA_OFFSET(tcp) \ (((be16_to_cpu((tcp)->th_offset_flags) >> 12) & 0xf) << 2) - static int rtl8139_cplus_transmit_one(RTL8139State *s) { @@ -1911,7 +1908,7 @@ rtl8139_cplus_transmit_one(RTL8139State *s) if (!rtl8139_cp_transmitter_enabled(s)) { DPRINTF("+++ C+ mode: C+ transmitter disabled\n"); - return 0 ; + return 0; } int descriptor = s->currCPlusTxDesc; @@ -1921,8 +1918,9 @@ rtl8139_cplus_transmit_one(RTL8139State *s) cplus_tx_ring_desc += 16 * descriptor; DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at " - "%08x %08x = 0x%08X\n", descriptor, s->TxAddr[1], - s->TxAddr[0], cplus_tx_ring_desc); + "%08x %08x = 0x%08X\n", + descriptor, s->TxAddr[1], + s->TxAddr[0], cplus_tx_ring_desc); uint32_t val; uint32_t txdw0; @@ -1930,104 +1928,108 @@ rtl8139_cplus_transmit_one(RTL8139State *s) uint32_t txbufLO; uint32_t txbufHI; - dma_bm_read(cplus_tx_ring_desc, (uint8_t *)&val, 4, 4); + dma_bm_read(cplus_tx_ring_desc, (uint8_t *) &val, 4, 4); txdw0 = le32_to_cpu(val); - dma_bm_read(cplus_tx_ring_desc+4, (uint8_t *)&val, 4, 4); + dma_bm_read(cplus_tx_ring_desc + 4, (uint8_t *) &val, 4, 4); txdw1 = le32_to_cpu(val); - dma_bm_read(cplus_tx_ring_desc+8, (uint8_t *)&val, 4, 4); + dma_bm_read(cplus_tx_ring_desc + 8, (uint8_t *) &val, 4, 4); txbufLO = le32_to_cpu(val); - dma_bm_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4, 4); + dma_bm_read(cplus_tx_ring_desc + 12, (uint8_t *) &val, 4, 4); txbufHI = le32_to_cpu(val); DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor, - txdw0, txdw1, txbufLO, txbufHI); + txdw0, txdw1, txbufLO, txbufHI); /* w0 ownership flag */ -#define CP_TX_OWN (1<<31) +#define CP_TX_OWN (1 << 31) /* w0 end of ring flag */ -#define CP_TX_EOR (1<<30) +#define CP_TX_EOR (1 << 30) /* first segment of received packet flag */ -#define CP_TX_FS (1<<29) +#define CP_TX_FS (1 << 29) /* last segment of received packet flag */ -#define CP_TX_LS (1<<28) +#define CP_TX_LS (1 << 28) /* large send packet flag */ -#define CP_TX_LGSEN (1<<27) +#define CP_TX_LGSEN (1 << 27) /* large send MSS mask, bits 16...26 */ #define CP_TC_LGSEN_MSS_SHIFT 16 -#define CP_TC_LGSEN_MSS_MASK ((1 << 11) - 1) +#define CP_TC_LGSEN_MSS_MASK ((1 << 11) - 1) /* IP checksum offload flag */ -#define CP_TX_IPCS (1<<18) +#define CP_TX_IPCS (1 << 18) /* UDP checksum offload flag */ -#define CP_TX_UDPCS (1<<17) +#define CP_TX_UDPCS (1 << 17) /* TCP checksum offload flag */ -#define CP_TX_TCPCS (1<<16) +#define CP_TX_TCPCS (1 << 16) /* w0 bits 0...15 : buffer size */ -#define CP_TX_BUFFER_SIZE (1<<16) +#define CP_TX_BUFFER_SIZE (1 << 16) #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1) /* w1 add tag flag */ -#define CP_TX_TAGC (1<<17) +#define CP_TX_TAGC (1 << 17) /* w1 bits 0...15 : VLAN tag (big endian) */ -#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1) +#define CP_TX_VLAN_TAG_MASK ((1 << 16) - 1) /* w2 low 32bit of Rx buffer ptr */ /* w3 high 32bit of Rx buffer ptr */ /* set after transmission */ /* FIFO underrun flag */ -#define CP_TX_STATUS_UNF (1<<25) +#define CP_TX_STATUS_UNF (1 << 25) /* transmit error summary flag, valid if set any of three below */ -#define CP_TX_STATUS_TES (1<<23) +#define CP_TX_STATUS_TES (1 << 23) /* out-of-window collision flag */ -#define CP_TX_STATUS_OWC (1<<22) +#define CP_TX_STATUS_OWC (1 << 22) /* link failure flag */ -#define CP_TX_STATUS_LNKF (1<<21) +#define CP_TX_STATUS_LNKF (1 << 21) /* excessive collisions flag */ -#define CP_TX_STATUS_EXC (1<<20) +#define CP_TX_STATUS_EXC (1 << 20) if (!(txdw0 & CP_TX_OWN)) { DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor); - return 0 ; + return 0; } DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor); if (txdw0 & CP_TX_FS) { DPRINTF("+++ C+ Tx mode : descriptor %d is first segment " - "descriptor\n", descriptor); + "descriptor\n", + descriptor); /* reset internal buffer offset */ s->cplus_txbuffer_offset = 0; } - int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; + int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK; uint32_t tx_addr = rtl8139_addr64(txbufLO, txbufHI); /* make sure we have enough space to assemble the packet */ if (!s->cplus_txbuffer) { - s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; - s->cplus_txbuffer = calloc(s->cplus_txbuffer_len, 1); + s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE; + s->cplus_txbuffer = calloc(s->cplus_txbuffer_len, 1); s->cplus_txbuffer_offset = 0; DPRINTF("+++ C+ mode transmission buffer allocated space %d\n", - s->cplus_txbuffer_len); + s->cplus_txbuffer_len); } if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len) { /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */ txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset; DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor" - "length to %d\n", txsize); + "length to %d\n", + txsize); } /* append more data to the packet */ DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at " - "%08X"" to offset %d\n", txsize, tx_addr, + "%08X" + " to offset %d\n", + txsize, tx_addr, s->cplus_txbuffer_offset); dma_bm_read(tx_addr, - s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize, 1); + s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize, 1); s->cplus_txbuffer_offset += txsize; /* seek to next Rx descriptor */ @@ -2054,30 +2056,31 @@ rtl8139_cplus_transmit_one(RTL8139State *s) /* update ring data */ val = cpu_to_le32(tx_status); - dma_bm_write(cplus_tx_ring_desc, (uint8_t *)&val, 4, 4); + dma_bm_write(cplus_tx_ring_desc, (uint8_t *) &val, 4, 4); /* Now decide if descriptor being processed is holding the last segment of packet */ if (txdw0 & CP_TX_LS) { - uint8_t dot1q_buffer_space[VLAN_HLEN]; + uint8_t dot1q_buffer_space[VLAN_HLEN]; uint16_t *dot1q_buffer; DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n", - descriptor); + descriptor); /* can transfer fully assembled packet */ - uint8_t *saved_buffer = s->cplus_txbuffer; - int saved_size = s->cplus_txbuffer_offset; + uint8_t *saved_buffer = s->cplus_txbuffer; + int saved_size = s->cplus_txbuffer_offset; int saved_buffer_len = s->cplus_txbuffer_len; /* create vlan tag */ if (txdw1 & CP_TX_TAGC) { /* the vlan tag is in BE byte order in the descriptor * BE + le_to_cpu() + ~swap()~ = cpu */ - DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n", - bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); + DPRINTF("+++ C+ Tx mode : inserting vlan tag with " + "tci: %u\n", + bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)); - dot1q_buffer = (uint16_t *) dot1q_buffer_space; + dot1q_buffer = (uint16_t *) dot1q_buffer_space; dot1q_buffer[0] = cpu_to_be16(0x8100); /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */ dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK); @@ -2086,9 +2089,9 @@ rtl8139_cplus_transmit_one(RTL8139State *s) } /* reset the card space to protect from recursive call */ - s->cplus_txbuffer = NULL; + s->cplus_txbuffer = NULL; s->cplus_txbuffer_offset = 0; - s->cplus_txbuffer_len = 0; + s->cplus_txbuffer_len = 0; if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN)) { DPRINTF("+++ C+ mode offloaded task checksum\n"); @@ -2099,15 +2102,15 @@ rtl8139_cplus_transmit_one(RTL8139State *s) } /* ip packet header */ - struct ip_header *ip = NULL; - int hlen = 0; - uint8_t ip_protocol = 0; - uint16_t ip_data_len = 0; + struct ip_header *ip = NULL; + int hlen = 0; + uint8_t ip_protocol = 0; + uint16_t ip_data_len = 0; uint8_t *eth_payload_data = NULL; size_t eth_payload_len = 0; - int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12)); + int proto = be16_to_cpu(*(uint16_t *) (saved_buffer + 12)); if (proto != ETH_P_IP) { goto skip_offload; } @@ -2120,14 +2123,15 @@ rtl8139_cplus_transmit_one(RTL8139State *s) * unaligned accesses. */ eth_payload_data = saved_buffer + ETH_HLEN; - eth_payload_len = saved_size - ETH_HLEN; + eth_payload_len = saved_size - ETH_HLEN; - ip = (struct ip_header*)eth_payload_data; + ip = (struct ip_header *) eth_payload_data; if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) { DPRINTF("+++ C+ mode packet has bad IP version %d " - "expected %d\n", IP_HEADER_VERSION(ip), - IP_HEADER_VERSION_4); + "expected %d\n", + IP_HEADER_VERSION(ip), + IP_HEADER_VERSION_4); goto skip_offload; } @@ -2150,7 +2154,7 @@ rtl8139_cplus_transmit_one(RTL8139State *s) ip->ip_sum = 0; ip->ip_sum = ip_checksum(ip, hlen); DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n", - hlen, ip->ip_sum); + hlen, ip->ip_sum); } if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP) { @@ -2159,15 +2163,14 @@ rtl8139_cplus_transmit_one(RTL8139State *s) goto skip_offload; } - int large_send_mss = (txdw0 >> CP_TC_LGSEN_MSS_SHIFT) & - CP_TC_LGSEN_MSS_MASK; + int large_send_mss = (txdw0 >> CP_TC_LGSEN_MSS_SHIFT) & CP_TC_LGSEN_MSS_MASK; if (large_send_mss == 0) { goto skip_offload; } DPRINTF("+++ C+ mode offloaded task TSO IP data %d " - "frame data %d specified MSS=%d\n", - ip_data_len, saved_size - ETH_HLEN, large_send_mss); + "frame data %d specified MSS=%d\n", + ip_data_len, saved_size - ETH_HLEN, large_send_mss); /* maximum IP header length is 60 bytes */ uint8_t saved_ip_header[60]; @@ -2176,13 +2179,13 @@ rtl8139_cplus_transmit_one(RTL8139State *s) memcpy(saved_ip_header, eth_payload_data, hlen); /* a placeholder for checksum calculation routine in tcp case */ - uint8_t *data_to_checksum = eth_payload_data + hlen - 12; + uint8_t *data_to_checksum = eth_payload_data + hlen - 12; #if 0 size_t data_to_checksum_len = eth_payload_len - hlen + 12; #endif /* pointer to TCP header */ - tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen); + tcp_header *p_tcp_hdr = (tcp_header *) (eth_payload_data + hlen); int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr); @@ -2194,7 +2197,8 @@ rtl8139_cplus_transmit_one(RTL8139State *s) int tcp_data_len = ip_data_len - tcp_hlen; DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP " - "data len %d\n", ip_data_len, tcp_hlen, tcp_data_len); + "data len %d\n", + ip_data_len, tcp_hlen, tcp_data_len); /* note the cycle below overwrites IP header data, but restores it from saved_ip_header before sending packet */ @@ -2207,25 +2211,25 @@ rtl8139_cplus_transmit_one(RTL8139State *s) /* check if this is the last frame */ if (tcp_send_offset + large_send_mss >= tcp_data_len) { is_last_frame = 1; - chunk_size = tcp_data_len - tcp_send_offset; + chunk_size = tcp_data_len - tcp_send_offset; } - //DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", - // ldl_be_p(&p_tcp_hdr->th_seq)); + // DPRINTF("+++ C+ mode TSO TCP seqno %08x\n", + // ldl_be_p(&p_tcp_hdr->th_seq)); /* add 4 TCP pseudoheader fields */ /* copy IP source and destination fields */ memcpy(data_to_checksum, saved_ip_header + 12, 8); DPRINTF("+++ C+ mode TSO calculating TCP checksum for " - "packet with %d bytes data\n", tcp_hlen + - chunk_size); + "packet with %d bytes data\n", + tcp_hlen + chunk_size); if (tcp_send_offset) { - memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); + memcpy((uint8_t *) p_tcp_hdr + tcp_hlen, (uint8_t *) p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size); } -#define TCP_FLAGS_ONLY(flags) ((flags) & 0x3f) +#define TCP_FLAGS_ONLY(flags) ((flags) &0x3f) #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off))) /* keep PUSH and FIN flags only for the last frame */ if (!is_last_frame) { @@ -2233,16 +2237,16 @@ rtl8139_cplus_transmit_one(RTL8139State *s) } /* recalculate TCP checksum */ - ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; - p_tcpip_hdr->zeros = 0; - p_tcpip_hdr->ip_proto = IP_PROTO_TCP; - p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); + ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *) data_to_checksum; + p_tcpip_hdr->zeros = 0; + p_tcpip_hdr->ip_proto = IP_PROTO_TCP; + p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size); p_tcp_hdr->th_sum = 0; int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12); DPRINTF("+++ C+ mode TSO TCP checksum %04x\n", - tcp_checksum); + tcp_checksum); p_tcp_hdr->th_sum = tcp_checksum; @@ -2253,18 +2257,20 @@ rtl8139_cplus_transmit_one(RTL8139State *s) ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size); /* increment IP id for subsequent frames */ - ip->ip_id = cpu_to_be16(tcp_send_offset/large_send_mss + be16_to_cpu(ip->ip_id)); + ip->ip_id = cpu_to_be16(tcp_send_offset / large_send_mss + be16_to_cpu(ip->ip_id)); ip->ip_sum = 0; ip->ip_sum = ip_checksum(eth_payload_data, hlen); DPRINTF("+++ C+ mode TSO IP header len=%d " - "checksum=%04x\n", hlen, ip->ip_sum); + "checksum=%04x\n", + hlen, ip->ip_sum); int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size; DPRINTF("+++ C+ mode TSO transferring packet size " - "%d\n", tso_send_size); + "%d\n", + tso_send_size); rtl8139_transfer_frame(s, saved_buffer, tso_send_size, - 0, (uint8_t *) dot1q_buffer); + 0, (uint8_t *) dot1q_buffer); /* add transferred count to TCP sequence number */ #if 0 @@ -2276,14 +2282,14 @@ rtl8139_cplus_transmit_one(RTL8139State *s) /* Stop sending this frame */ saved_size = 0; - } else if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))) { + } else if (!(txdw0 & CP_TX_LGSEN) && (txdw0 & (CP_TX_TCPCS | CP_TX_UDPCS))) { DPRINTF("+++ C+ mode need TCP or UDP checksum\n"); /* maximum IP header length is 60 bytes */ uint8_t saved_ip_header[60]; memcpy(saved_ip_header, eth_payload_data, hlen); - uint8_t *data_to_checksum = eth_payload_data + hlen - 12; + uint8_t *data_to_checksum = eth_payload_data + hlen - 12; #if 0 size_t data_to_checksum_len = eth_payload_len - hlen + 12; #endif @@ -2294,38 +2300,40 @@ rtl8139_cplus_transmit_one(RTL8139State *s) if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP) { DPRINTF("+++ C+ mode calculating TCP checksum for " - "packet with %d bytes data\n", ip_data_len); + "packet with %d bytes data\n", + ip_data_len); - ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum; - p_tcpip_hdr->zeros = 0; - p_tcpip_hdr->ip_proto = IP_PROTO_TCP; - p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); + ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *) data_to_checksum; + p_tcpip_hdr->zeros = 0; + p_tcpip_hdr->ip_proto = IP_PROTO_TCP; + p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len); - tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12); + tcp_header *p_tcp_hdr = (tcp_header *) (data_to_checksum + 12); p_tcp_hdr->th_sum = 0; int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); DPRINTF("+++ C+ mode TCP checksum %04x\n", - tcp_checksum); + tcp_checksum); p_tcp_hdr->th_sum = tcp_checksum; } else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP) { DPRINTF("+++ C+ mode calculating UDP checksum for " - "packet with %d bytes data\n", ip_data_len); + "packet with %d bytes data\n", + ip_data_len); - ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum; - p_udpip_hdr->zeros = 0; - p_udpip_hdr->ip_proto = IP_PROTO_UDP; - p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); + ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *) data_to_checksum; + p_udpip_hdr->zeros = 0; + p_udpip_hdr->ip_proto = IP_PROTO_UDP; + p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len); - udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12); + udp_header *p_udp_hdr = (udp_header *) (data_to_checksum + 12); p_udp_hdr->uh_sum = 0; int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12); DPRINTF("+++ C+ mode UDP checksum %04x\n", - udp_checksum); + udp_checksum); p_udp_hdr->uh_sum = udp_checksum; } @@ -2342,7 +2350,7 @@ skip_offload: DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size); rtl8139_transfer_frame(s, saved_buffer, saved_size, 1, - (uint8_t *) dot1q_buffer); + (uint8_t *) dot1q_buffer); /* restore card space if there was no recursion and reset offset */ if (!s->cplus_txbuffer) { @@ -2371,7 +2379,7 @@ rtl8139_cplus_transmit(RTL8139State *s) /* Mark transfer completed */ if (!txcount) { DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n", - s->currCPlusTxDesc); + s->currCPlusTxDesc); } else { /* update interrupt status */ s->IntrStatus |= TxOK; @@ -2383,7 +2391,7 @@ static void rtl8139_transmit(RTL8139State *s) { int descriptor = s->currTxDesc; - int txcount = 0; + int txcount = 0; /*while*/ if (rtl8139_transmit_one(s, descriptor)) { @@ -2395,21 +2403,21 @@ rtl8139_transmit(RTL8139State *s) /* Mark transfer completed */ if (!txcount) { DPRINTF("transmitter queue stalled, current TxDesc = %d\n", - s->currTxDesc); + s->currTxDesc); } } - static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) { - int descriptor = txRegOffset/4; + int descriptor = txRegOffset / 4; /* handle C+ transmit mode register configuration */ if (s->cplus_enabled) { DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x " - "descriptor=%d\n", txRegOffset, val, descriptor); + "descriptor=%d\n", + txRegOffset, val, descriptor); /* handle Dump Tally Counters command */ s->TxStatus[descriptor] = val; @@ -2428,7 +2436,7 @@ rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) } DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", - txRegOffset, val, descriptor); + txRegOffset, val, descriptor); /* mask only reserved bits */ val &= ~0xff00c000; /* these bits are reset on write */ @@ -2442,16 +2450,17 @@ rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val) static uint32_t rtl8139_TxStatus_TxAddr_read(UNUSED(RTL8139State *s), uint32_t regs[], - uint32_t base, uint8_t addr, - int size) + uint32_t base, uint8_t addr, + int size) { - uint32_t reg = (addr - base) / 4; + uint32_t reg = (addr - base) / 4; uint32_t offset = addr & 0x3; - uint32_t ret = 0; + uint32_t ret = 0; if (addr & (size - 1)) { DPRINTF("not implemented read for TxStatus/TxAddr " - "addr=0x%x size=0x%x\n", addr, size); + "addr=0x%x size=0x%x\n", + addr, size); return ret; } @@ -2459,7 +2468,7 @@ rtl8139_TxStatus_TxAddr_read(UNUSED(RTL8139State *s), uint32_t regs[], case 1: /* fall through */ case 2: /* fall through */ case 4: - ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1); + ret = (regs[reg] >> offset * 8) & (((uint64_t) 1 << (size * 8)) - 1); DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n", reg, addr, size, ret); break; @@ -2479,26 +2488,25 @@ rtl8139_TSAD_read(RTL8139State *s) /* Simulate TSAD, it is read only anyway */ - ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0) - |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0) - |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0) - |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0) + ret = ((s->TxStatus[3] & TxStatOK) ? TSAD_TOK3 : 0) + | ((s->TxStatus[2] & TxStatOK) ? TSAD_TOK2 : 0) + | ((s->TxStatus[1] & TxStatOK) ? TSAD_TOK1 : 0) + | ((s->TxStatus[0] & TxStatOK) ? TSAD_TOK0 : 0) - |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0) - |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0) - |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0) - |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0) + | ((s->TxStatus[3] & TxUnderrun) ? TSAD_TUN3 : 0) + | ((s->TxStatus[2] & TxUnderrun) ? TSAD_TUN2 : 0) + | ((s->TxStatus[1] & TxUnderrun) ? TSAD_TUN1 : 0) + | ((s->TxStatus[0] & TxUnderrun) ? TSAD_TUN0 : 0) - |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0) - |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0) - |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0) - |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0) - - |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0) - |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0) - |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0) - |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ; + | ((s->TxStatus[3] & TxAborted) ? TSAD_TABT3 : 0) + | ((s->TxStatus[2] & TxAborted) ? TSAD_TABT2 : 0) + | ((s->TxStatus[1] & TxAborted) ? TSAD_TABT1 : 0) + | ((s->TxStatus[0] & TxAborted) ? TSAD_TABT0 : 0) + | ((s->TxStatus[3] & TxHostOwns) ? TSAD_OWN3 : 0) + | ((s->TxStatus[2] & TxHostOwns) ? TSAD_OWN2 : 0) + | ((s->TxStatus[1] & TxHostOwns) ? TSAD_OWN1 : 0) + | ((s->TxStatus[0] & TxHostOwns) ? TSAD_OWN0 : 0); DPRINTF("TSAD read val=0x%04x\n", ret); @@ -2520,13 +2528,13 @@ rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val) { DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val); - s->TxAddr[txAddrOffset/4] = val; + s->TxAddr[txAddrOffset / 4] = val; } static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset) { - uint32_t ret = s->TxAddr[txAddrOffset/4]; + uint32_t ret = s->TxAddr[txAddrOffset / 4]; DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret); @@ -2542,7 +2550,7 @@ rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val) s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize); DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n", - s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); + s->RxBufferSize, s->RxBufAddr, s->RxBufPtr); } static uint32_t @@ -2598,7 +2606,6 @@ rtl8139_IntrMask_write(RTL8139State *s, uint32_t val) s->IntrMask = val; rtl8139_update_irq(s); - } static uint32_t @@ -2685,16 +2692,16 @@ rtl8139_io_writeb(uint32_t addr, uint8_t val, void *priv) addr &= 0xFF; switch (addr) { - case MAC0 ... MAC0+4: + case MAC0 ... MAC0 + 4: s->phys[addr - MAC0] = val; break; - case MAC0+5: + case MAC0 + 5: s->phys[addr - MAC0] = val; break; - case MAC0+6 ... MAC0+7: + case MAC0 + 6 ... MAC0 + 7: /* reserved */ break; - case MAR0 ... MAR0+7: + case MAR0 ... MAR0 + 7: s->mult[addr - MAR0] = val; break; case ChipCmd: @@ -2724,7 +2731,7 @@ rtl8139_io_writeb(uint32_t addr, uint8_t val, void *priv) case MediaStatus: /* ignore */ DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n", - val); + val); break; case HltClk: @@ -2745,7 +2752,7 @@ rtl8139_io_writeb(uint32_t addr, uint8_t val, void *priv) DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val); if (val & (1 << 7)) { DPRINTF("C+ TxPoll high priority transmission (not " - "implemented)\n"); + "implemented)\n"); #if 0 //rtl8139_cplus_transmit(s); #endif @@ -2759,7 +2766,7 @@ rtl8139_io_writeb(uint32_t addr, uint8_t val, void *priv) default: DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr, - val); + val); break; } } @@ -2770,8 +2777,7 @@ rtl8139_io_writew(uint32_t addr, uint16_t val, void *priv) RTL8139State *s = priv; addr &= 0xFF; - switch (addr) - { + switch (addr) { case IntrMask: rtl8139_IntrMask_write(s, val); break; @@ -2816,7 +2822,7 @@ rtl8139_io_writew(uint32_t addr, uint16_t val, void *priv) default: DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n", - addr, val); + addr, val); rtl8139_io_writeb(addr, val & 0xff, priv); rtl8139_io_writeb(addr + 1, (val >> 8) & 0xff, priv); @@ -2832,8 +2838,7 @@ rtl8139_io_writel(uint32_t addr, uint32_t val, void *priv) RTL8139State *s = priv; addr &= 0xFF; - switch (addr) - { + switch (addr) { case RxMissed: DPRINTF("RxMissed clearing on write\n"); s->RxMissed = 0; @@ -2847,12 +2852,12 @@ rtl8139_io_writel(uint32_t addr, uint32_t val, void *priv) rtl8139_RxConfig_write(s, val); break; - case TxStatus0 ... TxStatus0+4*4-1: - rtl8139_TxStatus_write(s, addr-TxStatus0, val); + case TxStatus0 ... TxStatus0 + 4 * 4 - 1: + rtl8139_TxStatus_write(s, addr - TxStatus0, val); break; - case TxAddr0 ... TxAddr0+4*4-1: - rtl8139_TxAddr_write(s, addr-TxAddr0, val); + case TxAddr0 ... TxAddr0 + 4 * 4 - 1: + rtl8139_TxAddr_write(s, addr - TxAddr0, val); break; case RxBuf: @@ -2887,7 +2892,7 @@ rtl8139_io_writel(uint32_t addr, uint32_t val, void *priv) default: DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n", - addr, val); + addr, val); rtl8139_io_writeb(addr, val & 0xff, priv); rtl8139_io_writeb(addr + 1, (val >> 8) & 0xff, priv); rtl8139_io_writeb(addr + 2, (val >> 16) & 0xff, priv); @@ -2896,25 +2901,24 @@ rtl8139_io_writel(uint32_t addr, uint32_t val, void *priv) } } - static uint8_t rtl8139_io_readb(uint32_t addr, void *priv) { RTL8139State *s = priv; - uint8_t ret; + uint8_t ret; addr &= 0xFF; switch (addr) { - case MAC0 ... MAC0+5: + case MAC0 ... MAC0 + 5: ret = s->phys[addr - MAC0]; break; - case MAC0+6 ... MAC0+7: + case MAC0 + 6 ... MAC0 + 7: ret = 0; break; - case MAR0 ... MAR0+7: + case MAR0 ... MAR0 + 7: ret = s->mult[addr - MAR0]; break; - case TxStatus0 ... TxStatus0+4*4-1: + case TxStatus0 ... TxStatus0 + 4 * 4 - 1: ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, addr, 1); break; @@ -2979,11 +2983,11 @@ static uint16_t rtl8139_io_readw(uint32_t addr, void *priv) { RTL8139State *s = priv; - uint16_t ret; + uint16_t ret; addr &= 0xFF; switch (addr) { - case TxAddr0 ... TxAddr0+4*4-1: + case TxAddr0 ... TxAddr0 + 4 * 4 - 1: ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2); break; case IntrMask: @@ -3044,7 +3048,7 @@ rtl8139_io_readw(uint32_t addr, void *priv) default: DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr); - ret = rtl8139_io_readb(addr, priv); + ret = rtl8139_io_readb(addr, priv); ret |= rtl8139_io_readb(addr + 1, priv) << 8; DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret); @@ -3058,7 +3062,7 @@ static uint32_t rtl8139_io_readl(uint32_t addr, void *priv) { RTL8139State *s = priv; - uint32_t ret; + uint32_t ret; addr &= 0xFF; switch (addr) { @@ -3076,13 +3080,13 @@ rtl8139_io_readl(uint32_t addr, void *priv) ret = rtl8139_RxConfig_read(s); break; - case TxStatus0 ... TxStatus0+4*4-1: + case TxStatus0 ... TxStatus0 + 4 * 4 - 1: ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0, addr, 4); break; - case TxAddr0 ... TxAddr0+4*4-1: - ret = rtl8139_TxAddr_read(s, addr-TxAddr0); + case TxAddr0 ... TxAddr0 + 4 * 4 - 1: + ret = rtl8139_TxAddr_read(s, addr - TxAddr0); break; case RxBuf: @@ -3116,7 +3120,7 @@ rtl8139_io_readl(uint32_t addr, void *priv) default: DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr); - ret = rtl8139_io_readb(addr, priv); + ret = rtl8139_io_readb(addr, priv); ret |= rtl8139_io_readb(addr + 1, priv) << 8; ret |= rtl8139_io_readb(addr + 2, priv) << 16; ret |= rtl8139_io_readb(addr + 3, priv) << 24; @@ -3165,9 +3169,9 @@ rtl8139_io_writeb_ioport(uint16_t addr, uint8_t val, void *priv) } static int -rtl8139_set_link_status(void* priv, uint32_t link_state) +rtl8139_set_link_status(void *priv, uint32_t link_state) { - RTL8139State *s = (RTL8139State*)priv; + RTL8139State *s = (RTL8139State *) priv; if (link_state & NET_LINK_DOWN) { s->BasicModeStatus &= ~0x04; @@ -3187,15 +3191,14 @@ rtl8139_timer(void *priv) timer_on_auto(&s->timer, 1000000.0 / ((double) cpu_pci_speed)); - if (!s->clock_enabled) - { + if (!s->clock_enabled) { DPRINTF(">>> timer: clock is not running\n"); return; } s->TCTR++; - if (s->TCTR == s->TimerInt && s->TimerInt != 0){ + if (s->TCTR == s->TimerInt && s->TimerInt != 0) { s->IntrStatus |= PCSTimeout; rtl8139_update_irq(s); } @@ -3260,10 +3263,16 @@ rtl8139_pci_write(int func, int addr, uint8_t val, void *priv) switch (addr) { case 0x04: mem_mapping_disable(&s->bar_mem); - io_removehandler((s->pci_conf[0x11] << 8), 256, rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport, rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport, priv); + io_removehandler((s->pci_conf[0x11] << 8), 256, + rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport, + rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport, + priv); s->pci_conf[addr & 0xFF] = val; if (val & PCI_COMMAND_IO) - io_sethandler((s->pci_conf[0x11] << 8), 256, rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport, rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport, priv); + io_sethandler((s->pci_conf[0x11] << 8), 256, + rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport, + rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport, + priv); if ((val & PCI_COMMAND_MEM) && s->bar_mem.size) mem_mapping_enable(&s->bar_mem); break; @@ -3278,10 +3287,16 @@ rtl8139_pci_write(int func, int addr, uint8_t val, void *priv) break; case 0x10: case 0x11: - io_removehandler((s->pci_conf[0x11] << 8), 256, rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport, rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport, priv); + io_removehandler((s->pci_conf[0x11] << 8), 256, + rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport, + rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport, + priv); s->pci_conf[addr & 0xFF] = val; if (s->pci_conf[0x4] & PCI_COMMAND_IO) - io_sethandler((s->pci_conf[0x11] << 8), 256, rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport, rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport, priv); + io_sethandler((s->pci_conf[0x11] << 8), 256, + rtl8139_io_readb_ioport, rtl8139_io_readw_ioport, rtl8139_io_readl_ioport, + rtl8139_io_writeb_ioport, rtl8139_io_writew_ioport, rtl8139_io_writel_ioport, + priv); break; case 0x14: case 0x15: @@ -3300,18 +3315,18 @@ rtl8139_pci_write(int func, int addr, uint8_t val, void *priv) static void * nic_init(const device_t *info) { - RTL8139State *s = calloc(1, sizeof(RTL8139State)); - FILE* fp = NULL; - char eeprom_filename[1024] = { 0 }; + RTL8139State *s = calloc(1, sizeof(RTL8139State)); + FILE *fp = NULL; + char eeprom_filename[1024] = { 0 }; + mem_mapping_add(&s->bar_mem, 0, 0, rtl8139_io_readb, rtl8139_io_readw, rtl8139_io_readl, rtl8139_io_writeb, rtl8139_io_writew, rtl8139_io_writel, NULL, MEM_MAPPING_EXTERNAL, s); pci_add_card(PCI_ADD_NETWORK, rtl8139_pci_read, rtl8139_pci_write, s, &s->pci_slot); s->inst = device_get_instance(); - + snprintf(eeprom_filename, sizeof(eeprom_filename), "eeprom_rtl8139c_plus_%d.nvr", s->inst); fp = nvr_fopen(eeprom_filename, "rb"); - if (fp) - { + if (fp) { fread(s->eeprom.contents, 2, 64, fp); fclose(fp); fp = NULL; @@ -3329,12 +3344,12 @@ nic_init(const device_t *info) s->eeprom.contents[9] = 0x1413; } - s->nic = network_attach(s, (uint8_t*)&s->eeprom.contents[7], rtl8139_do_receive, rtl8139_set_link_status); + s->nic = network_attach(s, (uint8_t *) &s->eeprom.contents[7], rtl8139_do_receive, rtl8139_set_link_status); timer_add(&s->timer, rtl8139_timer, s, 0); timer_on_auto(&s->timer, 1000000.0 / cpu_pci_speed); - s->cplus_txbuffer = NULL; - s->cplus_txbuffer_len = 0; + s->cplus_txbuffer = NULL; + s->cplus_txbuffer_len = 0; s->cplus_txbuffer_offset = 0; return s; @@ -3343,14 +3358,13 @@ nic_init(const device_t *info) static void nic_close(void *priv) { - const RTL8139State *s = (RTL8139State*) priv; - FILE* fp = NULL; - char eeprom_filename[1024] = { 0 }; + const RTL8139State *s = (RTL8139State *) priv; + FILE *fp = NULL; + char eeprom_filename[1024] = { 0 }; snprintf(eeprom_filename, sizeof(eeprom_filename), "eeprom_rtl8139c_plus_%d.nvr", s->inst); fp = nvr_fopen(eeprom_filename, "wb"); - if (fp) - { + if (fp) { fwrite(s->eeprom.contents, 2, 64, fp); fclose(fp); fp = NULL; diff --git a/src/network/net_tulip.c b/src/network/net_tulip.c index 680f1e939..0f5724608 100644 --- a/src/network/net_tulip.c +++ b/src/network/net_tulip.c @@ -989,7 +989,7 @@ tulip_xmit_list_update(TULIPState *s) static void tulip_csr9_write(TULIPState *s, UNUSED(uint32_t old_val), - uint32_t new_val) + uint32_t new_val) { if (new_val & CSR9_SR) { nmc93cxx_eeprom_write(s->eeprom, @@ -1002,7 +1002,7 @@ tulip_csr9_write(TULIPState *s, UNUSED(uint32_t old_val), static void tulip_reset(void *priv) { - TULIPState *s = (TULIPState *) priv; + TULIPState *s = (TULIPState *) priv; const uint16_t *eeprom_data = nmc93cxx_eeprom_data(s->eeprom); s->csr[0] = 0xfe000000; s->csr[1] = 0xffffffff; @@ -1526,10 +1526,16 @@ tulip_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) switch (addr) { case 0x4: mem_mapping_disable(&s->memory); - io_removehandler((s->pci_conf[0x10] & 0x80) | (s->pci_conf[0x11] << 8), 128, NULL, NULL, tulip_read_io, NULL, NULL, tulip_write_io, priv); + io_removehandler((s->pci_conf[0x10] & 0x80) | (s->pci_conf[0x11] << 8), 128, + NULL, NULL, tulip_read_io, + NULL, NULL, tulip_write_io, + priv); s->pci_conf[addr & 0xFF] = val; if (val & PCI_COMMAND_IO) - io_sethandler((s->pci_conf[0x10] & 0x80) | (s->pci_conf[0x11] << 8), 128, NULL, NULL, tulip_read_io, NULL, NULL, tulip_write_io, priv); + io_sethandler((s->pci_conf[0x10] & 0x80) | (s->pci_conf[0x11] << 8), 128, + NULL, NULL, tulip_read_io, + NULL, NULL, tulip_write_io, + priv); if ((val & PCI_COMMAND_MEM) && s->memory.size) mem_mapping_enable(&s->memory); break; @@ -1538,10 +1544,16 @@ tulip_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv) break; case 0x10: case 0x11: - io_removehandler((s->pci_conf[0x10] & 0x80) | (s->pci_conf[0x11] << 8), 128, NULL, NULL, tulip_read_io, NULL, NULL, tulip_write_io, priv); + io_removehandler((s->pci_conf[0x10] & 0x80) | (s->pci_conf[0x11] << 8), 128, + NULL, NULL, tulip_read_io, + NULL, NULL, tulip_write_io, + priv); s->pci_conf[addr & 0xFF] = val; if (s->pci_conf[0x4] & PCI_COMMAND_IO) - io_sethandler((s->pci_conf[0x10] & 0x80) | (s->pci_conf[0x11] << 8), 128, NULL, NULL, tulip_read_io, NULL, NULL, tulip_write_io, priv); + io_sethandler((s->pci_conf[0x10] & 0x80) | (s->pci_conf[0x11] << 8), 128, + NULL, NULL, tulip_read_io, + NULL, NULL, tulip_write_io, + priv); break; case 0x14: case 0x15: