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OPTi 5x7 no longer does excess logging, running of timers on the recompiler is now done on every fourth AT KBC port 61h read instead of every 3F4h read, added some safety precautions to io.c to handle the cases where a handler removes itself, implmented the STPC ELCR and refresh control, and fixed the messed up register reading in the PC87307 and PC87309 implementations.

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This commit is contained in:
OBattler
2020-07-10 02:05:49 +02:00
parent 3fe9ad3e67
commit 72c1c36ec6
14 changed files with 99 additions and 37 deletions
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25
src/chipset/opti5x7.c
View File

@@ -41,6 +41,27 @@ typedef struct
port_92_t *port_92;
} opti5x7_t;
#ifdef ENABLE_OPTI5X7_LOG
int opti5x7_do_log = ENABLE_OPTI5X7_LOG;
static void
opti5x7_log(const char *fmt, ...)
{
va_list ap;
if (opti5x7_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define opti5x7_log(fmt, ...)
#endif
static void
opti5x7_recalc(opti5x7_t *dev)
{
@@ -81,7 +102,7 @@ static void
opti5x7_write(uint16_t addr, uint8_t val, void *priv)
{
opti5x7_t *dev = (opti5x7_t *) priv;
pclog("Write %02x to OPTi 5x7 address %02x\n", val, addr);
opti5x7_log("Write %02x to OPTi 5x7 address %02x\n", val, addr);
switch (addr) {
case 0x22:
@@ -113,7 +134,7 @@ opti5x7_read(uint16_t addr, void *priv)
switch (addr) {
case 0x24:
pclog("Read from OPTi 5x7 register %02x\n", dev->idx);
opti5x7_log("Read from OPTi 5x7 register %02x\n", dev->idx);
ret = dev->regs[dev->idx];
break;
}

14
src/chipset/stpc.c
View File

@@ -27,6 +27,8 @@
#include <86box/rom.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/port_92.h>
@@ -631,6 +633,9 @@ stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
case 0x56: case 0x57:
/* ELCR goes here */
elcr_write(dev->reg_offset, val, NULL);
if (dev->reg_offset == 0x57)
refresh_at_enable = val & 0x01;
break;
}
@@ -649,7 +654,11 @@ stpc_reg_read(uint16_t addr, void *priv)
ret = dev->reg_offset;
else if (dev->reg_offset >= 0xc0)
return 0xff; /* Cyrix CPU registers: let the CPU code handle those */
else
else if ((dev->reg_offset == 0x56) || (dev->reg_offset == 0x57)) {
ret = elcr_read(dev->reg_offset, NULL);
if (dev->reg_offset == 0x57)
ret |= (dev->regs[dev->reg_offset] & 0x01);
} else
ret = dev->regs[dev->reg_offset];
stpc_log("STPC: reg_read(%04X) = %02X\n", addr, ret);
@@ -837,6 +846,9 @@ stpc_init(const device_t *info)
device_add(&port_92_pci_device);
pci_elcr_io_disable();
refresh_at_enable = 0;
return dev;
}