Finished the SiS 50x work and added the two ASUS'es.
This commit is contained in:
OBattler
@@ -35,304 +35,368 @@
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#include <86box/chipset.h>
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#ifdef ENABLE_SIS_85C50X_LOG
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int sis_85c50x_do_log = ENABLE_SIS_85C50X_LOG;
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static void
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sis_85c50x_log(const char *fmt, ...)
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{
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va_list ap;
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va_list ap;
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if (sis_85c50x_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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if (sis_85c50x_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define sis_85c50x_log(fmt, ...)
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#endif
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typedef struct sis_85c50x_t
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{
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uint8_t pci_conf[256], pci_conf_sb[256], regs[256], index;
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uint8_t index,
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pci_conf[256], pci_conf_sb[256],
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regs[256];
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apm_t *apm;
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smram_t *smram;
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smram_t * smram;
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port_92_t * port_92;
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} sis_85c50x_t;
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static void
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sis_85c50x_shadow_recalc(sis_85c50x_t *dev)
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{
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uint32_t base, i, can_read, can_write;
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uint32_t base, i, can_read, can_write;
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can_read = (dev->pci_conf[0x53] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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can_write = (dev->pci_conf[0x53] & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
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can_read = (dev->pci_conf[0x53] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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can_write = (dev->pci_conf[0x53] & 0x20) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
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if (!can_read)
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can_write = MEM_WRITE_EXTANY;
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mem_set_mem_state_both(0xf0000, 0x10000, can_read | can_write);
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mem_set_mem_state_both(0xf0000, 0x10000, can_read | can_write);
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shadowbios = 1;
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shadowbios_write = 1;
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for (i = 0; i < 4; i++)
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{
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base = 0xd0000 - ((i + 1) << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x56] & (1 << (i + 4))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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mem_set_mem_state_both(base + 0x10000, 0x4000, (dev->pci_conf[0x55] & (1 << (i + 4))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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mem_set_mem_state_both(base + 0x20000, 0x4000, (dev->pci_conf[0x54] & (1 << (i + 4))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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}
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flushmmucache();
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for (i = 0; i < 4; i++) {
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base = 0xe0000 + (i << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x54] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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base = 0xd0000 + (i << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x55] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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base = 0xc0000 + (i << 14);
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mem_set_mem_state_both(base, 0x4000, (dev->pci_conf[0x56] & (1 << (7 - i))) ? (can_read | can_write) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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}
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flushmmucache();
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}
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static void
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sis_85c50x_smm_recalc(sis_85c50x_t *dev)
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{
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//Note: Host Address determination is unclear
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switch ((dev->pci_conf[0x65] & 0xe0) >> 5)
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{
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/* NOTE: Naming mismatch - what the datasheet calls "host address" is what we call ram_base. */
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uint32_t ram_base = (dev->pci_conf[0x64] << 20) |
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((dev->pci_conf[0x65] & 0x07) << 28);
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smram_disable(dev->smram);
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if ((((dev->pci_conf[0x65] & 0xe0) >> 5) != 0x00) && (ram_base == 0x00000000))
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return;
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switch ((dev->pci_conf[0x65] & 0xe0) >> 5) {
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case 0x00:
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if (dev->pci_conf[0x54] == 0x00)
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smram_enable(dev->smram, 0xa0000, 0xe0000, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
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if (!(dev->pci_conf[0x54] & 0xc0))
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smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
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break;
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case 0x01:
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smram_enable(dev->smram, 0xa0000, 0xb0000, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
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smram_enable(dev->smram, 0xb0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
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break;
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case 0x02:
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smram_enable(dev->smram, 0xa0000, 0xa0000, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
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smram_enable(dev->smram, 0xa0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);
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break;
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case 0x04:
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smram_enable(dev->smram, 0xa0000, 0xa0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
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smram_enable(dev->smram, 0xa0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
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break;
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case 0x06:
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smram_enable(dev->smram, 0xa0000, 0xb0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
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smram_enable(dev->smram, 0xb0000, ram_base, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
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break;
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}
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}
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}
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static void
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sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
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{
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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uint8_t valxor = (val ^ dev->pci_conf[addr]);
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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dev->pci_conf[addr] = val;
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switch (addr)
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{
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case 0x04: /* Command */
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dev->pci_conf[addr] = (val & 0xcf);
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switch (addr) {
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case 0x04: /* Command - low byte */
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dev->pci_conf[addr] = (dev->pci_conf[addr] & 0xb4) | (val & 0x4b);
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break;
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case 0x07: /* Status */
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dev->pci_conf[addr] = (val & 0xfe);
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case 0x07: /* Status - high byte */
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dev->pci_conf[addr] = ((dev->pci_conf[addr] & 0xf9) & ~(val & 0xf8)) | (val & 0x06);
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break;
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case 0x50:
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dev->pci_conf[addr] = val;
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break;
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case 0x51: /* Cache */
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dev->pci_conf[addr] = val;
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cpu_cache_ext_enabled = (val & 0x40);
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cpu_update_waitstates();
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break;
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case 0x52:
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dev->pci_conf[addr] = val;
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break;
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case 0x53: /* Shadow RAM */
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case 0x54:
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case 0x55:
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case 0x56:
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dev->pci_conf[addr] = val;
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sis_85c50x_shadow_recalc(dev);
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if (addr == 0x54)
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sis_85c50x_smm_recalc(dev);
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break;
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case 0x57: case 0x58: case 0x59: case 0x5a:
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case 0x5c: case 0x5d: case 0x5e: case 0x61:
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case 0x62: case 0x63: case 0x67: case 0x68:
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case 0x6a: case 0x6b: case 0x6c: case 0x6d:
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case 0x6e: case 0x6f:
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dev->pci_conf[addr] = val;
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break;
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case 0x5f:
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dev->pci_conf[addr] = (val & 0xfe);
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dev->pci_conf[addr] = val & 0xfe;
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break;
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case 0x60: /* SMI */
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apm_set_do_smi(dev->apm, ((val & 0x02) && (dev->pci_conf[0x68] & 0x01)));
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if (val & 0x02)
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dev->pci_conf[0x69] &= 0x01;
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case 0x5b:
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dev->pci_conf[addr] = val;
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if (valxor & 0xc0)
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port_92_set_features(dev->port_92, !!(val & 0x40), !!(val & 0x80));
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break;
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case 0x64: /* SMM/SMRAM */
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case 0x60: /* SMI */
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if ((dev->pci_conf[0x68] & 0x01) && !(dev->pci_conf[addr] & 0x02) && (val & 0x02)) {
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dev->pci_conf[0x69] |= 0x01;
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smi_line = 1;
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}
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dev->pci_conf[addr] = val & 0x3e;
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break;
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case 0x64: /* SMRAM */
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case 0x65:
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dev->pci_conf[addr] = val;
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sis_85c50x_smm_recalc(dev);
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break;
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case 0x66:
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dev->pci_conf[addr] = (val & 0x7f);
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break;
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}
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sis_85c50x_log("85C501: dev->pci_conf[%02x] = %02x\n", addr, val);
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case 0x69:
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dev->pci_conf[addr] &= ~(val);
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break;
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}
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sis_85c50x_log("85C501: dev->pci_conf[%02x] = %02x\n", addr, val);
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}
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static uint8_t
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sis_85c50x_read(int func, int addr, void *priv)
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{
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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sis_85c50x_log("85C501: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]);
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return dev->pci_conf[addr];
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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sis_85c50x_log("85C501: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]);
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return dev->pci_conf[addr];
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}
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static void
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sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
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{
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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switch (addr) {
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case 0x04: /* Command */
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dev->pci_conf_sb[addr] = val & 0x0f;
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break;
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case 0x07: /* Status */
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dev->pci_conf_sb[addr] &= ~(val & 0x30);
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break;
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case 0x40: /* BIOS Control Register */
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dev->pci_conf_sb[addr] = val & 0x3f;
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break;
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case 0x41: case 0x42: case 0x43: case 0x44:
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/* INTA/B/C/D# Remapping Control Register */
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dev->pci_conf_sb[addr] = val & 0x8f;
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTA + (addr - 0x41), PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTA + (addr - 0x41), val & 0xf);
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break;
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case 0x48: /* ISA Master/DMA Memory Cycle Control Register 1 */
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case 0x49: /* ISA Master/DMA Memory Cycle Control Register 2 */
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case 0x4a: /* ISA Master/DMA Memory Cycle Control Register 3 */
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case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
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dev->pci_conf_sb[addr] = val;
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break;
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}
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dev->pci_conf_sb[addr] = val;
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switch (addr)
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{
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case 0x07: /* Status */
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dev->pci_conf_sb[addr] = (val & 0x36);
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break;
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case 0x40:
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dev->pci_conf_sb[addr] = (val & 0x3f);
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break;
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case 0x41: /* PCI INTA IRQ */
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sis_85c50x_log("85C503: Remapping Slot %02x to IRQ %02x\n", PCI_INTA, (val & 0x0f));
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dev->pci_conf_sb[addr] = (val & 0x8f);
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pci_set_irq_routing(PCI_INTA, !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
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break;
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case 0x42: /* PCI INTB IRQ */
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sis_85c50x_log("85C503: Remapping Slot %02x to IRQ %02x\n", PCI_INTB, (val & 0x0f));
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dev->pci_conf_sb[addr] = (val & 0x8f);
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pci_set_irq_routing(PCI_INTB, !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
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break;
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case 0x43: /* PCI INTC IRQ */
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sis_85c50x_log("85C503: Remapping Slot %02x to IRQ %02x\n", PCI_INTC, (val & 0x0f));
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dev->pci_conf_sb[addr] = (val & 0x8f);
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pci_set_irq_routing(PCI_INTC, !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
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break;
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case 0x44: /* PCI INTD IRQ */
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sis_85c50x_log("85C503: Remapping Slot %02x to IRQ %02x\n", PCI_INTD, (val & 0x0f));
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dev->pci_conf_sb[addr] = (val & 0x8f);
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pci_set_irq_routing(PCI_INTD, !(val & 0x80) ? (val & 0x0f) : PCI_IRQ_DISABLED);
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break;
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}
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sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] = %02x\n", addr, val);
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sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] = %02x\n", addr, val);
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}
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static uint8_t
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sis_85c50x_sb_read(int func, int addr, void *priv)
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{
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] (%02x)\n", addr, dev->pci_conf_sb[addr]);
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return dev->pci_conf_sb[addr];
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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sis_85c50x_log("85C503: dev->pci_conf_sb[%02x] (%02x)\n", addr, dev->pci_conf_sb[addr]);
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return dev->pci_conf_sb[addr];
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}
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static void
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sis_85c50x_isa_write(uint16_t addr, uint8_t val, void *priv)
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{
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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switch (addr)
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{
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switch (addr) {
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case 0x22:
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dev->index = val;
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break;
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case 0x23:
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dev->regs[dev->index] = val;
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switch (dev->index)
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{
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case 0x81:
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dev->regs[dev->index] = (val & 0xf4);
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cpu_update_waitstates();
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break;
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switch (dev->index) {
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case 0x80:
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dev->regs[dev->index] = val & 0xe7;
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break;
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case 0x81:
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dev->regs[dev->index] = val & 0xf4;
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break;
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case 0x84: case 0x88: case 0x9: case 0x8a:
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case 0x8b:
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dev->regs[dev->index] = val;
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break;
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case 0x85:
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outb(0x70, val);
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break;
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}
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}
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sis_85c50x_log("85C501-ISA: dev->regs[%02x] = %02x\n", addr, val);
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break;
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}
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sis_85c50x_log("85C501-ISA: dev->regs[%02x] = %02x\n", addr, val);
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}
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static uint8_t
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sis_85c50x_isa_read(uint16_t addr, void *priv)
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{
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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return dev->regs[dev->index];
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sis_85c50x_log("85C501-ISA: dev->regs[%02x] (%02x)\n", dev->index, dev->regs[dev->index]);
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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uint8_t ret = 0xff;
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switch (addr) {
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case 0x22:
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ret = dev->index;
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break;
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case 0x23:
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if (dev->index == 0x85)
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ret = inb(0x70);
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else
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ret = dev->regs[dev->index];
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break;
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}
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sis_85c50x_log("85C501-ISA: dev->regs[%02x] (%02x)\n", dev->index, ret);
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return ret;
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}
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static void
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sis_85c50x_reset(void *priv)
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{
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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sis_85c50x_t *dev = (sis_85c50x_t *)priv;
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/* North Bridge (SiS 85C501/502) */
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dev->pci_conf[0x00] = 0x39;
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dev->pci_conf[0x01] = 0x10;
|
||||
dev->pci_conf[0x02] = 0x06;
|
||||
dev->pci_conf[0x03] = 0x04;
|
||||
dev->pci_conf[0x04] = 0x04;
|
||||
dev->pci_conf[0x05] = 0x00;
|
||||
dev->pci_conf[0x06] = 0x00;
|
||||
dev->pci_conf[0x07] = 0x00;
|
||||
dev->pci_conf[0x08] = 0x00;
|
||||
dev->pci_conf[0x09] = 0x00;
|
||||
dev->pci_conf[0x0a] = 0x00;
|
||||
dev->pci_conf[0x0b] = 0x06;
|
||||
dev->pci_conf[0x0c] = 0x00;
|
||||
dev->pci_conf[0x0d] = 0x00;
|
||||
dev->pci_conf[0x0e] = 0x00;
|
||||
dev->pci_conf[0x0f] = 0x00;
|
||||
/* North Bridge (SiS 85C501/502) */
|
||||
dev->pci_conf[0x00] = 0x39;
|
||||
dev->pci_conf[0x01] = 0x10;
|
||||
dev->pci_conf[0x02] = 0x06;
|
||||
dev->pci_conf[0x03] = 0x04;
|
||||
dev->pci_conf[0x04] = 0x04;
|
||||
dev->pci_conf[0x07] = 0x04;
|
||||
dev->pci_conf[0x09] = 0x00;
|
||||
dev->pci_conf[0x0a] = 0x00;
|
||||
dev->pci_conf[0x0b] = 0x06;
|
||||
|
||||
sis_85c50x_write(0, 0x51, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x53, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x54, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x55, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x56, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x60, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x64, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x65, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x51, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x53, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x54, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x55, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x56, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x5b, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x60, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x64, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x65, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x68, 0x00, dev);
|
||||
sis_85c50x_write(0, 0x69, 0xff, dev);
|
||||
|
||||
/* South Bridge (SiS 85C503) */
|
||||
dev->pci_conf_sb[0x00] = 0x39;
|
||||
dev->pci_conf_sb[0x01] = 0x10;
|
||||
dev->pci_conf_sb[0x02] = 0x08;
|
||||
dev->pci_conf_sb[0x03] = 0x00;
|
||||
dev->pci_conf_sb[0x04] = 0x07;
|
||||
dev->pci_conf_sb[0x05] = 0x00;
|
||||
dev->pci_conf_sb[0x06] = 0x00;
|
||||
dev->pci_conf_sb[0x07] = 0x00;
|
||||
dev->pci_conf_sb[0x08] = 0x00;
|
||||
dev->pci_conf_sb[0x09] = 0x00;
|
||||
dev->pci_conf_sb[0x0a] = 0x01;
|
||||
dev->pci_conf_sb[0x0b] = 0x06;
|
||||
dev->pci_conf_sb[0x0c] = 0x00;
|
||||
dev->pci_conf_sb[0x0d] = 0x00;
|
||||
dev->pci_conf_sb[0x0e] = 0x00;
|
||||
dev->pci_conf_sb[0x0f] = 0x00;
|
||||
sis_85c50x_write(0, 0x41, 0x80, dev);
|
||||
sis_85c50x_write(0, 0x42, 0x80, dev);
|
||||
sis_85c50x_write(0, 0x43, 0x80, dev);
|
||||
sis_85c50x_write(0, 0x44, 0x80, dev);
|
||||
/* South Bridge (SiS 85C503) */
|
||||
dev->pci_conf_sb[0x00] = 0x39;
|
||||
dev->pci_conf_sb[0x01] = 0x10;
|
||||
dev->pci_conf_sb[0x02] = 0x08;
|
||||
dev->pci_conf_sb[0x03] = 0x00;
|
||||
dev->pci_conf_sb[0x04] = 0x07;
|
||||
dev->pci_conf_sb[0x05] = 0x00;
|
||||
dev->pci_conf_sb[0x06] = 0x00;
|
||||
dev->pci_conf_sb[0x07] = 0x02;
|
||||
dev->pci_conf_sb[0x08] = 0x00;
|
||||
dev->pci_conf_sb[0x09] = 0x00;
|
||||
dev->pci_conf_sb[0x0a] = 0x01;
|
||||
dev->pci_conf_sb[0x0b] = 0x06;
|
||||
sis_85c50x_write(0, 0x41, 0x80, dev);
|
||||
sis_85c50x_write(0, 0x42, 0x80, dev);
|
||||
sis_85c50x_write(0, 0x43, 0x80, dev);
|
||||
sis_85c50x_write(0, 0x44, 0x80, dev);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
sis_85c50x_close(void *priv)
|
||||
{
|
||||
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
|
||||
sis_85c50x_t *dev = (sis_85c50x_t *)priv;
|
||||
|
||||
smram_del(dev->smram);
|
||||
free(dev);
|
||||
smram_del(dev->smram);
|
||||
free(dev);
|
||||
}
|
||||
|
||||
|
||||
static void *
|
||||
sis_85c50x_init(const device_t *info)
|
||||
{
|
||||
sis_85c50x_t *dev = (sis_85c50x_t *)malloc(sizeof(sis_85c50x_t));
|
||||
memset(dev, 0, sizeof(sis_85c50x_t));
|
||||
sis_85c50x_t *dev = (sis_85c50x_t *)malloc(sizeof(sis_85c50x_t));
|
||||
memset(dev, 0x00, sizeof(sis_85c50x_t));
|
||||
|
||||
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c50x_read, sis_85c50x_write, dev);
|
||||
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_85c50x_sb_read, sis_85c50x_sb_write, dev);
|
||||
io_sethandler(0x0022, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
|
||||
dev->apm = device_add(&apm_pci_device);
|
||||
dev->smram = smram_add();
|
||||
device_add(&port_92_device);
|
||||
sis_85c50x_reset(dev);
|
||||
return dev;
|
||||
/* 501/502 (Northbridge) */
|
||||
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c50x_read, sis_85c50x_write, dev);
|
||||
|
||||
/* 503 (Southbridge) */
|
||||
pci_add_card(PCI_ADD_SOUTHBRIDGE, sis_85c50x_sb_read, sis_85c50x_sb_write, dev);
|
||||
io_sethandler(0x0022, 0x0002, sis_85c50x_isa_read, NULL, NULL, sis_85c50x_isa_write, NULL, NULL, dev);
|
||||
|
||||
dev->smram = smram_add();
|
||||
dev->port_92 = device_add(&port_92_device);
|
||||
|
||||
sis_85c50x_reset(dev);
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
|
||||
const device_t sis_85c50x_device = {
|
||||
"SiS 85C50x",
|
||||
DEVICE_PCI,
|
||||
0,
|
||||
sis_85c50x_init,
|
||||
sis_85c50x_close,
|
||||
sis_85c50x_reset,
|
||||
{NULL},
|
||||
NULL,
|
||||
NULL,
|
||||
NULL};
|
||||
"SiS 85C50x",
|
||||
DEVICE_PCI,
|
||||
0,
|
||||
sis_85c50x_init, sis_85c50x_close,
|
||||
sis_85c50x_reset, { NULL },
|
||||
NULL, NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user