The Intel SIO and PIIX* southbridges now have the undocumented (by the datasheets, but fully documented by the Intel motherboard technical specifications) second PIT on ports 48h-4Bh.

src/chipset/intel_piix.c

@@ -1374,6 +1374,8 @@ static void
     else
 	dev->board_config[1] |= 0x00;
 
+    device_add(&i8254_sec_device);
+
     return dev;
 }