The Intel SIO and PIIX* southbridges now have the undocumented (by the datasheets, but fully documented by the Intel motherboard technical specifications) second PIT on ports 48h-4Bh.

src/chipset/intel_sio.c

@@ -539,6 +539,8 @@ sio_init(const device_t *info)
 
     timer_add(&dev->timer, NULL, NULL, 0);
 
+    device_add(&i8254_sec_device);
+
     return dev;
 }