Finished the Intel 450KX, changes to the memory and SMRAM API's, removed the ASUS P/I-P6RP4 from the Dev branch, added the CMD646 PCI IDE controller, and fixed some bugs on the CMD640.
This commit is contained in:
OBattler
@@ -7,7 +7,7 @@
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* This file is part of the 86Box distribution.
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*
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* Implementation of the CMD PCI-0640B controller.
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2020 Miran Grca.
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@@ -42,7 +42,8 @@ typedef struct
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{
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uint8_t vlb_idx, id,
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in_cfg, single_channel,
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regs[256];
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pci, regs[256];
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uint32_t local;
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int slot, irq_mode[2],
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irq_pin, irq_line;
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} cmd640_t;
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@@ -51,15 +52,45 @@ typedef struct
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static int next_id = 0;
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#ifdef ENABLE_CMD640_LOG
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int cmd640_do_log = ENABLE_CMD640_LOG;
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static void
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cmd640_log(const char *fmt, ...)
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{
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va_list ap;
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if (cmd640_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define cmd640_log(fmt, ...)
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#endif
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void
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cmd640_set_irq(int channel, void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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dev->regs[0x50] &= ~0x04;
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dev->regs[0x50] |= (channel >> 4);
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int irq = !!(channel & 0x40);
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if (channel & 0x01) {
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if (!(dev->regs[0x57] & 0x10) || (channel & 0x40)) {
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dev->regs[0x57] &= ~0x10;
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dev->regs[0x57] |= (channel >> 2);
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}
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} else {
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if (!(dev->regs[0x50] & 0x04) || (channel & 0x40)) {
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dev->regs[0x50] &= ~0x04;
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dev->regs[0x50] |= (channel >> 4);
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}
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}
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channel &= 0x01;
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if (dev->regs[0x50] & 0x04) {
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if (irq) {
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if (dev->irq_mode[channel] == 1)
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pci_set_irq(dev->slot, dev->irq_pin);
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else
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@@ -196,6 +227,8 @@ cmd640_vlb_read(uint16_t addr, void *priv)
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ret = dev->regs[dev->vlb_idx];
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if (dev->vlb_idx == 0x50)
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dev->regs[0x50] &= ~0x04;
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else if (dev->vlb_idx == 0x57)
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dev->regs[0x57] &= ~0x10;
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if (dev->regs[0x50] & 0x80)
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dev->in_cfg = 0;
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break;
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@@ -234,6 +267,8 @@ cmd640_pci_write(int func, int addr, uint8_t val, void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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cmd640_log("cmd640_pci_write(%i, %02X, %02X)\n", func, addr, val);
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if (func == 0x00) switch (addr) {
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case 0x04:
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dev->regs[addr] = (val & 0x41);
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@@ -315,15 +350,20 @@ cmd640_pci_read(int func, int addr, void *priv)
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ret = dev->regs[addr];
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if (addr == 0x50)
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dev->regs[0x50] &= ~0x04;
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else if (addr == 0x57)
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dev->regs[0x57] &= ~0x10;
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}
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cmd640_log("cmd640_pci_read(%i, %02X, %02X)\n", func, addr, ret);
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return ret;
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}
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static void
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cmd640_reset(void *p)
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cmd640_reset(void *priv)
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{
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cmd640_t *dev = (cmd640_t *) priv;
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int i = 0;
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for (i = 0; i < CDROM_NUM; i++) {
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@@ -342,8 +382,58 @@ cmd640_reset(void *p)
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mo_reset((scsi_common_t *) mo_drives[i].priv);
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}
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cmd640_set_irq(0x00, p);
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cmd640_set_irq(0x01, p);
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cmd640_set_irq(0x00, priv);
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cmd640_set_irq(0x01, priv);
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memset(dev->regs, 0x00, sizeof(dev->regs));
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dev->regs[0x50] = 0x02; /* Revision 02 */
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dev->regs[0x50] |= (dev->id << 3); /* Device ID: 00 = 60h, 01 = 61h, 10 = 62h, 11 = 63h */
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dev->regs[0x59] = 0x40;
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if (dev->pci) {
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cmd640_log("dev->local = %08X\n", dev->local);
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if ((dev->local & 0xffff) == 0x0a) {
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dev->regs[0x50] |= 0x40; /* Enable Base address register R/W;
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If 0, they return 0 and are read-only 8 */
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}
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dev->regs[0x00] = 0x95; /* CMD */
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dev->regs[0x01] = 0x10;
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dev->regs[0x02] = 0x40; /* PCI-0640B */
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dev->regs[0x03] = 0x06;
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dev->regs[0x04] = 0x01; /* Apparently required by the ASUS PCI/I-P5SP4 AND PCI/I-P54SP4 */
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dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
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dev->regs[0x08] = 0x02; /* Revision 02 */
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dev->regs[0x09] = dev->local; /* Programming interface */
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dev->regs[0x0a] = 0x01; /* IDE controller */
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dev->regs[0x0b] = 0x01; /* Mass storage controller */
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/* Base addresses (1F0, 3F4, 170, 374) */
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x10] = 0xf1; dev->regs[0x11] = 0x01;
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dev->regs[0x14] = 0xf5; dev->regs[0x15] = 0x03;
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dev->regs[0x18] = 0x71; dev->regs[0x19] = 0x01;
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dev->regs[0x1c] = 0x75; dev->regs[0x1d] = 0x03;
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}
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dev->regs[0x3c] = 0x14; /* IRQ 14 */
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dev->regs[0x3d] = 0x01; /* INTA */
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dev->irq_mode[0] = dev->irq_mode[1] = 0;
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dev->irq_pin = PCI_INTA;
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dev->irq_line = 14;
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} else {
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if ((dev->local & 0xffff) == 0x0078)
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dev->regs[0x50] |= 0x20; /* 0 = 178h, 17Ch; 1 = 078h, 07Ch */
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/* If bit 7 is 1, then device ID has to be written on port x78h before
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accessing the configuration registers */
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dev->in_cfg = 1; /* Configuration registers are accessible */
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}
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cmd640_ide_handlers(dev);
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}
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@@ -366,45 +456,13 @@ cmd640_init(const device_t *info)
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dev->id = next_id | 0x60;
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dev->regs[0x50] = 0x02; /* Revision 02 */
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dev->regs[0x50] |= (next_id << 3); /* Device ID: 00 = 60h, 01 = 61h, 10 = 62h, 11 = 63h */
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dev->regs[0x59] = 0x40;
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dev->pci = !!(info->flags & DEVICE_PCI);
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dev->local = info->local;
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if (info->flags & DEVICE_PCI) {
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if ((info->local & 0xffff) == 0x0a) {
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dev->regs[0x50] |= 0x40; /* Enable Base address register R/W;
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If 0, they return 0 and are read-only 8 */
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}
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dev->regs[0x00] = 0x95; /* CMD */
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dev->regs[0x01] = 0x10;
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dev->regs[0x02] = 0x40; /* PCI-0640B */
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dev->regs[0x03] = 0x06;
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dev->regs[0x04] = 0x01; /* Apparently required by the ASUS PCI/I-P5SP4 AND PCI/I-P54SP4 */
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dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
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dev->regs[0x08] = 0x02; /* Revision 02 */
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dev->regs[0x09] = info->local; /* Programming interface */
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dev->regs[0x0a] = 0x01; /* IDE controller */
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dev->regs[0x0b] = 0x01; /* Mass storage controller */
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/* Base addresses (1F0, 3F4, 170, 374) */
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if (dev->regs[0x50] & 0x40) {
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dev->regs[0x10] = 0xf1; dev->regs[0x11] = 0x01;
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dev->regs[0x14] = 0xf5; dev->regs[0x15] = 0x03;
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dev->regs[0x18] = 0x71; dev->regs[0x19] = 0x01;
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dev->regs[0x1c] = 0x75; dev->regs[0x1d] = 0x03;
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}
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dev->regs[0x3c] = 0x14; /* IRQ 14 */
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dev->regs[0x3d] = 0x01; /* INTA */
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device_add(&ide_pci_2ch_device);
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dev->slot = pci_add_card(PCI_ADD_IDE, cmd640_pci_read, cmd640_pci_write, dev);
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dev->irq_mode[0] = dev->irq_mode[1] = 0;
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dev->irq_pin = PCI_INTA;
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dev->irq_line = 14;
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ide_set_bus_master(0, NULL, cmd640_set_irq, dev);
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ide_set_bus_master(1, NULL, cmd640_set_irq, dev);
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@@ -416,12 +474,6 @@ cmd640_init(const device_t *info)
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// ide_pri_disable();
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} else if (info->flags & DEVICE_VLB) {
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if ((info->local & 0xffff) == 0x0078)
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dev->regs[0x50] |= 0x20; /* 0 = 178h, 17Ch; 1 = 078h, 07Ch */
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/* If bit 7 is 1, then device ID has to be written on port x78h before
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accessing the configuration registers */
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dev->in_cfg = 1; /* Configuration register are accessible */
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device_add(&ide_vlb_2ch_device);
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io_sethandler(info->local & 0xffff, 0x0008,
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@@ -432,11 +484,10 @@ cmd640_init(const device_t *info)
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dev->single_channel = !!(info->local & 0x20000);
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if (!dev->single_channel)
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ide_sec_disable();
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next_id++;
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cmd640_reset(dev);
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return dev;
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}
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@@ -445,7 +496,7 @@ const device_t ide_cmd640_vlb_device = {
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"CMD PCI-0640B VLB",
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DEVICE_VLB,
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0x0078,
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cmd640_init, cmd640_close, NULL,
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cmd640_init, cmd640_close, cmd640_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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@@ -454,7 +505,7 @@ const device_t ide_cmd640_vlb_178_device = {
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"CMD PCI-0640B VLB (Port 178h)",
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DEVICE_VLB,
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0x0178,
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cmd640_init, cmd640_close, NULL,
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cmd640_init, cmd640_close, cmd640_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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