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Finished the Intel 450KX, changes to the memory and SMRAM API's, removed the ASUS P/I-P6RP4 from the Dev branch, added the CMD646 PCI IDE controller, and fixed some bugs on the CMD640.

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This commit is contained in:
OBattler
2021-10-26 01:54:35 +02:00
parent 08f64058eb
commit 77d73ed3c2
22 changed files with 1269 additions and 305 deletions
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24
src/disk/hdc_ide_sff8038i.c
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@@ -47,10 +47,10 @@
static int next_id = 0;
static uint8_t sff_bus_master_read(uint16_t port, void *priv);
uint8_t sff_bus_master_read(uint16_t port, void *priv);
static uint16_t sff_bus_master_readw(uint16_t port, void *priv);
static uint32_t sff_bus_master_readl(uint16_t port, void *priv);
static void sff_bus_master_write(uint16_t port, uint8_t val, void *priv);
void sff_bus_master_write(uint16_t port, uint8_t val, void *priv);
static void sff_bus_master_writew(uint16_t port, uint16_t val, void *priv);
static void sff_bus_master_writel(uint16_t port, uint32_t val, void *priv);
@@ -112,7 +112,7 @@ sff_bus_master_next_addr(sff8038i_t *dev)
}
static void
void
sff_bus_master_write(uint16_t port, uint8_t val, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
@@ -138,6 +138,9 @@ sff_bus_master_write(uint16_t port, uint8_t val, void *priv)
dev->command = val;
break;
case 1:
dev->dma_mode = val & 0x03;
break;
case 2:
sff_log("sff Status: val = %02X, old = %02X\n", val, dev->status);
dev->status &= 0x07;
@@ -177,6 +180,7 @@ sff_bus_master_writew(uint16_t port, uint16_t val, void *priv)
switch (port & 7) {
case 0:
case 1:
case 2:
sff_bus_master_write(port, val & 0xff, priv);
break;
@@ -202,6 +206,7 @@ sff_bus_master_writel(uint16_t port, uint32_t val, void *priv)
switch (port & 7) {
case 0:
case 1:
case 2:
sff_bus_master_write(port, val & 0xff, priv);
break;
@@ -214,7 +219,7 @@ sff_bus_master_writel(uint16_t port, uint32_t val, void *priv)
}
static uint8_t
uint8_t
sff_bus_master_read(uint16_t port, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
@@ -225,6 +230,9 @@ sff_bus_master_read(uint16_t port, void *priv)
case 0:
ret = dev->command;
break;
case 1:
ret = dev->dma_mode & 0x03;
break;
case 2:
ret = dev->status & 0x67;
break;
@@ -257,6 +265,7 @@ sff_bus_master_readw(uint16_t port, void *priv)
switch (port & 7) {
case 0:
case 1:
case 2:
ret = (uint16_t) sff_bus_master_read(port, priv);
break;
@@ -283,6 +292,7 @@ sff_bus_master_readl(uint16_t port, void *priv)
switch (port & 7) {
case 0:
case 1:
case 2:
ret = (uint32_t) sff_bus_master_read(port, priv);
break;
@@ -297,7 +307,7 @@ sff_bus_master_readl(uint16_t port, void *priv)
}
static int
int
sff_bus_master_dma(int channel, uint8_t *data, int transfer_length, int out, void *priv)
{
sff8038i_t *dev = (sff8038i_t *) priv;
@@ -311,8 +321,10 @@ sff_bus_master_dma(int channel, uint8_t *data, int transfer_length, int out, voi
sop = out ? "Read" : "Writ";
#endif
if (!(dev->status & 1))
if (!(dev->status & 1)) {
sff_log("DMA disabled\n");
return 2; /*DMA disabled*/
}
sff_log("SFF-8038i Bus master %s: %i bytes\n", out ? "write" : "read", transfer_length);