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Finished the Intel 450KX, changes to the memory and SMRAM API's, removed the ASUS P/I-P6RP4 from the Dev branch, added the CMD646 PCI IDE controller, and fixed some bugs on the CMD640.

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This commit is contained in:
OBattler
2021-10-26 01:54:35 +02:00
parent 08f64058eb
commit 77d73ed3c2
22 changed files with 1269 additions and 305 deletions
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4
src/include/86box/chipset.h
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@@ -83,10 +83,7 @@ extern const device_t i440bx_device;
extern const device_t i440bx_no_agp_device;
extern const device_t i440gx_device;
extern const device_t i440zx_device;
#if defined(DEV_BRANCH) && defined(USE_I450KX)
extern const device_t i450kx_device;
#endif
extern const device_t sio_device;
extern const device_t sio_zb_device;
@@ -133,6 +130,7 @@ extern const device_t stpc_serial_device;
extern const device_t stpc_lpt_device;
/* UMC */
extern const device_t umc_um82c49x_device;
extern const device_t umc_8886f_device;
extern const device_t umc_8886af_device;
extern const device_t umc_hb4_device;

3
src/include/86box/hdc.h
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@@ -56,6 +56,9 @@ extern const device_t ide_cmd640_vlb_178_device; /* CMD PCI-640B VLB (Port 178h
extern const device_t ide_cmd640_pci_device; /* CMD PCI-640B PCI */
extern const device_t ide_cmd640_pci_legacy_only_device; /* CMD PCI-640B PCI (Legacy Mode Only) */
extern const device_t ide_cmd640_pci_single_channel_device; /* CMD PCI-640B PCI (Only primary channel) */
extern const device_t ide_cmd646_device; /* CMD PCI-646 */
extern const device_t ide_cmd646_legacy_only_device; /* CMD PCI-646 (Legacy Mode Only) */
extern const device_t ide_cmd646_single_channel_device; /* CMD PCI-646 (Only primary channel) */
extern const device_t ide_opti611_vlb_device; /* OPTi 82c611/611A VLB */

11
src/include/86box/hdc_ide_sff8038i.h
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@@ -19,8 +19,10 @@
typedef struct
{
uint8_t command, status,
ptr0, enabled;
uint16_t base, pad;
ptr0, enabled,
dma_mode, pad,
pad0, pad1;
uint16_t base, pad2;
uint32_t ptr, ptr_cur,
addr;
int count, eot,
@@ -39,6 +41,11 @@ extern int sff_bus_master_dma_write(int channel, uint8_t *data, int transfer_len
extern void sff_bus_master_set_irq(int channel, void *priv);
extern int sff_bus_master_dma(int channel, uint8_t *data, int transfer_length, int out, void *priv);
extern void sff_bus_master_write(uint16_t port, uint8_t val, void *priv);
extern uint8_t sff_bus_master_read(uint16_t port, void *priv);
extern void sff_bus_master_reset(sff8038i_t *dev, uint16_t old_base);
extern void sff_set_slot(sff8038i_t *dev, int slot);

2
src/include/86box/machine.h
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@@ -539,9 +539,7 @@ extern int machine_at_ficva503a_init(const machine_t *);
extern int machine_at_sy_5ema_pro_init(const machine_t *);
/* m_at_socket8.c */
#if defined(DEV_BRANCH) && defined(USE_I450KX)
extern int machine_at_p6rp4_init(const machine_t *);
#endif
extern int machine_at_686nx_init(const machine_t *);
extern int machine_at_v60n_init(const machine_t *);

8
src/include/86box/mem.h
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@@ -145,10 +145,18 @@
mem_set_access(ACCESS_SMM, 0, base, size, access)
#define mem_set_mem_state_both(base, size, access) \
mem_set_access(ACCESS_ALL, 0, base, size, access)
#define mem_set_mem_state_cpu_both(base, size, access) \
mem_set_access(ACCESS_CPU_BOTH, 0, base, size, access)
#define mem_set_mem_state_bus_both(base, size, access) \
mem_set_access(ACCESS_BUS_BOTH, 0, base, size, access)
#define mem_set_mem_state_smram(smm, base, size, is_smram) \
mem_set_access((smm ? ACCESS_SMM : ACCESS_NORMAL), 1, base, size, is_smram)
#define mem_set_mem_state_smram_ex(smm, base, size, is_smram) \
mem_set_access((smm ? ACCESS_SMM : ACCESS_NORMAL), 2, base, size, is_smram)
#define mem_set_access_smram_cpu(smm, base, size, is_smram) \
mem_set_access((smm ? ACCESS_CPU_SMM : ACCESS_CPU), 1, base, size, is_smram)
#define mem_set_access_smram_bus(smm, base, size, is_smram) \
mem_set_access((smm ? ACCESS_BUS_SMM : ACCESS_BUS), 1, base, size, is_smram)
#define flushmmucache_cr3 \
flushmmucache_nopc

1
src/include/86box/nvr.h
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@@ -95,6 +95,7 @@ extern const device_t piix4_nvr_device;
extern const device_t ls486e_nvr_device;
extern const device_t ami_apollo_nvr_device;
extern const device_t via_nvr_device;
extern const device_t p6rp4_nvr_device;
#endif

7
src/include/86box/smram.h
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@@ -39,12 +39,19 @@ extern void smram_recalc_all(int ret);
extern void smram_del(smram_t *smr);
/* Add a SMRAM mapping. */
extern smram_t *smram_add(void);
/* Set memory state in the specified model (normal or SMM) according to the specified flags,
separately for bus and CPU. */
extern void smram_map_ex(int bus, int smm, uint32_t addr, uint32_t size, int is_smram);
/* Set memory state in the specified model (normal or SMM) according to the specified flags. */
extern void smram_map(int smm, uint32_t addr, uint32_t size, int is_smram);
/* Disable a specific SMRAM mapping. */
extern void smram_disable(smram_t *smr);
/* Disable all SMRAM mappings. */
extern void smram_disable_all(void);
/* Enable SMRAM mappings according to flags for both normal and SMM modes, separately for bus
and CPU. */
extern void smram_enable_ex(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size,
int flags_normal, int flags_normal_bus, int flags_smm, int flags_smm_bus);
/* Enable SMRAM mappings according to flags for both normal and SMM modes. */
extern void smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size,
int flags_normal, int flags_smm);