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Some minor fixes, the PS/2 mouse command F0h (set remote mode) is now implemented, the PS/2 mouse command F3h (set sample rate) now actually changes the host mouse polling rate, and the Intel SIO IB and ZB now forcibly initialize a keyboard and mouse IRQ latch if the board has a PS/2 keyboard controller, to simulate the presence of a latch external to the chip.

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This commit is contained in:
OBattler
2023-04-26 01:42:23 +02:00
parent 3b54cb085e
commit 78a897f07a
7 changed files with 56 additions and 15 deletions
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20
src/chipset/intel_sio.c
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@@ -200,9 +200,11 @@ sio_write(int func, int addr, uint8_t val, void *priv)
dev->regs[addr] = val;
break;
case 0x4c:
dev->regs[addr] = (val & 0x7f);
break;
case 0x4d:
dev->regs[addr] = (val & 0x7f);
pic_mouse_latch(!!(val & 0x10));
// pic_mouse_latch(!!(val & 0x10));
break;
case 0x4f:
dev->regs[addr] = val;
@@ -394,7 +396,7 @@ sio_reset_hard(void *priv)
dev->regs[0x4b] = 0x0f;
dev->regs[0x4c] = 0x56;
dev->regs[0x4d] = 0x40;
pic_mouse_latch(0x00);
// pic_mouse_latch(0x00);
dev->regs[0x4e] = 0x07;
dev->regs[0x4f] = 0x4f;
dev->regs[0x57] = 0x04;
@@ -544,7 +546,19 @@ sio_init(const device_t *info)
// device_add(&i8254_sec_device);
pic_kbd_latch(0x01);
// pic_kbd_latch(0x01);
/* The situation is as follow: SIO.AB has the IRQ 1 latch but SIO.IB and SIO.ZB do not,
and I suspect that because of that, the IRQ 12 latch on SIO.IB and SIO.ZB, while
evidently planned and documented in the datashet, was basically non-functional, and
motherboard manufacturers had to install their own latches to use PS/2 keyboards
and/or mice. One such example is the AMI Excalibur PCI Pentium, which never enables
the SIO.ZB's IRQ 12 latch but clearly expects one since otherwise, the PS/2 mouse
behaves erractically in the WinBIOS CMOS Setup. */
if (machine_has_bus(machine, MACHINE_BUS_PS2)) {
pic_kbd_latch(0x01);
pic_mouse_latch(0x01);
}
return dev;
}