PIC rewrite, proper SMRAM API, complete SiS 471 rewrite and addition of 40x, 460, and 461, changes to mem.c/h, disabled Voodoo memory dumping on exit, bumped SDL Hardware scale quality to 2, bumped IDE/ATAPI drives to ATA-6, finally bumped emulator version to 3.0, redid the bus type ID's to allow for planned ATAPI hard disks, made SST flash set its high mappings to the correct address if the CPU is 16-bit, and added the SiS 401 AMI 486 Clone, AOpen Vi15G, and the Soyo 4SA2 (486 with SiS 496/497 that can boot from CD-ROM), assorted 286+ protected mode fixes (for slightly more accuracy), and fixes to 808x emulation (MS Word 1.0 and 1.10 for DOS now work correctly from floppy).
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OBattler
@@ -22,6 +22,7 @@
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/mem.h>
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#include <86box/smram.h>
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#include <86box/io.h>
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#include <86box/rom.h>
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#include <86box/device.h>
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@@ -57,6 +58,7 @@ typedef struct
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drb_unit, drb_default;
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uint8_t regs[256], regs_locked[256];
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int type;
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smram_t *smram_low, *smram_high;
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} i4x0_t;
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@@ -101,36 +103,18 @@ i4x0_map(uint32_t addr, uint32_t size, int state)
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}
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static void
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i4x0_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
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{
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mem_set_mem_state_smram(smm, addr, size, is_smram);
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}
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static void
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i4x0_smram_handler_phase0(i4x0_t *dev)
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{
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uint32_t tom = (mem_size << 10);
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/* Disable any active mappings. */
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if (smram[0].size != 0x00000000) {
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i4x0_smram_map(0, smram[0].host_base, smram[0].size, 0);
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i4x0_smram_map(1, smram[0].host_base, smram[0].size, 0);
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memset(&smram[0], 0x00, sizeof(smram_t));
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mem_mapping_disable(&ram_smram_mapping[0]);
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}
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if ((dev->type >= INTEL_440BX) && (smram[1].size != 0x00000000)) {
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i4x0_smram_map(1, smram[1].host_base, smram[1].size, 0);
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if ((dev->type >= INTEL_440BX) && smram_enabled(dev->smram_high)) {
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tom -= (1 << 20);
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mem_set_mem_state_smm(tom, (1 << 20), MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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memset(&smram[1], 0x00, sizeof(smram_t));
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mem_mapping_disable(&ram_smram_mapping[1]);
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}
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/* Disable any active mappings. */
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smram_disable_all();
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}
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@@ -158,20 +142,9 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
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}
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}
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if (((regs[0x72] & 0x70) == 0x40) || ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20))) {
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smram[0].host_base = base[0];
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smram[0].ram_base = base[0] & 0x000f0000;
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smram[0].size = size[0];
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mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size[0]);
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mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
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/* If D_OPEN = 1 and D_LCK = 0, extended SMRAM is visible outside SMM. */
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i4x0_smram_map(0, base[0], size[0], ((regs[0x72] & 0x70) == 0x40));
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/* If the register is set accordingly, disable the mapping also in SMM. */
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i4x0_smram_map(1, base[0], size[0], ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20)));
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}
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if (((regs[0x72] & 0x70) == 0x40) || ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20)))
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smram_enable(dev->smram_low, base[0], base[0] & 0x000f0000, size[0],
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((regs[0x72] & 0x70) == 0x40), ((regs[0x72] & 0x08) && !(regs[0x72] & 0x20)));
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/* TSEG mapping. */
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if (dev->type >= INTEL_440BX) {
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@@ -183,18 +156,10 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
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base[1] = size[1] = 0x00000000;
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if (size[1] != 0x00000000) {
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smram[1].host_base = base[1] + (1 << 28);
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smram[1].ram_base = base[1];
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smram[1].size = size[1];
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mem_mapping_set_addr(&ram_smram_mapping[1], smram[1].host_base, smram[1].size);
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if (smram[1].ram_base < (1 << 30))
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mem_mapping_set_exec(&ram_smram_mapping[1], ram + smram[1].ram_base);
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else
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mem_mapping_set_exec(&ram_smram_mapping[1], ram2 + smram[1].ram_base - (1 << 30));
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smram_enable(dev->smram_high, base[1] + (1 << 28), base[1], size[1],
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0, 1);
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mem_set_mem_state_smm(base[1], size[1], MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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i4x0_smram_map(1, smram[1].host_base, size[1], 1);
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}
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}
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} else {
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@@ -220,18 +185,8 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
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}
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if (((((regs[0x72] & 0x38) == 0x20) || s) || (!(regs[0x72] & 0x10) || s)) && (size[0] != 0x00000000)) {
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smram[0].host_base = base[0];
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smram[0].ram_base = base[0];
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smram[0].size = size[0];
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mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, size[0]);
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mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base);
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/* If OSS = 1 and LSS = 0, extended SMRAM is visible outside SMM. */
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i4x0_smram_map(0, base[0], size[0], (((regs[0x72] & 0x38) == 0x20) || s));
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/* If the register is set accordingly, disable the mapping also in SMM. */
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i4x0_smram_map(0, base[0], size[0], (!(regs[0x72] & 0x10) || s));
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smram_enable(dev->smram_low, base[0], base[0], size[0],
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(((regs[0x72] & 0x38) == 0x20) || s), (!(regs[0x72] & 0x10) || s));
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}
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}
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@@ -1306,9 +1261,12 @@ i4x0_reset(void *priv)
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static void
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i4x0_close(void *p)
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{
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i4x0_t *i4x0 = (i4x0_t *)p;
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i4x0_t *dev = (i4x0_t *)p;
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free(i4x0);
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smram_del(dev->smram_high);
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smram_del(dev->smram_low);
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free(dev);
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}
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@@ -1320,6 +1278,9 @@ static void
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memset(dev, 0, sizeof(i4x0_t));
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dev->smram_low = smram_add();
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dev->smram_high = smram_add();
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dev->type = info->local & 0xff;
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regs = (uint8_t *) dev->regs;
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