PIC rewrite, proper SMRAM API, complete SiS 471 rewrite and addition of 40x, 460, and 461, changes to mem.c/h, disabled Voodoo memory dumping on exit, bumped SDL Hardware scale quality to 2, bumped IDE/ATAPI drives to ATA-6, finally bumped emulator version to 3.0, redid the bus type ID's to allow for planned ATAPI hard disks, made SST flash set its high mappings to the correct address if the CPU is 16-bit, and added the SiS 401 AMI 486 Clone, AOpen Vi15G, and the Soyo 4SA2 (486 with SiS 496/497 that can boot from CD-ROM), assorted 286+ protected mode fixes (for slightly more accuracy), and fixes to 808x emulation (MS Word 1.0 and 1.10 for DOS now work correctly from floppy).
This commit is contained in:
OBattler
@@ -56,7 +56,7 @@ extern "C" {
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enum {
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CDROM_BUS_DISABLED = 0,
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CDROM_BUS_ATAPI = 4,
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CDROM_BUS_ATAPI = 5,
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CDROM_BUS_SCSI,
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CDROM_BUS_USB
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};
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@@ -89,6 +89,9 @@ extern const device_t opti5x7_device;
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/* SiS */
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extern const device_t rabbit_device;
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extern const device_t sis_85c401_device;
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extern const device_t sis_85c460_device;
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extern const device_t sis_85c461_device;
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extern const device_t sis_85c471_device;
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extern const device_t sis_85c496_device;
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extern const device_t sis_85c496_ls486e_device;
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@@ -110,16 +113,13 @@ extern const device_t stpc_lpt_device;
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extern const device_t umc491_device;
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/* VIA */
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extern const device_t via_vt82c49x_device;
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extern const device_t via_vt82c49x_ide_device;
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extern const device_t via_vt82c505_device;
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extern const device_t via_vpx_device;
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extern const device_t via_vp3_device;
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extern const device_t via_mvp3_device;
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extern const device_t via_apro_device;
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extern const device_t via_vt82c586b_device;
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extern const device_t via_vt82c596_device;
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extern const device_t via_vt82c596b_device;
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@@ -39,7 +39,7 @@ extern int fdc_type;
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typedef struct {
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uint8_t dor, stat, command, processed_cmd, dat, st0, swap, dtl;
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uint8_t swwp, disable_write;
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uint8_t swwp, disable_write, st5, st6, error;
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uint8_t params[8], res[11];
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uint8_t specify[2];
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uint8_t config, pretrk;
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@@ -66,6 +66,7 @@ enum {
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HDD_BUS_XTA,
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HDD_BUS_ESDI,
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HDD_BUS_IDE,
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HDD_BUS_ATAPI,
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HDD_BUS_SCSI,
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HDD_BUS_USB
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};
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@@ -144,18 +144,16 @@
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#define IDS_4352 4352 // "MFM/RLL"
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#define IDS_4353 4353 // "XT IDE"
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#define IDS_4354 4354 // "ESDI"
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#define IDS_4355 4355 // "IDE (PIO-only)"
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#define IDS_4356 4356 // "IDE (PIO+DMA)"
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#define IDS_4355 4355 // "IDE"
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#define IDS_4356 4356 // "ATAPI"
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#define IDS_4357 4357 // "SCSI"
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#define IDS_4358 4358 // "SCSI (removable)"
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#define IDS_4608 4608 // "MFM/RLL (%01i:%01i)"
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#define IDS_4609 4609 // "XT IDE (%01i:%01i)"
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#define IDS_4610 4610 // "ESDI (%01i:%01i)"
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#define IDS_4611 4611 // "IDE (PIO-only) (%01i:%01i)"
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#define IDS_4612 4612 // "IDE (PIO+DMA) (%01i:%01i)"
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#define IDS_4611 4611 // "IDE (%01i:%01i)"
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#define IDS_4612 4612 // "ATAPI (%01i:%01i)"
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#define IDS_4613 4613 // "SCSI (%02i:%02i)"
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#define IDS_4614 4614 // "SCSI (removable) (%02i:%02i)"
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#define IDS_5120 5120 // "CD-ROM %i (%s): %s"
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@@ -163,16 +161,16 @@
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#define IDS_5377 5377 // <Reserved>
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#define IDS_5378 5378 // <Reserved>
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#define IDS_5379 5379 // <Reserved>
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#define IDS_5380 5380 // "ATAPI (PIO-only)"
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#define IDS_5381 5381 // "ATAPI (PIO and DMA)"
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#define IDS_5380 5380 // <Reserved>
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#define IDS_5381 5381 // "ATAPI"
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#define IDS_5382 5382 // "SCSI"
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#define IDS_5632 5632 // "Disabled"
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#define IDS_5633 5633 // <Reserved>
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#define IDS_5634 5634 // <Reserved>
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#define IDS_5635 5635 // <Reserved>
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#define IDS_5636 5636 // "ATAPI (PIO-only) (%01i:%01i)"
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#define IDS_5637 5637 // "ATAPI (PIO and DMA) (%01i:%01i)"
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#define IDS_5636 5636 // <Reserved>
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#define IDS_5637 5637 // "ATAPI (%01i:%01i)"
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#define IDS_5638 5638 // "SCSI (%02i:%02i)"
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#define IDS_5888 5888 // "160 kB"
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@@ -212,8 +210,8 @@
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#define STR_NUM_2048 92
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#define STR_NUM_3072 11
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#define STR_NUM_4096 18
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#define STR_NUM_4352 7
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#define STR_NUM_4608 7
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#define STR_NUM_4352 6
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#define STR_NUM_4608 6
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#define STR_NUM_5120 1
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#define STR_NUM_5376 7
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#define STR_NUM_5632 7
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@@ -23,43 +23,65 @@
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/* Machine feature flags. */
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#ifdef NEW_FLAGS
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#define MACHINE_PC 0x000000 /* PC architecture */
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#define MACHINE_AT 0x000001 /* PC/AT architecture */
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#define MACHINE_PS2 0x000002 /* PS/2 architecture */
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#define MACHINE_ISA 0x000010 /* sys has ISA bus */
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#define MACHINE_CBUS 0x000020 /* sys has C-BUS bus */
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#define MACHINE_EISA 0x000040 /* sys has EISA bus */
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#define MACHINE_VLB 0x000080 /* sys has VL bus */
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#define MACHINE_MCA 0x000100 /* sys has MCA bus */
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#define MACHINE_PCI 0x000200 /* sys has PCI bus */
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#define MACHINE_AGP 0x000400 /* sys has AGP bus */
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#define MACHINE_HDC 0x001000 /* sys has int HDC */
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#define MACHINE_VIDEO 0x002000 /* sys has int video */
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#define MACHINE_VIDEO_FIXED 0x004000 /* sys has ONLY int video */
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#define MACHINE_MOUSE 0x008000 /* sys has int mouse */
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#define MACHINE_SOUND 0x010000 /* sys has int sound */
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#define MACHINE_NONMI 0x020000 /* sys does not have NMI's */
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#define MACHINE_FDC 0x040000 /* sys has int FDC */
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#else
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#define MACHINE_PC 0x000000 /* PC architecture */
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#define MACHINE_AT 0x000001 /* PC/AT architecture */
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#define MACHINE_PS2 0x000002 /* PS/2 architecture */
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#define MACHINE_ISA 0x000010 /* sys has ISA bus */
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#define MACHINE_CBUS 0x000020 /* sys has C-BUS bus */
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#define MACHINE_EISA 0x000040 /* sys has EISA bus */
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#define MACHINE_VLB 0x000080 /* sys has VL bus */
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#define MACHINE_MCA 0x000100 /* sys has MCA bus */
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#define MACHINE_PCI 0x000200 /* sys has PCI bus */
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#define MACHINE_AGP 0x000400 /* sys has AGP bus */
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#define MACHINE_HDC 0x001000 /* sys has int HDC */
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#define MACHINE_VIDEO 0x002000 /* sys has int video */
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#define MACHINE_VIDEO_FIXED 0x004000 /* sys has ONLY int video */
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#define MACHINE_MOUSE 0x008000 /* sys has int mouse */
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#define MACHINE_SOUND 0x010000 /* sys has int sound */
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#define MACHINE_NONMI 0x020000 /* sys does not have NMI's */
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#define MACHINE_FDC 0x040000 /* sys has int FDC */
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#endif
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// #define MACHINE_PC 0x00000000 /* PC architecture */
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/* Feature flags for features. */
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#define MACHINE_NONMI 0x00000001 /* sys does not have NMI's */
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/* Feature flags for BUS'es. */
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#define MACHINE_BUS_ISA 0x00000004 /* sys has ISA bus */
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#define MACHINE_BUS_ISA16 0x00000008 /* sys has ISA16 bus - PC/AT architecture */
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#define MACHINE_BUS_CBUS 0x00000010 /* sys has C-BUS bus */
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#define MACHINE_BUS_PS2 0x00000020 /* system has PS/2 keyboard and mouse ports */
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#define MACHINE_BUS_EISA 0x00000040 /* sys has EISA bus */
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#define MACHINE_BUS_VLB 0x00000080 /* sys has VL bus */
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#define MACHINE_BUS_MCA 0x00000100 /* sys has MCA bus */
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#define MACHINE_BUS_PCI 0x00000200 /* sys has PCI bus */
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#define MACHINE_BUS_PCMCIA 0x00000400 /* sys has PCMCIA bus */
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#define MACHINE_BUS_AGP 0x00000800 /* sys has AGP bus */
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/* Combined flags. */
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#define MACHINE_PC 0x00000004 /* sys is PC/XT-compatible (ISA) */
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#define MACHINE_AT 0x0000000C /* sys is AT-compatible (ISA + ISA16) */
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#define MACHINE_PC98 0x00000010 /* sys is NEC PC-98x1 series */
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#define MACHINE_EISA 0x0000004C /* sys is AT-compatible with EISA */
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#define MACHINE_VLB 0x0000008C /* sys is AT-compatible with VLB */
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#define MACHINE_VLB98 0x00000090 /* sys is NEC PC-98x1 series with VLB (did that even exist?) */
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#define MACHINE_VLBE 0x000000CC /* sys is AT-compatible with EISA and VLB */
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#define MACHINE_MCA 0x00000100 /* sys is MCA */
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#define MACHINE_PCI 0x0000020C /* sys is AT-compatible with PCI */
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#define MACHINE_PCI98 0x00000210 /* sys is NEC PC-98x1 series with PCI */
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#define MACHINE_PCIE 0x0000024C /* sys is AT-compatible with PCI, and EISA */
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#define MACHINE_PCIV 0x0000028C /* sys is AT-compatible with PCI and VLB */
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#define MACHINE_PCIVE 0x000002CC /* sys is AT-compatible with PCI, VLB, and EISA */
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#define MACHINE_PCMCIA 0x00000400 /* sys is AT-compatible laptop with PCMCIA */
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#define MACHINE_AGP 0x00000A0C /* sys is AT-compatible with AGP */
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#define MACHINE_AGP98 0x00000A10 /* sys is NEC PC-98x1 series with AGP (did that even exist?) */
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#define MACHINE_IS_AT 0x00000FCC /* sys is AT-compatible (ISA + ISA16) */
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/* Feature flags for miscellaneous internal devices. */
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#define MACHINE_VIDEO 0x00001000 /* sys has int video */
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#define MACHINE_VIDEO_ONLY 0x00002000 /* sys has fixed video */
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#define MACHINE_MOUSE 0x00004000 /* sys has int mouse */
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#define MACHINE_SOUND 0x00008000 /* sys has int sound */
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#define MACHINE_FDC 0x00010000 /* sys has int FDC */
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#define MACHINE_NIC 0x00020000 /* sys has int NIC */
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/* Combined flags. */
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#define MACHINE_VIDEO_FIXED 0x00003000 /* sys has fixed int video */
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/* Feature flags for internal storage controllers. */
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#define MACHINE_HDC 0x0FFC0000 /* sys has int HDC */
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#define MACHINE_MFM 0x00100000 /* sys has int MFM/RLL */
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#define MACHINE_XTA 0x00200000 /* sys has int XTA */
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#define MACHINE_ESDI 0x00400000 /* sys has int ESDI */
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#define MACHINE_IDE_PRI 0x00800000 /* sys has int pri IDE/ATAPI */
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#define MACHINE_IDE_SEC 0x01000000 /* sys has int sec IDE/ATAPI */
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#define MACHINE_IDE_TER 0x02000000 /* sys has int ter IDE/ATAPI */
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#define MACHINE_IDE_QUA 0x04000000 /* sys has int qua IDE/ATAPI */
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#define MACHINE_SCSI_PRI 0x08000000 /* sys has int pri SCSI */
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#define MACHINE_SCSI_SEC 0x10000000 /* sys has int sec SCSI */
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#define MACHINE_USB 0x20000000 /* sys has int USB */
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/* Combined flags. */
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#define MACHINE_IDE 0x00800000 /* sys has int single IDE/ATAPI - mark as pri IDE/ATAPI */
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#define MACHINE_IDE_DUAL 0x01800000 /* sys has int dual IDE/ATAPI - mark as both pri and sec IDE/ATAPI */
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#define MACHINE_IDE_QUAD 0x07800000 /* sys has int quad IDE/ATAPI - mark as dual + both ter and and qua IDE/ATAPI */
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#define MACHINE_SCSI 0x08000000 /* sys has int single SCSI - mark as pri SCSI */
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#define MACHINE_SCSI_DUAL 0x18000000 /* sys has int dual SCSI - mark as both pri and sec SCSI */
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#define IS_ARCH(m, a) (machines[(m)].flags & (a)) ? 1 : 0;
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@@ -274,17 +296,19 @@ extern int machine_at_opti495_mr_init(const machine_t *);
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extern int machine_at_403tg_init(const machine_t *);
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extern int machine_at_pc330_6571_init(const machine_t *);
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extern int machine_at_sis401_init(const machine_t *);
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extern int machine_at_vli486sv2g_init(const machine_t *);
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extern int machine_at_ami471_init(const machine_t *);
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extern int machine_at_dtk486_init(const machine_t *);
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extern int machine_at_px471_init(const machine_t *);
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#if defined(DEV_BRANCH) && defined(USE_WIN471)
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extern int machine_at_win471_init(const machine_t *);
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#endif
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extern int machine_at_vi15g_init(const machine_t *);
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extern int machine_at_r418_init(const machine_t *);
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extern int machine_at_ls486e_init(const machine_t *);
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extern int machine_at_4dps_init(const machine_t *);
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extern int machine_at_4sa2_init(const machine_t *);
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extern int machine_at_alfredo_init(const machine_t *);
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extern int machine_at_486sp3g_init(const machine_t *);
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extern int machine_at_486ap4_init(const machine_t *);
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@@ -346,6 +370,7 @@ extern int machine_at_acerv30_init(const machine_t *);
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#ifdef EMU_DEVICE_H
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extern const device_t *at_endeavor_get_device(void);
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extern const device_t *at_pb520r_get_device(void);
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extern const device_t *at_thor_get_device(void);
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#endif
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/* m_at_socket7_s7.c */
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@@ -183,14 +183,6 @@ typedef struct _page_ {
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#endif
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typedef struct
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{
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uint32_t size,
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host_base,
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ram_base;
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} smram_t;
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extern uint8_t *ram, *ram2;
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extern uint32_t rammask;
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@@ -207,15 +199,13 @@ extern uintptr_t * writelookup2;
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extern int writelnext;
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extern uint32_t ram_mapped_addr[64];
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|
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extern mem_mapping_t base_mapping,
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ram_low_mapping,
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extern mem_mapping_t ram_low_mapping,
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#if 1
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ram_mid_mapping,
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#endif
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ram_remapped_mapping,
|
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ram_high_mapping,
|
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ram_2gb_mapping,
|
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ram_smram_mapping[2],
|
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bios_mapping,
|
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bios_high_mapping;
|
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|
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@@ -225,7 +215,6 @@ extern page_t *pages,
|
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**page_lookup;
|
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|
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extern uint32_t get_phys_virt, get_phys_phys;
|
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extern smram_t smram[2];
|
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|
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extern int shadowbios,
|
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shadowbios_write;
|
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@@ -242,6 +231,9 @@ extern int mem_a20_state,
|
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mem_a20_key;
|
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|
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|
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extern uint8_t read_mem_b(uint32_t addr);
|
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extern void write_mem_b(uint32_t addr, uint8_t val);
|
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|
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#ifndef USE_NEW_DYNAREC
|
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#define readmemb(a) ((readlookup2[(a)>>12]==-1)?readmembl(a):*(uint8_t *)(readlookup2[(a) >> 12] + (a)))
|
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#define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (s)==0xFFFFFFFF || (((s)+(a)) & 1))?readmemwl(s,a):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
|
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@@ -258,14 +250,14 @@ extern void writememll(uint32_t seg, uint32_t addr, uint32_t val);
|
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extern uint64_t readmemql(uint32_t seg, uint32_t addr);
|
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extern void writememql(uint32_t seg, uint32_t addr, uint64_t val);
|
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#else
|
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uint8_t readmembl(uint32_t addr);
|
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void writemembl(uint32_t addr, uint8_t val);
|
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uint16_t readmemwl(uint32_t addr);
|
||||
void writememwl(uint32_t addr, uint16_t val);
|
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uint32_t readmemll(uint32_t addr);
|
||||
void writememll(uint32_t addr, uint32_t val);
|
||||
uint64_t readmemql(uint32_t addr);
|
||||
void writememql(uint32_t addr, uint64_t val);
|
||||
extern uint8_t readmembl(uint32_t addr);
|
||||
extern void writemembl(uint32_t addr, uint8_t val);
|
||||
extern uint16_t readmemwl(uint32_t addr);
|
||||
extern void writememwl(uint32_t addr, uint16_t val);
|
||||
extern uint32_t readmemll(uint32_t addr);
|
||||
extern void writememll(uint32_t addr, uint32_t val);
|
||||
extern uint64_t readmemql(uint32_t addr);
|
||||
extern void writememql(uint32_t addr, uint64_t val);
|
||||
#endif
|
||||
|
||||
extern uint8_t *getpccache(uint32_t a);
|
||||
@@ -326,16 +318,12 @@ extern void mem_write_ram(uint32_t addr, uint8_t val, void *priv);
|
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extern void mem_write_ramw(uint32_t addr, uint16_t val, void *priv);
|
||||
extern void mem_write_raml(uint32_t addr, uint32_t val, void *priv);
|
||||
|
||||
extern uint8_t mem_read_smram(uint32_t addr, void *priv);
|
||||
extern uint16_t mem_read_smramw(uint32_t addr, void *priv);
|
||||
extern uint32_t mem_read_smraml(uint32_t addr, void *priv);
|
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extern void mem_write_smram(uint32_t addr, uint8_t val, void *priv);
|
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extern void mem_write_smramw(uint32_t addr, uint16_t val, void *priv);
|
||||
extern void mem_write_smraml(uint32_t addr, uint32_t val, void *priv);
|
||||
|
||||
extern uint8_t mem_read_bios(uint32_t addr, void *priv);
|
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extern uint16_t mem_read_biosw(uint32_t addr, void *priv);
|
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extern uint32_t mem_read_biosl(uint32_t addr, void *priv);
|
||||
extern uint8_t mem_read_ram_2gb(uint32_t addr, void *priv);
|
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extern uint16_t mem_read_ram_2gbw(uint32_t addr, void *priv);
|
||||
extern uint32_t mem_read_ram_2gbl(uint32_t addr, void *priv);
|
||||
extern void mem_write_ram_2gb(uint32_t addr, uint8_t val, void *priv);
|
||||
extern void mem_write_ram_2gbw(uint32_t addr, uint16_t val, void *priv);
|
||||
extern void mem_write_ram_2gbl(uint32_t addr, uint32_t val, void *priv);
|
||||
|
||||
extern void mem_write_null(uint32_t addr, uint8_t val, void *p);
|
||||
extern void mem_write_nullw(uint32_t addr, uint16_t val, void *p);
|
||||
@@ -362,11 +350,8 @@ extern void mmu_invalidate(uint32_t addr);
|
||||
extern void mem_a20_init(void);
|
||||
extern void mem_a20_recalc(void);
|
||||
|
||||
extern void mem_add_upper_bios(void);
|
||||
extern void mem_add_bios(void);
|
||||
|
||||
extern void mem_init(void);
|
||||
|
||||
extern void mem_close(void);
|
||||
extern void mem_reset(void);
|
||||
extern void mem_remap_top(int kb);
|
||||
|
||||
|
||||
@@ -85,7 +85,7 @@ static const mo_drive_type_t mo_drive_types[KNOWN_MO_DRIVE_TYPES] = {
|
||||
|
||||
enum {
|
||||
MO_BUS_DISABLED = 0,
|
||||
MO_BUS_ATAPI = 4,
|
||||
MO_BUS_ATAPI = 5,
|
||||
MO_BUS_SCSI,
|
||||
MO_BUS_USB
|
||||
};
|
||||
|
||||
@@ -112,11 +112,6 @@ extern void trc_init(void);
|
||||
extern uint8_t trc_read(uint16_t port, void *priv);
|
||||
extern void trc_write(uint16_t port, uint8_t val, void *priv);
|
||||
|
||||
extern void pci_elcr_set_enabled(int enabled);
|
||||
extern void pci_elcr_io_disable(void);
|
||||
extern void elcr_write(uint16_t port, uint8_t val, void *priv);
|
||||
extern uint8_t elcr_read(uint16_t port, void *priv);
|
||||
|
||||
|
||||
#ifdef EMU_DEVICE_H
|
||||
extern const device_t dec21150_device;
|
||||
|
||||
@@ -1,29 +1,57 @@
|
||||
/*
|
||||
* 86Box A hypervisor and IBM PC system emulator that specializes in
|
||||
* running old operating systems and software designed for IBM
|
||||
* PC systems and compatibles from 1981 through fairly recent
|
||||
* system designs based on the PCI bus.
|
||||
*
|
||||
* This file is part of the 86Box distribution.
|
||||
*
|
||||
* Header of the implementation of the Intel PIC chip emulation,
|
||||
* partially ported from reenigne's XTCE.
|
||||
*
|
||||
* Authors: Andrew Jenner, <https://www.reenigne.org>
|
||||
* Miran Grca, <mgrca8@gmail.com>
|
||||
*
|
||||
* Copyright 2015-2020 Andrew Jenner.
|
||||
* Copyright 2016-2020 Miran Grca.
|
||||
*/
|
||||
#ifndef EMU_PIC_H
|
||||
# define EMU_PIC_H
|
||||
|
||||
|
||||
typedef struct PIC {
|
||||
uint8_t icw1, icw3, icw4, mask, ins, pend, mask2, vector, ocw2, ocw3;
|
||||
int icw, read;
|
||||
} PIC;
|
||||
typedef struct pic {
|
||||
uint8_t icw1, icw2, icw3, icw4,
|
||||
imr, isr, irr, ocw2,
|
||||
ocw3, int_pending, is_master, elcr,
|
||||
state, ack_bytes, priority, special_mask_mode,
|
||||
auto_eoi_rotate, interrupt, lines, data_bus;
|
||||
struct pic *slaves[8];
|
||||
} pic_t;
|
||||
|
||||
|
||||
extern PIC pic, pic2;
|
||||
extern int pic_intpending, pic_pending;
|
||||
extern pic_t pic, pic2;
|
||||
|
||||
|
||||
extern int pic_elcr_get_enabled(void);
|
||||
extern void pic_elcr_set_enabled(int enabled);
|
||||
extern void pic_elcr_io_handler(int set);
|
||||
extern void pic_elcr_write(uint16_t port, uint8_t val, void *priv);
|
||||
extern uint8_t pic_elcr_read(uint16_t port, void *priv);
|
||||
|
||||
extern void pic_set_shadow(int sh);
|
||||
extern void pic_init(void);
|
||||
extern void pic_init_pcjr(void);
|
||||
extern void pic2_init(void);
|
||||
extern void pic_reset(void);
|
||||
|
||||
extern int picint_is_level(int irq);
|
||||
extern void picint_common(uint16_t num, int level, int set);
|
||||
extern void picint(uint16_t num);
|
||||
extern void picintlevel(uint16_t num);
|
||||
extern void picintc(uint16_t num);
|
||||
extern int picinterrupt(void);
|
||||
extern void picclear(int num);
|
||||
extern void dumppic(void);
|
||||
|
||||
extern uint8_t pic_irq_ack(void);
|
||||
|
||||
|
||||
#endif /*EMU_PIC_H*/
|
||||
|
||||
@@ -54,6 +54,10 @@ extern int rom_load_linear(wchar_t *fn, uint32_t addr, int sz,
|
||||
extern int rom_load_interleaved(wchar_t *fnl, wchar_t *fnh, uint32_t addr,
|
||||
int sz, int off, uint8_t *ptr);
|
||||
|
||||
extern uint8_t bios_read(uint32_t addr, void *priv);
|
||||
extern uint16_t bios_readw(uint32_t addr, void *priv);
|
||||
extern uint32_t bios_readl(uint32_t addr, void *priv);
|
||||
|
||||
extern int bios_load(wchar_t *fn1, wchar_t *fn2, uint32_t addr, int sz,
|
||||
int off, int flags);
|
||||
extern int bios_load_linear_combined(wchar_t *fn1, wchar_t *fn2,
|
||||
|
||||
57
src/include/86box/smram.h
Normal file
57
src/include/86box/smram.h
Normal file
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* 86Box A hypervisor and IBM PC system emulator that specializes in
|
||||
* running old operating systems and software designed for IBM
|
||||
* PC systems and compatibles from 1981 through fairly recent
|
||||
* system designs based on the PCI bus.
|
||||
*
|
||||
* This file is part of the 86Box distribution.
|
||||
*
|
||||
* Definitions for the SMRAM interface.
|
||||
*
|
||||
*
|
||||
*
|
||||
* Authors: Miran Grca, <mgrca8@gmail.com>
|
||||
*
|
||||
* Copyright 2016-2020 Miran Grca.
|
||||
*/
|
||||
#ifndef EMU_SMRAM_H
|
||||
# define EMU_SMRAM_H
|
||||
|
||||
|
||||
typedef struct _smram_
|
||||
{
|
||||
struct _smram_ *prev, *next;
|
||||
|
||||
mem_mapping_t mapping;
|
||||
|
||||
uint32_t host_base, ram_base,
|
||||
size,
|
||||
old_host_base, old_size;
|
||||
} smram_t;
|
||||
|
||||
|
||||
/* Make a backup copy of host_base and size of all the SMRAM structs, needed so that if
|
||||
the SMRAM mappings change while in SMM, they will be recalculated on return. */
|
||||
extern void smram_backup_all(void);
|
||||
/* Recalculate any mappings, including the backup if returning from SMM. */
|
||||
extern void smram_recalc_all(int ret);
|
||||
/* Delete a SMRAM mapping. */
|
||||
extern void smram_del(smram_t *smr);
|
||||
/* Add a SMRAM mapping. */
|
||||
extern smram_t *smram_add(void);
|
||||
/* Set memory state in the specified model (normal or SMM) according to the specified flags. */
|
||||
extern void smram_map(int smm, uint32_t addr, uint32_t size, int is_smram);
|
||||
/* Disable a specific SMRAM mapping. */
|
||||
extern void smram_disable(smram_t *smr);
|
||||
/* Disable all SMRAM mappings. */
|
||||
extern void smram_disable_all(void);
|
||||
/* Enable SMRAM mappings according to flags for both normal and SMM modes. */
|
||||
extern void smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size,
|
||||
int flags_normal, int flags_smm);
|
||||
/* Checks if a SMRAM mapping is enabled or not. */
|
||||
extern int smram_enabled(smram_t *smr);
|
||||
/* Changes the SMRAM state. */
|
||||
extern void smram_state_change(smram_t *smr, int smm, int flags);
|
||||
|
||||
|
||||
#endif /*EMU_SMRAM_H*/
|
||||
@@ -80,17 +80,9 @@ extern void timer_add(pc_timer_t *timer, void (*callback)(void *p), void *p, int
|
||||
extern uint64_t TIMER_USEC;
|
||||
|
||||
/*True if timer a expires before timer b*/
|
||||
#if 0
|
||||
#define TIMER_LESS_THAN(a, b) ((int32_t)((a)->ts_integer - (b)->ts_integer) <= 0)
|
||||
#else
|
||||
#define TIMER_LESS_THAN(a, b) ((int64_t)((a)->ts.ts64 - (b)->ts.ts64) <= 0)
|
||||
#endif
|
||||
/*True if timer a expires before 32 bit integer timestamp b*/
|
||||
#if 0
|
||||
#define TIMER_LESS_THAN_VAL(a, b) ((int32_t)((a)->ts_integer - (b)) <= 0)
|
||||
#else
|
||||
#define TIMER_LESS_THAN_VAL(a, b) ((int32_t)((a)->ts.ts32.integer - (b)) <= 0)
|
||||
#endif
|
||||
/*True if 32 bit integer timestamp a expires before 32 bit integer timestamp b*/
|
||||
#define TIMER_VAL_LESS_THAN_VAL(a, b) ((int32_t)((a) - (b)) <= 0)
|
||||
|
||||
@@ -100,17 +92,7 @@ extern uint64_t TIMER_USEC;
|
||||
static __inline void
|
||||
timer_advance_u64(pc_timer_t *timer, uint64_t delay)
|
||||
{
|
||||
#if 0
|
||||
uint32_t int_delay = delay >> 32;
|
||||
uint32_t frac_delay = delay & 0xffffffff;
|
||||
|
||||
if ((frac_delay + timer->ts_frac) < frac_delay)
|
||||
timer->ts_integer++;
|
||||
timer->ts_frac += frac_delay;
|
||||
timer->ts_integer += int_delay;
|
||||
#else
|
||||
timer->ts.ts64 += delay;
|
||||
#endif
|
||||
|
||||
timer_enable(timer);
|
||||
}
|
||||
@@ -121,17 +103,9 @@ timer_advance_u64(pc_timer_t *timer, uint64_t delay)
|
||||
static __inline void
|
||||
timer_set_delay_u64(pc_timer_t *timer, uint64_t delay)
|
||||
{
|
||||
#if 0
|
||||
uint32_t int_delay = delay >> 32;
|
||||
uint32_t frac_delay = delay & 0xffffffff;
|
||||
|
||||
timer->ts_frac = frac_delay;
|
||||
timer->ts_integer = int_delay + (uint32_t)tsc;
|
||||
#else
|
||||
timer->ts.ts64 = 0ULL;
|
||||
timer->ts.ts32.integer = tsc;
|
||||
timer->ts.ts64 += delay;
|
||||
#endif
|
||||
|
||||
timer_enable(timer);
|
||||
}
|
||||
@@ -149,11 +123,7 @@ timer_is_enabled(pc_timer_t *timer)
|
||||
static __inline uint32_t
|
||||
timer_get_ts_int(pc_timer_t *timer)
|
||||
{
|
||||
#if 0
|
||||
return timer->ts_integer;
|
||||
#else
|
||||
return timer->ts.ts32.integer;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
@@ -165,11 +135,7 @@ timer_get_remaining_us(pc_timer_t *timer)
|
||||
int64_t remaining;
|
||||
|
||||
if (timer->flags & TIMER_ENABLED) {
|
||||
#if 0
|
||||
remaining = (((uint64_t)timer->ts_integer << 32) | timer->ts_frac) - (tsc << 32);
|
||||
#else
|
||||
remaining = (int64_t) (timer->ts.ts64 - (uint64_t)(tsc << 32));
|
||||
#endif
|
||||
|
||||
if (remaining < 0)
|
||||
return 0;
|
||||
@@ -188,11 +154,7 @@ timer_get_remaining_u64(pc_timer_t *timer)
|
||||
int64_t remaining;
|
||||
|
||||
if (timer->flags & TIMER_ENABLED) {
|
||||
#if 0
|
||||
remaining = (((uint64_t)timer->ts_integer << 32) | timer->ts_frac) - (tsc << 32);
|
||||
#else
|
||||
remaining = (int64_t) (timer->ts.ts64 - (uint64_t)(tsc << 32));
|
||||
#endif
|
||||
|
||||
if (remaining < 0)
|
||||
return 0;
|
||||
|
||||
@@ -17,10 +17,11 @@
|
||||
#define EMU_NAME "86Box"
|
||||
#define EMU_NAME_W L"86Box"
|
||||
|
||||
#define EMU_VERSION "2.10"
|
||||
#define EMU_VERSION_W L"2.10"
|
||||
#define EMU_VERSION_MAJ 2
|
||||
#define EMU_VERSION_MIN 10
|
||||
#define EMU_VERSION "3.0"
|
||||
#define EMU_VERSION_W L"3.0"
|
||||
#define EMU_VERSION_EX "3.00"
|
||||
#define EMU_VERSION_MAJ 3
|
||||
#define EMU_VERSION_MIN 0
|
||||
|
||||
#define COPYRIGHT_YEAR "2020"
|
||||
|
||||
|
||||
@@ -314,6 +314,7 @@ extern const device_t s3_phoenix_trio64_onboard_pci_device;
|
||||
extern const device_t s3_phoenix_trio64_pci_device;
|
||||
extern const device_t s3_phoenix_trio64vplus_vlb_device;
|
||||
extern const device_t s3_phoenix_trio64vplus_pci_device;
|
||||
extern const device_t s3_phoenix_trio64vplus_onboard_pci_device;
|
||||
extern const device_t s3_phoenix_vision864_pci_device;
|
||||
extern const device_t s3_phoenix_vision864_vlb_device;
|
||||
extern const device_t s3_diamond_stealth64_pci_device;
|
||||
|
||||
@@ -32,7 +32,7 @@
|
||||
|
||||
enum {
|
||||
ZIP_BUS_DISABLED = 0,
|
||||
ZIP_BUS_ATAPI = 4,
|
||||
ZIP_BUS_ATAPI = 5,
|
||||
ZIP_BUS_SCSI,
|
||||
ZIP_BUS_USB
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user