Major commit, cleaning a lot of old stuff.
IBM.H is gone, video stuff re-organized. Keyboard stuff reorganized. Machines that have their own video, mouse and/or keyboard now have all this in their machine file. Fixed and other cleanups here and there.
This commit is contained in:
waltje
516
src/cpu/cpu.h
516
src/cpu/cpu.h
@@ -8,7 +8,7 @@
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*
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* CPU type handler.
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*
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* Version: @(#)cpu.h 1.0.2 2017/10/14
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* Version: @(#)cpu.h 1.0.3 2017/11/04
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* leilei,
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@@ -21,132 +21,254 @@
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#ifndef EMU_CPU_H
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# define EMU_CPU_H
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extern int cpu, cpu_manufacturer;
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/*808x class CPUs*/
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#define CPU_8088 0
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#define CPU_8086 1
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/*286 class CPUs*/
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#define CPU_286 2
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/*386 class CPUs*/
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#define CPU_386SX 3
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#define CPU_386DX 4
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#define CPU_8088 0 /* 808x class CPUs */
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#define CPU_8086 1
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#define CPU_286 2 /* 286 class CPUs */
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#define CPU_386SX 3 /* 386 class CPUs */
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#define CPU_386DX 4
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#define CPU_RAPIDCAD 5
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#define CPU_486SLC 6
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#define CPU_486DLC 7
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/*486 class CPUs*/
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#define CPU_i486SX 8
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#define CPU_Am486SX 9
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#define CPU_Cx486S 10
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#define CPU_i486DX 11
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#define CPU_Am486DX 12
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#define CPU_Cx486DX 13
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#define CPU_iDX4 14
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#define CPU_Cx5x86 15
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/*586 class CPUs*/
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#define CPU_WINCHIP 16
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#define CPU_PENTIUM 17
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#define CPU_PENTIUMMMX 18
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#define CPU_486SLC 6
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#define CPU_486DLC 7
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#define CPU_i486SX 8 /* 486 class CPUs */
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#define CPU_Am486SX 9
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#define CPU_Cx486S 10
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#define CPU_i486DX 11
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#define CPU_Am486DX 12
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#define CPU_Cx486DX 13
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#define CPU_iDX4 14
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#define CPU_Cx5x86 15
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#define CPU_WINCHIP 16 /* 586 class CPUs */
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#define CPU_PENTIUM 17
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#define CPU_PENTIUMMMX 18
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#define CPU_Cx6x86 19
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#define CPU_Cx6x86MX 20
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#define CPU_Cx6x86L 21
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#define CPU_CxGX1 22
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#define CPU_K5 23
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#define CPU_5K86 24
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#define CPU_K6 25
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#define CPU_K5 23
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#define CPU_5K86 24
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#define CPU_K6 25
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#define CPU_PENTIUMPRO 26 /* 686 class CPUs */
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#if 0
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# define CPU_PENTIUM2 27
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# define CPU_PENTIUM2D 28
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#else
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# define CPU_PENTIUM2D 27
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#endif
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/*686 class CPUs*/
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#define CPU_PENTIUMPRO 26
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/*
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#define CPU_PENTIUM2 27
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#define CPU_PENTIUM2D 28 */
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#define CPU_PENTIUM2D 27
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#define MANU_INTEL 0
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#define MANU_AMD 1
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#define MANU_CYRIX 2
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#define MANU_IDT 3
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#define MANU_INTEL 0
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#define MANU_AMD 1
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#define MANU_CYRIX 2
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#define MANU_IDT 3
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extern int timing_rr;
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extern int timing_mr, timing_mrl;
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extern int timing_rm, timing_rml;
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extern int timing_mm, timing_mml;
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extern int timing_bt, timing_bnt;
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extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm, timing_int_pm_outer;
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extern int timing_iret_rm, timing_iret_v86, timing_iret_pm, timing_iret_pm_outer;
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extern int timing_call_rm, timing_call_pm, timing_call_pm_gate, timing_call_pm_gate_inner;
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extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
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extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
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extern int timing_misaligned;
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#define CPU_SUPPORTS_DYNAREC 1
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#define CPU_REQUIRES_DYNAREC 2
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typedef struct
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{
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char name[32];
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int cpu_type;
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int speed;
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int rspeed;
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int multi;
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int pci_speed;
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uint32_t edx_reset;
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uint32_t cpuid_model;
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uint16_t cyrix_id;
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int cpu_flags;
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int mem_read_cycles, mem_write_cycles;
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int cache_read_cycles, cache_write_cycles;
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typedef struct {
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char name[32];
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int cpu_type;
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int speed;
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int rspeed;
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int multi;
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int pci_speed;
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uint32_t edx_reset;
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uint32_t cpuid_model;
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uint16_t cyrix_id;
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int cpu_flags;
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int mem_read_cycles, mem_write_cycles;
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int cache_read_cycles, cache_write_cycles;
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} CPU;
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extern CPU cpus_8088[];
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extern CPU cpus_8086[];
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extern CPU cpus_286[];
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extern CPU cpus_i386SX[];
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extern CPU cpus_i386DX[];
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extern CPU cpus_Am386SX[];
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extern CPU cpus_Am386DX[];
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extern CPU cpus_486SLC[];
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extern CPU cpus_486DLC[];
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extern CPU cpus_i486[];
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extern CPU cpus_Am486[];
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extern CPU cpus_Cx486[];
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extern CPU cpus_WinChip[];
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extern CPU cpus_Pentium5V[];
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extern CPU cpus_Pentium5V50[];
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extern CPU cpus_PentiumS5[];
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extern CPU cpus_K5[];
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extern CPU cpus_K56[];
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extern CPU cpus_Pentium[];
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extern CPU cpus_6x86[];
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extern CPU cpus_PentiumPro[];
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extern CPU cpus_Pentium2[];
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extern CPU cpus_Pentium2D[];
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extern CPU cpus_8088[];
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extern CPU cpus_8086[];
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extern CPU cpus_286[];
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extern CPU cpus_i386SX[];
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extern CPU cpus_i386DX[];
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extern CPU cpus_Am386SX[];
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extern CPU cpus_Am386DX[];
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extern CPU cpus_486SLC[];
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extern CPU cpus_486DLC[];
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extern CPU cpus_i486[];
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extern CPU cpus_Am486[];
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extern CPU cpus_Cx486[];
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extern CPU cpus_WinChip[];
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extern CPU cpus_Pentium5V[];
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extern CPU cpus_Pentium5V50[];
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extern CPU cpus_PentiumS5[];
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extern CPU cpus_K5[];
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extern CPU cpus_K56[];
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extern CPU cpus_Pentium[];
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extern CPU cpus_6x86[];
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extern CPU cpus_PentiumPro[];
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extern CPU cpus_Pentium2[];
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extern CPU cpus_Pentium2D[];
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extern CPU cpus_pcjr[];
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extern CPU cpus_europc[];
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extern CPU cpus_pc1512[];
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extern CPU cpus_ibmat[];
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extern CPU cpus_ibmxt286[];
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extern CPU cpus_ps1_m2011[];
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extern CPU cpus_ps2_m30_286[];
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extern CPU cpus_acer[];
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extern int cpu_iscyrix;
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extern int cpu_16bitbus;
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extern int cpu_busspeed;
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extern int cpu_multi;
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/*Cyrix 5x86/6x86 only has data misalignment penalties when crossing 8-byte boundaries*/
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extern int cpu_cyrix_alignment;
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#define C_FLAG 0x0001
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#define P_FLAG 0x0004
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#define A_FLAG 0x0010
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#define Z_FLAG 0x0040
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#define N_FLAG 0x0080
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#define T_FLAG 0x0100
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#define I_FLAG 0x0200
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#define D_FLAG 0x0400
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#define V_FLAG 0x0800
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#define NT_FLAG 0x4000
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extern int cpu_hasrdtsc;
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extern int cpu_hasMSR;
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extern int cpu_hasMMX;
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extern int cpu_hasCR4;
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extern int cpu_hasVME;
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#define VM_FLAG 0x0002 /* in EFLAGS */
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#define VIF_FLAG 0x0008 /* in EFLAGS */
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#define VIP_FLAG 0x0010 /* in EFLAGS */
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#define WP_FLAG 0x10000 /* in CR0 */
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#define CR4_VME (1 << 0)
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#define CR4_PVI (1 << 1)
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#define CR4_PSE (1 << 4)
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#define CPL ((_cs.access>>5)&3)
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#define IOPL ((flags>>12)&3)
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#define IOPLp ((!(msw&1)) || (CPL<=IOPL))
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typedef union {
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uint32_t l;
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uint16_t w;
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struct {
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uint8_t l,
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h;
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} b;
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} x86reg;
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typedef struct {
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uint32_t base;
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uint32_t limit;
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uint8_t access;
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uint16_t seg;
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uint32_t limit_low,
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limit_high;
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int checked; /*Non-zero if selector is known to be valid*/
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} x86seg;
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typedef union MMX_REG {
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uint64_t q;
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int64_t sq;
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uint32_t l[2];
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int32_t sl[2];
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uint16_t w[4];
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int16_t sw[4];
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uint8_t b[8];
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int8_t sb[8];
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} MMX_REG;
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typedef struct {
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uint32_t tr1, tr12;
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uint32_t cesr;
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uint32_t fcr;
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uint64_t fcr2, fcr3;
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} msr_t;
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typedef union {
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uint32_t l;
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uint16_t w;
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} cr0_t;
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struct _cpustate_ {
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x86reg regs[8];
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uint8_t tag[8];
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x86seg *ea_seg;
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uint32_t eaaddr;
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int flags_op;
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uint32_t flags_res;
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uint32_t flags_op1,
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flags_op2;
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uint32_t pc;
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uint32_t oldpc;
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uint32_t op32;
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int TOP;
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union {
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struct {
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int8_t rm,
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mod,
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reg;
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} rm_mod_reg;
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int32_t rm_mod_reg_data;
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} rm_data;
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int8_t ssegs;
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int8_t ismmx;
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int8_t abrt;
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int _cycles;
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int cpu_recomp_ins;
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uint16_t npxs,
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npxc;
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double ST[8];
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uint16_t MM_w4[8];
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MMX_REG MM[8];
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uint16_t old_npxc,
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new_npxc;
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uint32_t last_ea;
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} cpu_state;
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#define CPU_STATUS_USE32 (1 << 0)
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#define CPU_STATUS_STACK32 (1 << 1)
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#define CPU_STATUS_FLATDS (1 << 2)
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#define CPU_STATUS_FLATSS (1 << 3)
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#ifdef __MSC__
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# define COMPILE_TIME_ASSERT(expr) /*nada*/
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#else
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# define COMPILE_TIME_ASSERT(expr) typedef char COMP_TIME_ASSERT[(expr) ? 1 : 0];
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#endif
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COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128)
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#define cpu_state_offset(MEMBER) ((uint8_t)((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state - 128))
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#define EAX cpu_state.regs[0].l
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#define AX cpu_state.regs[0].w
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#define AL cpu_state.regs[0].b.l
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#define AH cpu_state.regs[0].b.h
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#define ECX cpu_state.regs[1].l
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#define CX cpu_state.regs[1].w
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#define CL cpu_state.regs[1].b.l
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#define CH cpu_state.regs[1].b.h
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#define EDX cpu_state.regs[2].l
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#define DX cpu_state.regs[2].w
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#define DL cpu_state.regs[2].b.l
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#define DH cpu_state.regs[2].b.h
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#define EBX cpu_state.regs[3].l
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#define BX cpu_state.regs[3].w
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#define BL cpu_state.regs[3].b.l
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#define BH cpu_state.regs[3].b.h
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#define ESP cpu_state.regs[4].l
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#define EBP cpu_state.regs[5].l
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#define ESI cpu_state.regs[6].l
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#define EDI cpu_state.regs[7].l
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#define SP cpu_state.regs[4].w
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#define BP cpu_state.regs[5].w
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#define SI cpu_state.regs[6].w
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#define DI cpu_state.regs[7].w
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#define cycles cpu_state._cycles
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#define cpu_rm cpu_state.rm_data.rm_mod_reg.rm
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#define cpu_mod cpu_state.rm_data.rm_mod_reg.mod
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#define cpu_reg cpu_state.rm_data.rm_mod_reg.reg
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#define CR4_TSD (1 << 2)
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#define CR4_DE (1 << 3)
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@@ -154,49 +276,161 @@ extern int cpu_hasVME;
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#define CR4_PCE (1 << 8)
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#define CR4_OSFXSR (1 << 9)
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extern uint64_t cpu_CR4_mask;
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#define CPU_SUPPORTS_DYNAREC 1
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#define CPU_REQUIRES_DYNAREC 2
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/* Global variables. */
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extern int cpu_iscyrix;
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extern int cpu_16bitbus;
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extern int cpu_busspeed;
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extern int cpu_multi;
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extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
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penalties when crossing 8-byte boundaries*/
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extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
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extern int cpu_prefetch_cycles, cpu_prefetch_width;
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extern int cpu_waitstates;
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extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
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extern int cpu_pci_speed;
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extern int is8086, is286, is386, is486;
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extern int is_rapidcad, is_pentium;
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extern int hasfpu;
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extern int cpu_hasrdtsc;
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extern int cpu_hasMSR;
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extern int cpu_hasMMX;
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extern int cpu_hasCR4;
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extern int cpu_hasVME;
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extern uint64_t tsc;
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extern uint32_t cpu_cur_status;
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extern uint64_t cpu_CR4_mask;
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extern uint64_t tsc;
|
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extern msr_t msr;
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extern int cpuspeed;
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extern int cycles_lost;
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extern uint8_t opcode;
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extern int insc;
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extern int fpucount;
|
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extern float mips,flops;
|
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extern int clockrate;
|
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extern int cgate16;
|
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extern int cpl_override;
|
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extern int CPUID;
|
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extern int xt_cpu_multi;
|
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extern int isa_cycles;
|
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extern uint16_t flags,eflags;
|
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extern uint32_t oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw;
|
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extern int ins,output;
|
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extern int cycdiff;
|
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extern uint32_t pccache;
|
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extern uint8_t *pccache2;
|
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|
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void cyrix_write(uint16_t addr, uint8_t val, void *priv);
|
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uint8_t cyrix_read(uint16_t addr, void *priv);
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extern float isa_timing, bus_timing;
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extern uint64_t pmc[2];
|
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extern uint16_t temp_seg_data[4];
|
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extern uint16_t cs_msr;
|
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extern uint32_t esp_msr;
|
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extern uint32_t eip_msr;
|
||||
|
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extern int is8086;
|
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/* For the AMD K6. */
|
||||
extern uint64_t star;
|
||||
|
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void cpu_CPUID();
|
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#define FPU_CW_Reserved_Bits (0xe0c0)
|
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|
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void cpu_RDMSR();
|
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void cpu_WRMSR();
|
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extern cr0_t CR0;
|
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#define cr0 CR0.l
|
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#define msw CR0.w
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extern uint32_t cr2, cr3, cr4;
|
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extern uint32_t dr[8];
|
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|
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extern int cpu_use_dynarec;
|
||||
|
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extern int xt_cpu_multi;
|
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/*Segments -
|
||||
_cs,_ds,_es,_ss are the segment structures
|
||||
CS,DS,ES,SS is the 16-bit data
|
||||
cs,ds,es,ss are defines to the bases*/
|
||||
extern x86seg gdt,ldt,idt,tr;
|
||||
extern x86seg _cs,_ds,_es,_ss,_fs,_gs;
|
||||
extern x86seg _oldds;
|
||||
#define CS _cs.seg
|
||||
#define DS _ds.seg
|
||||
#define ES _es.seg
|
||||
#define SS _ss.seg
|
||||
#define FS _fs.seg
|
||||
#define GS _gs.seg
|
||||
#define cs _cs.base
|
||||
#define ds _ds.base
|
||||
#define es _es.base
|
||||
#define ss _ss.base
|
||||
#define seg_fs _fs.base
|
||||
#define gs _gs.base
|
||||
|
||||
|
||||
#define ISA_CYCLES_SHIFT 6
|
||||
extern int isa_cycles;
|
||||
#define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT)
|
||||
#define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT)
|
||||
|
||||
void cpu_update_waitstates();
|
||||
void cpu_set();
|
||||
extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
|
||||
extern int cpu_prefetch_cycles, cpu_prefetch_width;
|
||||
extern int cpu_waitstates;
|
||||
extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
|
||||
extern int cpu_pci_speed;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t tr1, tr12;
|
||||
uint32_t cesr;
|
||||
uint32_t fcr;
|
||||
uint64_t fcr2, fcr3;
|
||||
} msr_t;
|
||||
extern int timing_rr;
|
||||
extern int timing_mr, timing_mrl;
|
||||
extern int timing_rm, timing_rml;
|
||||
extern int timing_mm, timing_mml;
|
||||
extern int timing_bt, timing_bnt;
|
||||
extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm;
|
||||
extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm;
|
||||
extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm;
|
||||
extern int timing_call_pm_gate, timing_call_pm_gate_inner;
|
||||
extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
|
||||
extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
|
||||
extern int timing_misaligned;
|
||||
|
||||
extern msr_t msr;
|
||||
|
||||
extern CPU cpus_pcjr[]; // FIXME: should be in machine file!
|
||||
extern CPU cpus_europc[]; // FIXME: should be in machine file!
|
||||
extern CPU cpus_pc1512[]; // FIXME: should be in machine file!
|
||||
extern CPU cpus_ibmat[]; // FIXME: should be in machine file!
|
||||
extern CPU cpus_ibmxt286[]; // FIXME: should be in machine file!
|
||||
extern CPU cpus_ps1_m2011[]; // FIXME: should be in machine file!
|
||||
extern CPU cpus_ps2_m30_286[]; // FIXME: should be in machine file!
|
||||
extern CPU cpus_acer[]; // FIXME: should be in machine file!
|
||||
|
||||
|
||||
/* Functions. */
|
||||
extern void cyrix_write(uint16_t addr, uint8_t val, void *priv);
|
||||
extern uint8_t cyrix_read(uint16_t addr, void *priv);
|
||||
extern void loadseg(uint16_t seg, x86seg *s);
|
||||
extern void loadcs(uint16_t seg);
|
||||
|
||||
extern void cpu_update_waitstates(void);
|
||||
extern void cpu_set(void);
|
||||
|
||||
extern void cpu_CPUID(void);
|
||||
extern void cpu_RDMSR(void);
|
||||
extern void cpu_WRMSR(void);
|
||||
|
||||
extern int checkio(int port);
|
||||
extern void codegen_block_end(void);
|
||||
extern void codegen_reset(void);
|
||||
extern void cpu_set_edx(void);
|
||||
extern int divl(uint32_t val);
|
||||
extern void dumpregs(int __force);
|
||||
extern void execx86(int cycs);
|
||||
extern void exec386(int cycs);
|
||||
extern void exec386_dynarec(int cycs);
|
||||
extern int idivl(int32_t val);
|
||||
extern void loadcscall(uint16_t seg);
|
||||
extern void loadcsjmp(uint16_t seg, uint32_t oxpc);
|
||||
extern void pmodeint(int num, int soft);
|
||||
extern void pmoderetf(int is32, uint16_t off);
|
||||
extern void pmodeiret(int is32);
|
||||
extern void resetmcr(void);
|
||||
extern void resetx86(void);
|
||||
extern void refreshread(void);
|
||||
extern void resetreadlookup(void);
|
||||
extern void softresetx86(void);
|
||||
extern void x86_int_sw(int num);
|
||||
extern int x86_int_sw_rm(int num);
|
||||
extern void x86gpf(char *s, uint16_t error);
|
||||
extern void x86np(char *s, uint16_t error);
|
||||
extern void x86ss(char *s, uint16_t error);
|
||||
extern void x86ts(char *s, uint16_t error);
|
||||
extern void x87_dumpregs(void);
|
||||
extern void x87_reset(void);
|
||||
|
||||
|
||||
#endif /*EMU_CPU_H*/
|
||||
|
||||
Reference in New Issue
Block a user