Major commit, cleaning a lot of old stuff.
IBM.H is gone, video stuff re-organized. Keyboard stuff reorganized. Machines that have their own video, mouse and/or keyboard now have all this in their machine file. Fixed and other cleanups here and there.
This commit is contained in:
waltje
185
src/machine/m_at_sis_85c496.c
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185
src/machine/m_at_sis_85c496.c
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/* Copyright holders: Sarah Walker
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see COPYING for more details
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <wchar.h>
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#include "../86box.h"
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#include "../cpu/cpu.h"
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#include "../io.h"
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#include "../pci.h"
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#include "../mem.h"
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#include "../memregs.h"
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#include "../sio.h"
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#include "machine.h"
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typedef struct sis_85c496_t
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{
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uint8_t pci_conf[256];
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} sis_85c496_t;
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sis_85c496_t sis496;
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static void sis_85c496_recalcmapping(void)
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{
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int c;
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for (c = 0; c < 8; c++)
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{
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uint32_t base = 0xc0000 + (c << 15);
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if (sis496.pci_conf[0x44] & (1 << c))
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{
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switch (sis496.pci_conf[0x45] & 3)
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{
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case 0:
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mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 1:
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mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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break;
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case 2:
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mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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case 3:
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mem_set_mem_state(base, 0x8000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
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break;
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}
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}
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else
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mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
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}
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flushmmucache();
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shadowbios = (sis496.pci_conf[0x44] & 0xf0);
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}
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static void sis_85c496_write(int func, int addr, uint8_t val, void *p)
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{
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switch (addr)
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{
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case 0x44: /*Shadow configure*/
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if ((sis496.pci_conf[0x44] & val) ^ 0xf0)
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{
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sis496.pci_conf[0x44] = val;
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sis_85c496_recalcmapping();
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}
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break;
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case 0x45: /*Shadow configure*/
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if ((sis496.pci_conf[0x45] & val) ^ 0x01)
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{
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sis496.pci_conf[0x45] = val;
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sis_85c496_recalcmapping();
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}
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break;
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case 0xc0:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTA, val & 0xf);
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else
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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break;
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case 0xc1:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTB, val & 0xf);
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else
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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break;
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case 0xc2:
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTC, val & 0xf);
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else
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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break;
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case 0xc3:// pclog("IRQ routing %02x %02x\n", addr, val);
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTD, val & 0xf);
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else
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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break;
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}
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if ((addr >= 4 && addr < 8) || addr >= 0x40)
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sis496.pci_conf[addr] = val;
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}
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static uint8_t sis_85c496_read(int func, int addr, void *p)
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{
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return sis496.pci_conf[addr];
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}
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static void sis_85c496_reset(void)
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{
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memset(&sis496, 0, sizeof(sis_85c496_t));
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sis496.pci_conf[0x00] = 0x39; /*SiS*/
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sis496.pci_conf[0x01] = 0x10;
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sis496.pci_conf[0x02] = 0x96; /*496/497*/
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sis496.pci_conf[0x03] = 0x04;
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sis496.pci_conf[0x04] = 7;
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sis496.pci_conf[0x05] = 0;
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sis496.pci_conf[0x06] = 0x80;
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sis496.pci_conf[0x07] = 0x02;
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sis496.pci_conf[0x08] = 2; /*Device revision*/
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sis496.pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
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sis496.pci_conf[0x0a] = 0x00;
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sis496.pci_conf[0x0b] = 0x06;
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sis496.pci_conf[0x0e] = 0x00; /*Single function device*/
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}
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static void sis_85c496_pci_reset(void)
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{
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uint8_t val = 0;
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val = sis_85c496_read(0, 0x44, NULL); /* Read current value of 0x44. */
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sis_85c496_write(0, 0x44, val & 0xf, NULL); /* Turn off shadow BIOS but keep the lower 4 bits. */
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}
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static void sis_85c496_init(void)
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{
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pci_add_card(5, sis_85c496_read, sis_85c496_write, NULL);
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sis_85c496_reset();
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pci_reset_handler.pci_master_reset = sis_85c496_pci_reset;
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}
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static void
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machine_at_sis_85c496_common_init(machine_t *model)
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{
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machine_at_ide_init(model);
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memregs_init();
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pci_init(PCI_CONFIG_TYPE_1);
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pci_register_slot(0x05, PCI_CARD_SPECIAL, 0, 0, 0, 0);
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pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
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pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
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pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
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pci_register_slot(0x07, PCI_CARD_NORMAL, 4, 1, 2, 3);
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sis_85c496_init();
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}
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void
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machine_at_r418_init(machine_t *model)
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{
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machine_at_sis_85c496_common_init(model);
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fdc37c665_init();
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}
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