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Removed V20 specific instructions (for now) and corrected some warnings.

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This commit is contained in:
TC1995
2018-07-21 16:00:10 +02:00
parent af066aee04
commit 7dffe08136
6 changed files with 99 additions and 383 deletions
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334
src/cpu/808x.c
View File

@@ -18,7 +18,7 @@
* 2 clocks - fetch opcode 1 2 clocks - execute
* 2 clocks - fetch opcode 2 etc
*
* Version: @(#)808x.c 1.0.6 2018/07/19
* Version: @(#)808x.c 1.0.5 2018/04/29
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
@@ -881,70 +881,19 @@ void rep(int fv)
cycles-=2;
goto startrep;
break;
case 0x6C: /*186+ REP INSB*/
if (is_nec)
{
if (c>0)
{
temp2=inb(DX);
writememb(ds+SI, temp2);
if (flags&D_FLAG) SI--;
else SI++;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
}
break;
case 0x6D: /*186+ REP INSW*/
if (is_nec)
{
if (c>0)
{
tempw2=inw(DX);
writememw(ds, SI, tempw2);
if (flags&D_FLAG) SI-=2;
else SI+=2;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
}
case 0x6E: /*REP OUTSB*/
if (c>0)
{
temp2=readmemb(ds+SI);
outb(DX,temp2);
if (flags&D_FLAG) SI--;
else SI++;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
break;
case 0x6E: /*186+ REP OUTSB*/
if (is_nec)
{
if (c>0)
{
temp2=readmemb(ds+SI);
outb(DX,temp2);
if (flags&D_FLAG) SI--;
else SI++;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
}
break;
case 0x6F: /*186+ REP OUTSW*/
if (is_nec)
{
if (c>0)
{
tempw2=readmemw(ds,SI);
outw(DX,tempw2);
if (flags&D_FLAG) SI-=2;
else SI+=2;
c--;
cycles-=5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; if (cpu_state.ssegs) cpu_state.ssegs++; FETCHCLEAR(); }
else firstrepcycle=1;
}
break;
case 0xA4: /*REP MOVSB*/
while (c>0 && !IRQTEST)
{
@@ -1261,16 +1210,13 @@ void execx86(int cycs)
cpu_state.last_ea = SP;
cycles-=14;
break;
case 0x0F: /*0F handler for NEC V20 soon */
if (!is_nec) /*POP CS - 8088/8086 only*/
{
if (cpu_state.ssegs) ss=oldss;
tempw=readmemw(ss,SP);
loadseg(tempw,&_cs);
SP+=2;
cpu_state.last_ea = SP;
cycles-=12;
}
case 0x0F: /*POP CS - 8088/8086 only*/
if (cpu_state.ssegs) ss=oldss;
tempw=readmemw(ss,SP);
loadseg(tempw,&_cs);
SP+=2;
cpu_state.last_ea = SP;
cycles-=12;
break;
case 0x10: /*ADC 8,reg*/
@@ -1695,218 +1641,73 @@ void execx86(int cycs)
break;
case 0x60:
if (is_nec) /*186+ PUSHA*/
{
writememw(ss, ((SP - 2) & 0xFFFF), AX);
writememw(ss, ((SP - 4) & 0xFFFF), CX);
writememw(ss, ((SP - 6) & 0xFFFF), DX);
writememw(ss, ((SP - 8) & 0xFFFF), BX);
writememw(ss, ((SP - 10) & 0xFFFF), SP);
writememw(ss, ((SP - 12) & 0xFFFF), BP);
writememw(ss, ((SP - 14) & 0xFFFF), SI);
writememw(ss, ((SP - 16) & 0xFFFF), DI);
cycles-=18;
break;
}
else /*JO alias*/
{
offset=(int8_t)FETCH();
if (flags&V_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
}
break;
case 0x60: /*JO alias*/
case 0x70: /*JO*/
offset=(int8_t)FETCH();
if (flags&V_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x61:
if (is_nec) /*186+ POPA*/
{
DI = readmemw(ss, ((SP) & 0xFFFF));
SI = readmemw(ss, ((SP + 2) & 0xFFFF));
BP = readmemw(ss, ((SP + 4) & 0xFFFF));
BX = readmemw(ss, ((SP + 8) & 0xFFFF));
DX = readmemw(ss, ((SP + 10) & 0xFFFF));
CX = readmemw(ss, ((SP + 12) & 0xFFFF));
AX = readmemw(ss, ((SP + 14) & 0xFFFF));
SP += 16;
cycles-=24;
break;
}
else /*JNO alias*/
{
offset=(int8_t)FETCH();
if (!(flags&V_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
}
break;
case 0x61: /*JNO alias*/
case 0x71: /*JNO*/
offset=(int8_t)FETCH();
if (!(flags&V_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x62:
if (is_nec) /*186+ BOUND*/
{
int16_t low, high;
low = geteaw();
high = readmemw(easeg,cpu_state.eaaddr);
if (((int16_t)cpu_state.regs[cpu_reg].w < low) || ((int16_t)cpu_state.regs[cpu_reg].w > high))
{
writememw(ss,(SP-2)&0xFFFF,flags|0xF000);
writememw(ss,(SP-4)&0xFFFF,CS);
writememw(ss,(SP-6)&0xFFFF,cpu_state.pc);
SP-=6;
flags&=~I_FLAG;
flags&=~T_FLAG;
cpu_state.pc=readmemw(0,0x14);
loadcs(readmemw(0,0x14+2));
FETCHCLEAR();
return;
}
cycles-=10;
break;
}
else /*JB alias*/
{
offset=(int8_t)FETCH();
if (flags&C_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
}
break;
case 0x62: /*JB alias*/
case 0x72: /*JB*/
offset=(int8_t)FETCH();
if (flags&C_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x63: /*JNB alias*/
case 0x63: /*JNB alias*/
case 0x73: /*JNB*/
offset=(int8_t)FETCH();
if (!(flags&C_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x64: /*JE alias*/
case 0x64: /*JE alias*/
case 0x74: /*JE*/
offset=(int8_t)FETCH();
if (flags&Z_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x65: /*JNE alias*/
case 0x65: /*JNE alias*/
case 0x75: /*JNE*/
offset=(int8_t)FETCH();
cycles-=4;
if (!(flags&Z_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
break;
case 0x66: /*JBE alias*/
case 0x66: /*JBE alias*/
case 0x76: /*JBE*/
offset=(int8_t)FETCH();
if (flags&(C_FLAG|Z_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x67: /*JNBE alias*/
case 0x67: /*JNBE alias*/
case 0x77: /*JNBE*/
offset=(int8_t)FETCH();
if (!(flags&(C_FLAG|Z_FLAG))) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x68:
if (is_nec) /*186+ PUSH imm*/
{
tempw = getword();
cpu_state.pc = tempw;
cycles-=2;
FETCHCLEAR();
return;
}
else /*JS alias*/
{
offset=(int8_t)FETCH();
if (flags&N_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
}
break;
case 0x68: /*JS alias*/
case 0x78: /*JS*/
offset=(int8_t)FETCH();
if (flags&N_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x69:
if (is_nec) /*186+ IMUL*/
{
tempw = geteaw();
tempw2 = getword();
templ = ((int)tempw) * ((int)tempw2);
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].w = templ & 0xffff;
cycles-=((cpu_mod==3)?14:17);
FETCHCLEAR();
break;
}
else /*JNS alias*/
{
offset=(int8_t)FETCH();
if (!(flags&N_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
}
break;
case 0x69: /*JNS alias*/
case 0x79: /*JNS*/
offset=(int8_t)FETCH();
if (!(flags&N_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x6A:
if (is_nec) /*186+ PUSH imm8*/
{
temp = (int8_t)FETCH();
cpu_state.pc = temp;
cycles-=2;
FETCHCLEAR();
return;
}
else /*JP alias*/
{
offset=(int8_t)FETCH();
if (flags&P_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
}
break;
case 0x6A: /*JP alias*/
case 0x7A: /*JP*/
offset=(int8_t)FETCH();
if (flags&P_FLAG) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
break;
case 0x6B:
if (is_nec) /*186+ IMUL byte*/
{
tempw = geteaw();
tempw2 = (int8_t)FETCH();
if (tempw2 & 0x80) tempw2 |= 0xff00;
templ = ((int)tempw) * ((int)tempw2);
if ((templ >> 15) != 0 && (templ >> 15) != -1) flags |= C_FLAG | V_FLAG;
else flags &= ~(C_FLAG | V_FLAG);
cpu_state.regs[cpu_reg].w = templ & 0xffff;
cycles-=((cpu_mod==3)?14:17);
FETCHCLEAR();
break;
}
else /*JNP alias*/
{
offset=(int8_t)FETCH();
if (!(flags&P_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
cycles-=4;
}
break;
case 0x6B: /*JNP alias*/
case 0x7B: /*JNP*/
offset=(int8_t)FETCH();
if (!(flags&P_FLAG)) { cpu_state.pc+=offset; cycles-=12; FETCHCLEAR(); }
@@ -2481,54 +2282,7 @@ void execx86(int cycs)
cycles-=((cpu_mod==3)?4:14);
break;
case 0xC8: /*186+ ENTER*/
if (is_nec)
{
uint16_t offsetw;
int count;
offsetw = getword();
tempw=readmemw(ss,SP);
tempw2=readmemw(ss,(SP-2)&0xFFFF);
tempw3=CS;
tempw4=cpu_state.pc;
if (cpu_state.ssegs) ss=oldss;
count=geteaw();
if (count > 0)
{
while (--count)
{
cpu_state.pc=tempw;
loadcs(tempw2);
cycles-=4;
}
writememw(ss,(SP-2)&0xFFFF,tempw3);
writememw(ss,((SP-4)&0xFFFF),tempw4);
cycles-=5;
}
cpu_state.last_ea = SP;
SP-=offsetw;
cycles-=10;
FETCHCLEAR();
break;
}
else /*RETF alias*/
{
tempw=getword();
if (cpu_state.ssegs) ss=oldss;
cpu_state.pc=readmemw(ss,SP);
loadcs(readmemw(ss,SP+2));
SP+=4;
SP+=tempw;
cycles-=33;
FETCHCLEAR();
}
break;
case 0xC8: /*RETF alias*/
case 0xCA: /*RETF*/
tempw=getword();
if (cpu_state.ssegs) ss=oldss;
@@ -2539,27 +2293,7 @@ void execx86(int cycs)
cycles-=33;
FETCHCLEAR();
break;
case 0xC9:
if (is_nec) /*186+ LEAVE*/
{
if (cpu_state.ssegs) ss=oldss;
cpu_state.regs[opcode&7].w=readmemw(ss,(SP-2)&0xFFFF);
cpu_state.last_ea = SP;
cycles-=4;
break;
}
else /*RETF alias*/
{
if (cpu_state.ssegs) ss=oldss;
cpu_state.pc=readmemw(ss,SP);
loadcs(readmemw(ss,SP+2));
SP+=4;
cycles-=34;
FETCHCLEAR();
}
break;
case 0xC9: /*RETF alias*/
case 0xCB: /*RETF*/
if (cpu_state.ssegs) ss=oldss;
cpu_state.pc=readmemw(ss,SP);

7
src/cpu/cpu.c
View File

@@ -8,7 +8,7 @@
*
* CPU type handler.
*
* Version: @(#)cpu.c 1.0.7 2018/07/19
* Version: @(#)cpu.c 1.0.6 2018/05/05
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
@@ -132,8 +132,7 @@ int cpu_waitstates;
int cpu_cache_int_enabled, cpu_cache_ext_enabled;
int cpu_pci_speed;
int is_nec,
is286,
int is286,
is386,
is486,
cpu_iscyrix,
@@ -244,7 +243,6 @@ cpu_set(void)
CPUID = cpu_s->cpuid_model;
cpuspeed = cpu_s->speed;
is8086 = (cpu_s->cpu_type > CPU_8088);
is_nec = (cpu_s->cpu_type == CPU_NEC);
is286 = (cpu_s->cpu_type >= CPU_286);
is386 = (cpu_s->cpu_type >= CPU_386SX);
israpidcad = (cpu_s->cpu_type == CPU_RAPIDCAD);
@@ -397,7 +395,6 @@ cpu_set(void)
{
case CPU_8088:
case CPU_8086:
case CPU_NEC:
break;
case CPU_286:

62
src/cpu/cpu.h
View File

@@ -8,7 +8,7 @@
*
* CPU type handler.
*
* Version: @(#)cpu.h 1.0.12 2018/07/19
* Version: @(#)cpu.h 1.0.11 2018/03/28
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* leilei,
@@ -24,43 +24,42 @@
#define CPU_8088 0 /* 808x class CPUs */
#define CPU_8086 1
#define CPU_NEC 2
#define CPU_286 3 /* 286 class CPUs */
#define CPU_386SX 4 /* 386 class CPUs */
#define CPU_386DX 5
#define CPU_RAPIDCAD 6
#define CPU_486SLC 7
#define CPU_486DLC 8
#define CPU_i486SX 9 /* 486 class CPUs */
#define CPU_Am486SX 10
#define CPU_Cx486S 11
#define CPU_i486DX 12
#define CPU_Am486DX 13
#define CPU_Cx486DX 14
#define CPU_iDX4 15
#define CPU_Cx5x86 16
#define CPU_WINCHIP 17 /* 586 class CPUs */
#define CPU_PENTIUM 18
#define CPU_PENTIUMMMX 19
#define CPU_Cx6x86 20
#define CPU_Cx6x86MX 21
#define CPU_Cx6x86L 22
#define CPU_CxGX1 23
#define CPU_286 2 /* 286 class CPUs */
#define CPU_386SX 3 /* 386 class CPUs */
#define CPU_386DX 4
#define CPU_RAPIDCAD 5
#define CPU_486SLC 6
#define CPU_486DLC 7
#define CPU_i486SX 8 /* 486 class CPUs */
#define CPU_Am486SX 9
#define CPU_Cx486S 10
#define CPU_i486DX 11
#define CPU_Am486DX 12
#define CPU_Cx486DX 13
#define CPU_iDX4 14
#define CPU_Cx5x86 15
#define CPU_WINCHIP 16 /* 586 class CPUs */
#define CPU_PENTIUM 17
#define CPU_PENTIUMMMX 18
#define CPU_Cx6x86 19
#define CPU_Cx6x86MX 20
#define CPU_Cx6x86L 21
#define CPU_CxGX1 22
#ifdef DEV_BRANCH
#ifdef USE_AMD_K
#define CPU_K5 24
#define CPU_5K86 25
#define CPU_K6 26
#define CPU_K5 23
#define CPU_5K86 24
#define CPU_K6 25
#endif
#endif
#ifdef DEV_BRANCH
#ifdef USE_I686
#define CPU_PENTIUMPRO 27 /* 686 class CPUs */
#define CPU_PENTIUMPRO 26 /* 686 class CPUs */
#if 0
# define CPU_PENTIUM2 28
# define CPU_PENTIUM2D 29
#else
# define CPU_PENTIUM2 27
# define CPU_PENTIUM2D 28
#else
# define CPU_PENTIUM2D 27
#endif
#endif
#endif
@@ -92,7 +91,6 @@ typedef struct {
extern CPU cpus_8088[];
extern CPU cpus_8086[];
extern CPU cpus_nec[];
extern CPU cpus_286[];
extern CPU cpus_i386SX[];
extern CPU cpus_i386DX[];
@@ -317,7 +315,7 @@ extern int cpu_multi;
extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
penalties when crossing 8-byte boundaries*/
extern int is8086, is_nec, is286, is386, is486;
extern int is8086, is286, is386, is486;
extern int is_rapidcad, is_pentium;
extern int hasfpu;
extern int cpu_hasrdtsc;

14
src/cpu/cpu_table.c
View File

@@ -29,7 +29,7 @@
* 16 = 180 MHz
* 17 = 200 MHz
*
* Version: @(#)cpu_table.c 1.0.5 2018/07/19
* Version: @(#)cpu_table.c 1.0.5 2018/07/17
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* leilei,
@@ -55,7 +55,6 @@ CPU cpus_8088[] = {
{"8088/4.77", CPU_8088, 0, 4772728, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"8088/7.16", CPU_8088, 1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"8088/8", CPU_8088, 1, 8000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"8088/10", CPU_8088, 2, 10000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0}
};
@@ -82,17 +81,6 @@ CPU cpus_8086[] = {
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0}
};
CPU cpus_nec[] = {
/*NEC V20/30 standard*/
{"V20/7.16", CPU_NEC, 1, 14318184/2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"V20/8", CPU_NEC, 1, 8000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"V20/9.54", CPU_NEC, 1, 4772728*2, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"V20/10", CPU_NEC, 2, 10000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"V20/12", CPU_NEC, 3, 12000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},
{"V20/16", CPU_NEC, 4, 16000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 2},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0}
};
CPU cpus_pc1512[] = {
/*8086 Amstrad*/
{"8086/8", CPU_8086, 1, 8000000, 1, 0, 0, 0, 0, 0, 0,0,0,0, 1},