Experimental Implementation of the ALi Aladdin IV
Popular chipset casually used on the PC Chips motherboards rebranded as TXPro. The implementation is extremely early with many bugs surrounding both machines it comes with.
This commit is contained in:
Panagiotis
GitHub
148
src/acpi.c
148
src/acpi.c
@@ -97,7 +97,7 @@ acpi_raise_smi(void *priv)
|
||||
smi_line = 1;
|
||||
dev->regs.smi_active = 1;
|
||||
}
|
||||
} else if (dev->vendor == VEN_INTEL) {
|
||||
} else if ((dev->vendor == VEN_INTEL) || (dev->vendor == VEN_ALI)) {
|
||||
smi_line = 1;
|
||||
/* Clear bit 16 of GLBCTL. */
|
||||
dev->regs.glbctl &= ~0x00010000;
|
||||
@@ -152,6 +152,65 @@ acpi_reg_read_common_regs(int size, uint16_t addr, void *p)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
acpi_reg_read_ali(int size, uint16_t addr, void *p)
|
||||
{
|
||||
acpi_t *dev = (acpi_t *) p;
|
||||
uint32_t ret = 0x00000000;
|
||||
int shift16, shift32;
|
||||
|
||||
addr &= 0x3f;
|
||||
shift16 = (addr & 1) << 3;
|
||||
shift32 = (addr & 3) << 3;
|
||||
|
||||
switch(addr)
|
||||
{
|
||||
case 0x10: case 0x11: case 0x12: case 0x13:
|
||||
/* PCNTRL - Processor Control Register (IO) */
|
||||
ret = (dev->regs.pcntrl >> shift16) & 0xff;
|
||||
break;
|
||||
case 0x14:
|
||||
/* LVL2 - Processor Level 2 Register */
|
||||
ret = dev->regs.plvl2;
|
||||
break;
|
||||
case 0x15:
|
||||
/* LVL3 - Processor Level 3 Register */
|
||||
ret = dev->regs.plvl3;
|
||||
break;
|
||||
case 0x18: case 0x19:
|
||||
/* GPE0_STS - General Purpose Event0 Status Register */
|
||||
ret = (dev->regs.gpsts >> shift16) & 0xff;
|
||||
break;
|
||||
case 0x1a: case 0x1b:
|
||||
/* GPE0_EN - General Purpose Event0 Enable Register */
|
||||
ret = (dev->regs.gpen >> shift16) & 0xff;
|
||||
break;
|
||||
case 0x1d: case 0x1c:
|
||||
/* GPE1_STS - General Purpose Event1 Status Register */
|
||||
ret = (dev->regs.gpsts >> shift16) & 0xff;
|
||||
break;
|
||||
case 0x1f: case 0x1e:
|
||||
/* GPE1_EN - General Purpose Event1 Enable Register */
|
||||
ret = (dev->regs.gpen1 >> shift16) & 0xff;
|
||||
break;
|
||||
case 0x20 ... 0x27:
|
||||
/* GPE1_CTL - General Purpose Event1 Control Register */
|
||||
ret = (dev->regs.gpcntrl >> shift32) & 0xff;
|
||||
break;
|
||||
case 0x30:
|
||||
/* PM2_CNTRL - Power Management 2 Control Register( */
|
||||
ret = dev->regs.pmcntrl;
|
||||
break;
|
||||
default:
|
||||
ret = acpi_reg_read_common_regs(size, addr, p);
|
||||
break;
|
||||
}
|
||||
#ifdef ENABLE_ACPI_LOG
|
||||
if (size != 1)
|
||||
acpi_log("(%i) ACPI Read (%i) %02X: %02X\n", in_smm, size, addr, ret);
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
acpi_reg_read_intel(int size, uint16_t addr, void *p)
|
||||
@@ -518,6 +577,69 @@ acpi_reg_write_common_regs(int size, uint16_t addr, uint8_t val, void *p)
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
acpi_reg_write_ali(int size, uint16_t addr, uint8_t val, void *p)
|
||||
{
|
||||
acpi_t *dev = (acpi_t *) p;
|
||||
int shift16, shift32;
|
||||
|
||||
addr &= 0x3f;
|
||||
#ifdef ENABLE_ACPI_LOG
|
||||
if (size != 1)
|
||||
acpi_log("(%i) ACPI Write (%i) %02X: %02X\n", in_smm, size, addr, val);
|
||||
#endif
|
||||
shift16 = (addr & 1) << 3;
|
||||
shift32 = (addr & 3) << 3;
|
||||
|
||||
switch (addr) {
|
||||
case 0x10: case 0x11: case 0x12: case 0x13:
|
||||
/* PCNTRL - Processor Control Register (IO) */
|
||||
dev->regs.pcntrl = ((dev->regs.pcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00023e1e;
|
||||
break;
|
||||
case 0x14:
|
||||
/* LVL2 - Processor Level 2 Register */
|
||||
dev->regs.plvl2 = val;
|
||||
break;
|
||||
case 0x15:
|
||||
/* LVL3 - Processor Level 3 Register */
|
||||
dev->regs.plvl3 = val;
|
||||
break;
|
||||
case 0x18: case 0x19:
|
||||
/* GPE0_STS - General Purpose Event0 Status Register */
|
||||
dev->regs.gpsts &= ~((val << shift16) & 0x0d07);
|
||||
break;
|
||||
case 0x1a: case 0x1b:
|
||||
/* GPE0_EN - General Purpose Event0 Enable Register */
|
||||
dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0d07;
|
||||
break;
|
||||
case 0x1d: case 0x1c:
|
||||
/* GPE1_STS - General Purpose Event1 Status Register */
|
||||
dev->regs.gpsts &= ~((val << shift16) & 0x0c01);
|
||||
break;
|
||||
case 0x1f: case 0x1e:
|
||||
/* GPE1_EN - General Purpose Event1 Enable Register */
|
||||
dev->regs.gpen = ((dev->regs.gpen & ~(0xff << shift16)) | (val << shift16)) & 0x0c01;
|
||||
break;
|
||||
case 0x20 ... 0x27:
|
||||
/* GPE1_CTL - General Purpose Event1 Control Register */
|
||||
dev->regs.gpcntrl = ((dev->regs.gpcntrl & ~(0xff << shift32)) | (val << shift32)) & 0x00000001;
|
||||
break;
|
||||
case 0x30:
|
||||
/* PM2_CNTRL - Power Management 2 Control Register( */
|
||||
dev->regs.pmcntrl = val & 1;
|
||||
break;
|
||||
default:
|
||||
acpi_reg_write_common_regs(size, addr, val, p);
|
||||
/* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
|
||||
if ((addr == 0x00) && !(dev->regs.pmsts & 0x20))
|
||||
dev->regs.glbctl &= ~0x0002;
|
||||
else if ((addr == 0x04) && (dev->regs.pmcntrl & 0x0004)) {
|
||||
dev->regs.glbsts |= 0x01;
|
||||
if (dev->regs.glben & 0x02)
|
||||
acpi_raise_smi(dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *p)
|
||||
@@ -823,7 +945,9 @@ acpi_reg_read_common(int size, uint16_t addr, void *p)
|
||||
acpi_t *dev = (acpi_t *) p;
|
||||
uint8_t ret = 0xff;
|
||||
|
||||
if (dev->vendor == VEN_VIA)
|
||||
if (dev->vendor == VEN_ALI)
|
||||
ret = acpi_reg_read_ali(size, addr, p);
|
||||
else if (dev->vendor == VEN_VIA)
|
||||
ret = acpi_reg_read_via(size, addr, p);
|
||||
else if (dev->vendor == VEN_VIA_596B)
|
||||
ret = acpi_reg_read_via_596b(size, addr, p);
|
||||
@@ -841,6 +965,8 @@ acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
|
||||
{
|
||||
acpi_t *dev = (acpi_t *) p;
|
||||
|
||||
if (dev->vendor == VEN_ALI)
|
||||
acpi_reg_write_ali(size, addr, val, p);
|
||||
if (dev->vendor == VEN_VIA)
|
||||
acpi_reg_write_via(size, addr, val, p);
|
||||
else if (dev->vendor == VEN_VIA_596B)
|
||||
@@ -1021,6 +1147,7 @@ acpi_update_io_mapping(acpi_t *dev, uint32_t base, int chipset_en)
|
||||
int size;
|
||||
|
||||
switch (dev->vendor) {
|
||||
case VEN_ALI:
|
||||
case VEN_INTEL:
|
||||
default:
|
||||
size = 0x040;
|
||||
@@ -1173,7 +1300,7 @@ acpi_apm_out(uint16_t port, uint8_t val, void *p)
|
||||
if (port == 0x0000) {
|
||||
dev->apm->cmd = val;
|
||||
if (dev->apm->do_smi) {
|
||||
if (dev->vendor == VEN_INTEL)
|
||||
if ((dev->vendor == VEN_INTEL) || (dev->vendor == VEN_ALI))
|
||||
dev->regs.glbsts |= 0x20;
|
||||
acpi_raise_smi(dev);
|
||||
}
|
||||
@@ -1285,7 +1412,7 @@ acpi_init(const device_t *info)
|
||||
|
||||
dev->irq_line = 9;
|
||||
|
||||
if (dev->vendor == VEN_INTEL) {
|
||||
if ((dev->vendor == VEN_INTEL) || (dev->vendor == VEN_ALI)) {
|
||||
dev->apm = device_add(&apm_pci_acpi_device);
|
||||
io_sethandler(0x00b2, 0x0002, acpi_apm_in, NULL, NULL, acpi_apm_out, NULL, NULL, dev);
|
||||
} else if (dev->vendor == VEN_VIA) {
|
||||
@@ -1301,6 +1428,19 @@ acpi_init(const device_t *info)
|
||||
return dev;
|
||||
}
|
||||
|
||||
const device_t acpi_ali_device =
|
||||
{
|
||||
"ALi M7101 ACPI",
|
||||
DEVICE_PCI,
|
||||
VEN_ALI,
|
||||
acpi_init,
|
||||
acpi_close,
|
||||
acpi_reset,
|
||||
{ NULL },
|
||||
acpi_speed_changed,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
const device_t acpi_intel_device =
|
||||
{
|
||||
|
||||
Reference in New Issue
Block a user