Experimental Implementation of the ALi Aladdin IV
Popular chipset casually used on the PC Chips motherboards rebranded as TXPro. The implementation is extremely early with many bugs surrounding both machines it comes with.
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Panagiotis
GitHub
296
src/chipset/ali1531.c
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296
src/chipset/ali1531.c
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the ALi M1531B CPU-to-PCI Bridge.
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*
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*
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*
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* Authors: Tiseno100,
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*
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* Copyright 2021 Tiseno100.
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*
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/timer.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/smram.h>
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#include <86box/spd.h>
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#include <86box/chipset.h>
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typedef struct ali1531_t
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{
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uint8_t pci_conf[256];
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smram_t *smram;
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} ali1531_t;
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void ali1531_shadow_recalc(ali1531_t *dev)
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{
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for (uint32_t i = 0; i < 8; i++)
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{
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mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4c] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4e] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4d] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4f] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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}
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}
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void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev)
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{
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if (!!(dev->pci_conf[0x48] & 1))
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{
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switch (smm_state)
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{
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case 0:
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smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, 0, 1);
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smram_map(1, 0xd0000, 0x10000, 1);
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break;
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case 1:
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smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, 1, 1);
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smram_map(1, 0xd0000, 0x10000, 1);
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break;
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case 2:
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smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, 0, 1);
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smram_map(1, 0xa0000, 0x20000, (dev->pci_conf[0x48] & 0x10) ? 2 : 1);
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break;
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case 3:
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smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, 1, 1);
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smram_map(1, 0xa0000, 0x20000, (dev->pci_conf[0x48] & 0x10) ? 2 : 1);
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break;
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case 4:
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smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, 0, 1);
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smram_map(1, 0x30000, 0x10000, 1);
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break;
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case 5:
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smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, 1, 1);
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smram_map(1, 0x30000, 0x10000, 1);
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break;
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}
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}
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else
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smram_disable_all();
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flushmmucache();
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}
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static void
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ali1531_write(int func, int addr, uint8_t val, void *priv)
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{
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ali1531_t *dev = (ali1531_t *)priv;
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switch (addr)
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{
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case 0x05:
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dev->pci_conf[addr] = val & 1;
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break;
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case 0x07:
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dev->pci_conf[addr] = val & 0xfe;
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break;
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case 0x0d:
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dev->pci_conf[addr] = val & 0xf8;
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break;
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case 0x40:
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dev->pci_conf[addr] = val & 0xf1;
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break;
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case 0x41:
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dev->pci_conf[addr] = val & 0xdf;
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break;
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case 0x42: /* L2 Cache */
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dev->pci_conf[addr] = val & 0xf7;
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cpu_cache_ext_enabled = !!(val & 1);
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cpu_update_waitstates();
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break;
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case 0x43: /* L1 Cache */
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dev->pci_conf[addr] = val;
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cpu_cache_int_enabled = !!(val & 1);
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cpu_update_waitstates();
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break;
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case 0x47:
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dev->pci_conf[addr] = val & 0xfc;
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if (mem_size > 0xe00000)
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mem_set_mem_state_both(0xe00000, 0x100000, !(val & 0x20) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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if (mem_size > 0xf00000)
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mem_set_mem_state_both(0xf00000, 0x100000, !(val & 0x10) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
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break;
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case 0x48: /* SMRAM */
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dev->pci_conf[addr] = val;
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ali1531_smm_recalc((val >> 1) & 7, dev);
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break;
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case 0x49:
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dev->pci_conf[addr] = val & 0x73;
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break;
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case 0x4c: /* Shadow RAM */
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case 0x4d:
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case 0x4e:
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case 0x4f:
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dev->pci_conf[addr] = val;
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ali1531_shadow_recalc(dev);
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break;
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case 0x57: /* H2PO */
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dev->pci_conf[addr] = val & 0x60;
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if (!(val & 0x20))
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outb(0x92, 0x01);
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break;
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case 0x58:
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dev->pci_conf[addr] = val & 0x83;
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break;
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case 0x5b:
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dev->pci_conf[addr] = val & 0x4f;
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break;
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case 0x5d:
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dev->pci_conf[addr] = val & 0x53;
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break;
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case 0x5f:
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dev->pci_conf[addr] = val & 0x7f;
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break;
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case 0x60 ... 0x6f: /* DRB's */
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dev->pci_conf[addr] = val;
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spd_write_drbs(dev->pci_conf, 0x60, 0x6f, 2);
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break;
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case 0x72:
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dev->pci_conf[addr] = val & 0xf;
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break;
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case 0x74:
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dev->pci_conf[addr] = val & 0x2b;
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break;
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case 0x80:
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dev->pci_conf[addr] = val & 0x84;
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break;
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case 0x81:
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dev->pci_conf[addr] = val & 0x81;
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break;
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case 0x83:
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dev->pci_conf[addr] = val & 0x10;
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break;
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default:
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dev->pci_conf[addr] = val;
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break;
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}
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}
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static uint8_t
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ali1531_read(int func, int addr, void *priv)
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{
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ali1531_t *dev = (ali1531_t *)priv;
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return dev->pci_conf[addr];
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}
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static void
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ali1531_reset(void *priv)
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{
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ali1531_t *dev = (ali1531_t *)priv;
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/* Default Registers */
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dev->pci_conf[0x00] = 0xb9;
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dev->pci_conf[0x01] = 0x10;
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dev->pci_conf[0x02] = 0x31;
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dev->pci_conf[0x03] = 0x15;
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dev->pci_conf[0x04] = 0x06;
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dev->pci_conf[0x05] = 0x00;
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dev->pci_conf[0x06] = 0x00;
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dev->pci_conf[0x07] = 0x04;
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dev->pci_conf[0x08] = 0xb0;
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dev->pci_conf[0x09] = 0x00;
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dev->pci_conf[0x0a] = 0x00;
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dev->pci_conf[0x0b] = 0x06;
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dev->pci_conf[0x0c] = 0x00;
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dev->pci_conf[0x0d] = 0x20;
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dev->pci_conf[0x0e] = 0x00;
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dev->pci_conf[0x0f] = 0x00;
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dev->pci_conf[0x2c] = 0xb9;
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dev->pci_conf[0x2d] = 0x10;
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dev->pci_conf[0x2e] = 0x31;
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dev->pci_conf[0x2f] = 0x15;
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dev->pci_conf[0x52] = 0xf0;
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dev->pci_conf[0x54] = 0xff;
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dev->pci_conf[0x55] = 0xff;
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dev->pci_conf[0x59] = 0x20;
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dev->pci_conf[0x5a] = 0x20;
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dev->pci_conf[0x70] = 0x22;
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ali1531_write(0, 0x42, 0x00, dev);
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ali1531_write(0, 0x43, 0x00, dev);
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ali1531_write(0, 0x47, 0x00, dev);
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ali1531_shadow_recalc(dev);
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ali1531_write(0, 0x60, 0x08, dev);
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ali1531_write(0, 0x61, 0x40, dev);
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}
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static void
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ali1531_close(void *priv)
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{
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ali1531_t *dev = (ali1531_t *)priv;
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smram_del(dev->smram);
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free(dev);
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}
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static void *
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ali1531_init(const device_t *info)
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{
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ali1531_t *dev = (ali1531_t *)malloc(sizeof(ali1531_t));
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memset(dev, 0, sizeof(ali1531_t));
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pci_add_card(PCI_ADD_NORTHBRIDGE, ali1531_read, ali1531_write, dev);
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dev->smram = smram_add();
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ali1531_reset(dev);
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return dev;
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}
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const device_t ali1531_device = {
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"ALi M1531 CPU-to-PCI Bridge",
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DEVICE_PCI,
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0,
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ali1531_init,
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ali1531_close,
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ali1531_reset,
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{NULL},
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NULL,
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NULL,
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NULL};
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