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Merge branch 'master' of https://github.com/86Box/86Box

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This commit is contained in:
RichardG867
2021-04-13 14:10:48 -03:00
parent b02e346943 3746b722c7
commit 80b1340454
51 changed files with 4565 additions and 4526 deletions
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64
src/chipset/intel_4x0.c
View File

@@ -120,20 +120,22 @@ i4x0_smram_handler_phase0(i4x0_t *dev)
static void
i4x0_smram_handler_phase1(i4x0_t *dev)
{
uint8_t *regs = (uint8_t *) dev->regs;
uint32_t tom = (mem_size << 10);
uint8_t *reg = (dev->type >= INTEL_430LX) ? &(regs[0x72]) : &(regs[0x57]);
uint8_t *ext_reg = (dev->type >= INTEL_440BX) ? &(regs[0x73]) : &(regs[0x71]);
uint32_t s, base[2] = { 0x000a0000, 0x00000000 };
uint32_t size[2] = { 0x00010000, 0x00000000 };
if (dev->type >= INTEL_430FX) {
if ((dev->type <= INTEL_420ZX) || (dev->type >= INTEL_430FX)) {
/* Set temporary bases and sizes. */
if (((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) &&
(*ext_reg & 0x80)) {
base[0] = 0x100a0000;
size[0] = 0x00060000;
} else if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((regs[0x72] & 0x07) == 0x04)) {
} else if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((*reg & 0x07) == 0x04)) {
base[0] = 0x000c0000;
size[0] = 0x00010000;
} else {
@@ -141,11 +143,11 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
size[0] = 0x00020000;
}
if (regs[0x72] & 0x08)
if (*reg & 0x08)
smram_enable(dev->smram_low, base[0], base[0] & 0x000f0000, size[0],
((regs[0x72] & 0x78) == 0x48), (regs[0x72] & 0x08));
((*reg & 0x78) == 0x48), (*reg & 0x08));
if ((regs[0x72] & 0x28) == 0x28) {
if ((*reg & 0x28) == 0x28) {
/* If SMRAM is enabled and DCLS is set, then data goes to PCI, but
code still goes to DRAM. */
mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02);
@@ -153,7 +155,7 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
/* TSEG mapping. */
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
if ((regs[0x72] & 0x08) && (*ext_reg & 0x01)) {
if ((*reg & 0x08) && (*ext_reg & 0x01)) {
size[1] = (1 << (17 + ((*ext_reg >> 1) & 0x03)));
tom -= size[1];
base[1] = tom;
@@ -169,7 +171,7 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
}
} else {
size[0] = 0x00010000;
switch (regs[0x72] & 0x03) {
switch (*reg & 0x03) {
case 0:
default:
base[0] = (mem_size << 10) - size[0];
@@ -191,9 +193,9 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
if (size[0] != 0x00000000) {
smram_enable(dev->smram_low, base[0], base[0], size[0],
(((regs[0x72] & 0x38) == 0x20) || s), 1);
(((*reg & 0x38) == 0x20) || s), 1);
if (regs[0x72] & 0x10) {
if (*reg & 0x10) {
/* If SMRAM is enabled and DCLS is set, then data goes to PCI, but
code still goes to DRAM. */
mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02);
@@ -517,7 +519,19 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x57:
switch (dev->type) {
/* On the 420TX and 420ZX, this is the SMRAM space register. */
case INTEL_420TX: case INTEL_420ZX:
i4x0_smram_handler_phase0(dev);
if (dev->smram_locked)
regs[0x57] = (regs[0x57] & 0xdf) | (val & 0x20);
else {
regs[0x57] = (regs[0x57] & 0x87) | (val & 0x78);
dev->smram_locked = (val & 0x10);
if (dev->smram_locked)
regs[0x57] &= 0xbf;
}
i4x0_smram_handler_phase1(dev);
break;
case INTEL_430LX: default:
regs[0x57] = val & 0x3f;
break;
@@ -824,6 +838,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
}
break;
case 0x72: /* SMRAM */
if (dev->type <= INTEL_420ZX)
break;
i4x0_smram_handler_phase0(dev);
if (dev->type >= INTEL_430FX) {
if (dev->smram_locked)
@@ -1215,6 +1232,10 @@ i4x0_reset(void *priv)
i4x0_t *dev = (i4x0_t *)priv;
int i;
if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) ||
(dev->type == INTEL_440ZX))
memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x59, 0x00, priv);
else
@@ -1229,14 +1250,18 @@ i4x0_reset(void *priv)
if (dev->type >= INTEL_430FX) {
dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x02, priv);
} else {
} else if (dev->type >= INTEL_430LX) {
dev->regs[0x72] &= 0xf7; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x00, priv);
} else {
dev->regs[0x57] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x57, 0x02, priv);
}
if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) ||
(dev->type == INTEL_440ZX))
memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv);
}
}
@@ -1554,7 +1579,18 @@ static void
i4x0_write(regs[0x5d], 0x5d, 0x00, dev);
i4x0_write(regs[0x5e], 0x5e, 0x00, dev);
i4x0_write(regs[0x5f], 0x5f, 0x00, dev);
i4x0_write(regs[0x72], 0x72, 0x00, dev);
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x72, 0x02, dev);
else if (dev->type >= INTEL_430LX)
i4x0_write(0, 0x72, 0x00, dev);
else
i4x0_write(0, 0x57, 0x02, dev);
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev);
}
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev);

27
src/chipset/intel_i450kx.c
View File

@@ -66,9 +66,9 @@ i450kx_log(const char *fmt, ...)
/* SMRAM */
#define SMRAM_ADDR (((dev->pb_pci_conf[0xb9] << 8) | dev->pb_pci_conf[0xb8]) << 17)
#define SMRAM_SIZE (1 << (((dev->pb_pci_conf[0xbb] >> 4) + 1) * 16))
#define SMRAM_ADDR_MC (((dev->mc_pci_conf[0xb9] << 8) | dev->mc_pci_conf[0xb8]) << 16)
#define SMRAM_SIZE_MC (1 << (((dev->mc_pci_conf[0xbb] >> 4) + 1) * 16))
#define SMRAM_SIZE (((dev->pb_pci_conf[0xbb] >> 4) + 1) * 64)
#define SMRAM_SIZE_MC (((dev->mc_pci_conf[0xbb] >> 4) + 1) * 64)
/* Miscellaneous */
#define ENABLE_SEGMENT (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
@@ -101,10 +101,7 @@ void i450kx_smm(uint32_t smram_addr, uint32_t smram_size, i450kx_t *dev)
smram_disable_all();
if ((smram_addr != 0) && !!(dev->mc_pci_conf[0x57] & 8))
{
smram_enable(dev->smram, smram_addr, smram_addr, smram_size, !!(dev->pb_pci_conf[0x57] & 8), 1);
mem_set_mem_state_smram_ex(1, smram_addr, smram_size, 0x03);
}
flushmmucache();
}
@@ -263,11 +260,7 @@ pb_write(int func, int addr, uint8_t val, void *priv)
case 0xb8:
case 0xb9:
case 0xbb:
if (addr == 0xbb)
dev->pb_pci_conf[addr] = val & 0xf0;
else
dev->pb_pci_conf[addr] = val;
dev->pb_pci_conf[addr] = !(addr == 0xbb) ? val : (val & 0xf0);
i450kx_smm(SMRAM_ADDR, SMRAM_SIZE, dev);
break;
@@ -324,7 +317,6 @@ mc_write(int func, int addr, uint8_t val, void *priv)
case 0x58:
dev->mc_pci_conf[addr] = val & 2;
mem_set_mem_state_both(0xa0000, 0x20000, (val & 2) ? ENABLE_SEGMENT : DISABLE_SEGMENT);
break;
case 0x59:
@@ -354,8 +346,8 @@ mc_write(int func, int addr, uint8_t val, void *priv)
case 0x6d:
case 0x6e:
case 0x6f:
dev->mc_pci_conf[addr] = ((addr & 0x0f) % 2) ? val : (val & 7);
spd_write_drbs(dev->mc_pci_conf, 0x60, 0x6f, 1);
dev->mc_pci_conf[addr] = ((addr & 0x0f) % 2) ? 0 : (val & 0x7f);
spd_write_drbs(dev->mc_pci_conf, 0x60, 0x6f, 4);
break;
case 0x74:
@@ -447,10 +439,7 @@ mc_write(int func, int addr, uint8_t val, void *priv)
case 0xb8:
case 0xb9:
case 0xbb:
if (addr == 0xbb)
dev->mc_pci_conf[addr] = val & 0xf0;
else
dev->mc_pci_conf[addr] = val;
dev->mc_pci_conf[addr] = !(addr == 0xbb) ? val : (val & 0xf0);
i450kx_smm(SMRAM_ADDR_MC, SMRAM_SIZE_MC, dev);
break;
@@ -500,7 +489,7 @@ i450kx_reset(void *priv)
dev->pb_pci_conf[0x05] = 4;
dev->pb_pci_conf[0x06] = 0x40;
dev->pb_pci_conf[0x07] = 2;
dev->pb_pci_conf[0x08] = 1;
dev->pb_pci_conf[0x08] = 2;
dev->pb_pci_conf[0x0b] = 6;
dev->pb_pci_conf[0x0c] = 8;
dev->pb_pci_conf[0x0d] = 0x20;
@@ -526,7 +515,7 @@ i450kx_reset(void *priv)
dev->mc_pci_conf[0x02] = 0xc5;
dev->mc_pci_conf[0x03] = 0x84;
dev->mc_pci_conf[0x06] = 0x80;
dev->mc_pci_conf[0x08] = 1;
dev->mc_pci_conf[0x08] = 4;
dev->mc_pci_conf[0x0b] = 5;
dev->mc_pci_conf[0x49] = 0x14;
dev->mc_pci_conf[0x4c] = 0x0b;

2
src/chipset/intel_piix.c
View File

@@ -1374,6 +1374,8 @@ static void
else
dev->board_config[1] |= 0x00;
device_add(&i8254_sec_device);
return dev;
}

3
src/chipset/intel_sio.c
View File

@@ -218,7 +218,6 @@ sio_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x60: case 0x61: case 0x62: case 0x63:
if (dev->id == 0x03) {
pclog("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val);
sio_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val);
dev->regs[addr] = val & 0x8f;
if (val & 0x80)
@@ -540,6 +539,8 @@ sio_init(const device_t *info)
timer_add(&dev->timer, NULL, NULL, 0);
device_add(&i8254_sec_device);
return dev;
}

13
src/chipset/sis_85c496.c
View File

@@ -299,7 +299,7 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
smram_disable_all();
if (val & 0x06) {
if (val & 0x02) {
host_base = 0x00060000;
ram_base = 0x000a0000;
size = 0x00010000;
@@ -453,6 +453,12 @@ sis_85c49x_pci_read(int func, int addr, void *priv)
uint8_t ret = dev->pci_conf[addr];
switch (addr) {
case 0xa0:
ret &= 0x10;
break;
case 0xa1:
ret = 0x00;
break;
case 0x82: /*Port 22h Mirror*/
ret = dev->cur_reg;
break;
@@ -517,6 +523,7 @@ sis_85c496_reset(void *priv)
sis_85c49x_pci_write(0, 0x58, 0x00, dev);
sis_85c49x_pci_write(0, 0x59, 0x00, dev);
sis_85c49x_pci_write(0, 0x5a, 0x00, dev);
// sis_85c49x_pci_write(0, 0x5a, 0x06, dev);
for (i = 0; i < 8; i++)
sis_85c49x_pci_write(0, 0x48 + i, 0x00, dev);
@@ -589,7 +596,7 @@ static void
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev);
sis_85c497_isa_reset(dev);
// sis_85c497_isa_reset(dev);
dev->port_92 = device_add(&port_92_device);
port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);
@@ -609,6 +616,8 @@ static void
timer_add(&dev->rmsmiblk_timer, sis_85c496_rmsmiblk_count, dev, 0);
sis_85c496_reset(dev);
return dev;
}