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Merge pull request #1303 from richardg867/master

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AGP and clock control
This commit is contained in:
Miran Grča
2021-03-15 22:50:31 +01:00
committed by GitHub
parent 0bf5001a8a 969a1ee3ae
commit 82b26f75be
21 changed files with 431 additions and 133 deletions
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10
src/chipset/ali1543.c
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@@ -891,13 +891,13 @@ ali1543_init(const device_t *info)
dev->pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, ali1533_read, ali1533_write, dev);
/* Device 0B: M5229 IDE Controller*/
dev->ide_slot = pci_add_card(PCI_ADD_IDE, ali5229_read, ali5229_write, dev);
/* Device 0D: M5237 USB */
dev->usb_slot = pci_add_card(PCI_ADD_NORMAL_NOBRIDGE, ali5237_read, ali5237_write, dev);
dev->ide_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, ali5229_read, ali5229_write, dev);
/* Device 0C: M7101 Power Managment Controller */
dev->pmu_slot = pci_add_card(PCI_ADD_BRIDGE, ali7101_read, ali7101_write, dev);
dev->pmu_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, ali7101_read, ali7101_write, dev);
/* Device 0D: M5237 USB */
dev->usb_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, ali5237_read, ali5237_write, dev);
/* Ports 3F0-1h: M1543 Super I/O */
io_sethandler(0x03f0, 0x0002, ali1533_sio_read, NULL, NULL, ali1533_sio_write, NULL, NULL, dev);

38
src/chipset/ali6117.c
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@@ -146,6 +146,42 @@ ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
case 0x1e:
val &= 0x07;
switch (val) {
/* Half PIT clock. */
case 0x0:
cpu_set_isa_speed(7159091);
break;
/* Divisors on the input clock PCLK2, which is double the CPU clock. */
case 0x1:
cpu_set_isa_speed(cpu_busspeed / 1.5);
break;
case 0x2:
cpu_set_isa_speed(cpu_busspeed / 2);
break;
case 0x3:
cpu_set_isa_speed(cpu_busspeed / 2.5);
break;
case 0x4:
cpu_set_isa_speed(cpu_busspeed / 3);
break;
case 0x5:
cpu_set_isa_speed(cpu_busspeed / 4);
break;
case 0x6:
cpu_set_isa_speed(cpu_busspeed / 5);
break;
case 0x7:
cpu_set_isa_speed(cpu_busspeed / 6);
break;
}
break;
case 0x20:
@@ -282,6 +318,8 @@ ali6117_reset(void *priv)
dev->regs[0x34] = 0x04; /* enable internal RTC */
dev->regs[0x35] = 0x20; /* enable internal KBC */
dev->regs[0x36] = dev->local & 0x4; /* M6117D ID */
cpu_set_isa_speed(7159091);
}

9
src/chipset/intel_4x0.c
View File

@@ -1540,6 +1540,15 @@ static void
cpu_update_waitstates();
}
/* Out-of-spec PCI and AGP clocks with overclocked bus. */
if ((dev->type <= INTEL_440FX) && (cpu_busspeed >= 66666666))
cpu_set_pci_speed(cpu_busspeed / 2);
if ((dev->type >= INTEL_440BX) && (cpu_busspeed >= 100000000))
cpu_set_agp_speed(cpu_busspeed / 1.5);
else if (dev->type >= INTEL_440LX)
cpu_set_agp_speed(cpu_busspeed);
i4x0_write(regs[0x59], 0x59, 0x00, dev);
i4x0_write(regs[0x5a], 0x5a, 0x00, dev);
i4x0_write(regs[0x5b], 0x5b, 0x00, dev);

7
src/chipset/intel_piix.c
View File

@@ -1237,9 +1237,10 @@ static void
piix_speed_changed(void *priv)
{
piix_t *dev = (piix_t *) priv;
int te;
if (!dev)
return;
te = timer_is_enabled(&dev->fast_off_timer);
int te = timer_is_enabled(&dev->fast_off_timer);
timer_stop(&dev->fast_off_timer);
if (te)
@@ -1306,6 +1307,8 @@ static void
dev->port_92 = device_add(&port_92_pci_device);
cpu_set_isa_pci_div(4);
dma_alias_set();
if (dev->type < 4)

38
src/chipset/via_apollo.c
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@@ -157,19 +157,33 @@ via_apollo_setup(via_apollo_t *dev)
if (dev->id >= VIA_691)
dev->pci_conf[0x67] = 0xec; /* DRAM Timing for Banks 6, 7 */
if (dev->id >= VIA_693A) {
if (cpu_busspeed < 95000000)
dev->pci_conf[0x68] |= 0x00; /* 66 MHz */
else if (cpu_busspeed < 124000000)
dev->pci_conf[0x68] |= 0x01; /* 100 MHz */
else
dev->pci_conf[0x68] |= (dev->id == VIA_8601) ? 0x03 : 0x02; /* 133 MHz */
if (cpu_busspeed < 95000000) { /* 66 MHz */
cpu_set_pci_speed(cpu_busspeed / 2);
cpu_set_agp_speed(cpu_busspeed);
dev->pci_conf[0x68] |= 0x00;
} else if (cpu_busspeed < 124000000) { /* 100 MHz */
cpu_set_pci_speed(cpu_busspeed / 3);
cpu_set_agp_speed(cpu_busspeed / 1.5);
dev->pci_conf[0x68] |= 0x01;
} else { /* 133 MHz */
cpu_set_pci_speed(cpu_busspeed / 4);
cpu_set_agp_speed(cpu_busspeed / 2);
dev->pci_conf[0x68] |= (dev->id == VIA_8601) ? 0x03 : 0x02;
}
} else if (dev->id >= VIA_598) {
if (cpu_busspeed < 75000000)
dev->pci_conf[0x68] |= 0x00; /* 66 MHz */
else if (cpu_busspeed < 100000000)
dev->pci_conf[0x68] |= (dev->id >= VIA_691) ? 0x00 : 0x03; /* 75/83 MHz (66 MHz on 691) */
else
dev->pci_conf[0x68] |= 0x01; /* 100 MHz */
if (cpu_busspeed < ((dev->id >= VIA_691) ? 100000000 : 75000000)) { /* 66 MHz */
cpu_set_pci_speed(cpu_busspeed / 2);
cpu_set_agp_speed(cpu_busspeed);
dev->pci_conf[0x68] |= 0x00;
} else if (cpu_busspeed < 100000000) { /* 75/83 MHz (not available on 691) */
cpu_set_pci_speed(cpu_busspeed / 2.5);
cpu_set_agp_speed(cpu_busspeed / 1.25);
dev->pci_conf[0x68] |= 0x03;
} else { /* 100 MHz */
cpu_set_pci_speed(cpu_busspeed / 3);
cpu_set_agp_speed(cpu_busspeed / 1.5);
dev->pci_conf[0x68] |= 0x01;
}
}
dev->pci_conf[0x6b] = 0x01;

48
src/chipset/via_pipc.c
View File

@@ -503,6 +503,52 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
dev->pci_isa_regs[0x07] &= ~(val & 0xb0);
break;
case 0x42:
dev->pci_isa_regs[0x42] = val & 0xcf;
switch (val & 0xf) {
/* Divisors on the PCI clock. */
case 0x8:
cpu_set_isa_pci_div(3);
break;
case 0x9:
cpu_set_isa_pci_div(2);
break;
case 0xa:
cpu_set_isa_pci_div(4);
break;
case 0xb:
cpu_set_isa_pci_div(6);
break;
case 0xc:
cpu_set_isa_pci_div(5);
break;
case 0xd:
cpu_set_isa_pci_div(10);
break;
case 0xe:
cpu_set_isa_pci_div(12);
break;
/* Half PIT clock. */
case 0xf:
cpu_set_isa_speed(7159091);
break;
/* Divisor 4 on the PCI clock whenever bit 3 is clear. */
default:
cpu_set_isa_pci_div(4);
break;
}
break;
case 0x47:
if (val & 0x01)
trc_write(0x0047, (val & 0x80) ? 0x06 : 0x04, NULL);
@@ -940,6 +986,8 @@ pipc_init(const device_t *info)
device_add(&port_92_pci_device);
cpu_set_isa_pci_div(4);
dma_alias_set();
if (dev->local <= VIA_PIPC_586B) {