Slight fixes to CL-GD 54xx and generic (S)VGA memory read/write code - fixes E-Ten 24x24 driver (and probably more) on CL-GD and even the Tridents (though the second half of the screen is glitched on Tridents, which is an interlace bug and needs to be looked into).
This commit is contained in:
@@ -9,7 +9,7 @@
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* Emulation of select Cirrus Logic cards (CL-GD 5428,
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* CL-GD 5429, CL-GD 5430, CL-GD 5434 and CL-GD 5436 are supported).
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*
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* Version: @(#)vid_cl_54xx.c 1.0.25 2018/10/04
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* Version: @(#)vid_cl_54xx.c 1.0.26 2018/10/21
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Barry Rodewald,
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@@ -1009,8 +1009,13 @@ gd54xx_write(uint32_t addr, uint8_t val, void *p)
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{
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gd54xx_t *gd54xx = (gd54xx_t *)p;
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svga_t *svga = &gd54xx->svga;
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if (gd54xx->blt.sys_tx) {
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if ((svga->seqregs[0x07] & 0x01) == 0) {
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svga_write(addr, val, svga);
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return;
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}
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if (gd54xx->blt.sys_tx) {
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if (gd54xx->blt.mode == CIRRUS_BLTMODE_MEMSYSSRC) {
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gd54xx->blt.sys_buf &= ~(0xff << (gd54xx->blt.sys_cnt * 8));
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gd54xx->blt.sys_buf |= (val << (gd54xx->blt.sys_cnt * 8));
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@@ -1021,7 +1026,7 @@ gd54xx_write(uint32_t addr, uint8_t val, void *p)
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}
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}
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return;
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}
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}
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addr &= svga->banked_mask;
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addr = (addr & 0x7fff) + gd54xx->bank[(addr >> 15) & 1];
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@@ -1035,14 +1040,18 @@ gd54xx_writew(uint32_t addr, uint16_t val, void *p)
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{
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gd54xx_t *gd54xx = (gd54xx_t *)p;
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svga_t *svga = &gd54xx->svga;
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if (gd54xx->blt.sys_tx)
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{
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gd54xx_write(addr, val, gd54xx);
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gd54xx_write(addr+1, val >> 8, gd54xx);
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return;
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}
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if ((svga->seqregs[0x07] & 0x01) == 0) {
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svga_writew(addr, val, svga);
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return;
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}
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if (gd54xx->blt.sys_tx) {
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gd54xx_write(addr, val, gd54xx);
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gd54xx_write(addr+1, val >> 8, gd54xx);
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return;
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}
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addr &= svga->banked_mask;
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addr = (addr & 0x7fff) + gd54xx->bank[(addr >> 15) & 1];
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@@ -1061,14 +1070,18 @@ gd54xx_writel(uint32_t addr, uint32_t val, void *p)
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gd54xx_t *gd54xx = (gd54xx_t *)p;
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svga_t *svga = &gd54xx->svga;
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if (gd54xx->blt.sys_tx)
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{
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gd54xx_write(addr, val, gd54xx);
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gd54xx_write(addr+1, val >> 8, gd54xx);
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gd54xx_write(addr+2, val >> 16, gd54xx);
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gd54xx_write(addr+3, val >> 24, gd54xx);
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return;
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}
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if ((svga->seqregs[0x07] & 0x01) == 0) {
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svga_writel(addr, val, svga);
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return;
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}
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if (gd54xx->blt.sys_tx) {
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gd54xx_write(addr, val, gd54xx);
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gd54xx_write(addr+1, val >> 8, gd54xx);
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gd54xx_write(addr+2, val >> 16, gd54xx);
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gd54xx_write(addr+3, val >> 24, gd54xx);
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return;
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}
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addr &= svga->banked_mask;
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addr = (addr & 0x7fff) + gd54xx->bank[(addr >> 15) & 1];
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@@ -1525,6 +1538,10 @@ gd54xx_read(uint32_t addr, void *p)
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{
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gd54xx_t *gd54xx = (gd54xx_t *)p;
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svga_t *svga = &gd54xx->svga;
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if ((svga->seqregs[0x07] & 0x01) == 0)
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return svga_read(addr, svga);
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addr &= svga->banked_mask;
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addr = (addr & 0x7fff) + gd54xx->bank[(addr >> 15) & 1];
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return svga_read_linear(addr, svga);
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@@ -1537,6 +1554,9 @@ gd54xx_readw(uint32_t addr, void *p)
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gd54xx_t *gd54xx = (gd54xx_t *)p;
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svga_t *svga = &gd54xx->svga;
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if ((svga->seqregs[0x07] & 0x01) == 0)
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return svga_readw(addr, svga);
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addr &= svga->banked_mask;
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addr = (addr & 0x7fff) + gd54xx->bank[(addr >> 15) & 1];
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return svga_readw_linear(addr, svga);
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@@ -1549,6 +1569,9 @@ gd54xx_readl(uint32_t addr, void *p)
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gd54xx_t *gd54xx = (gd54xx_t *)p;
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svga_t *svga = &gd54xx->svga;
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if ((svga->seqregs[0x07] & 0x01) == 0)
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return svga_readl(addr, svga);
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addr &= svga->banked_mask;
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addr = (addr & 0x7fff) + gd54xx->bank[(addr >> 15) & 1];
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return svga_readl_linear(addr, svga);
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@@ -11,7 +11,7 @@
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* This is intended to be used by another SVGA driver,
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* and not as a card in it's own right.
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*
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* Version: @(#)vid_svga.c 1.0.34 2018/10/07
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* Version: @(#)vid_svga.c 1.0.35 2018/10/21
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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@@ -829,6 +829,7 @@ svga_write_common(uint32_t addr, uint8_t val, uint8_t linear, void *p)
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svga_t *svga = (svga_t *)p;
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int func_select, writemask2 = svga->writemask;
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int memory_map_mode;
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uint32_t write_mask, bit_mask, set_mask, val32 = (uint32_t) val;
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egawrites++;
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@@ -836,8 +837,30 @@ svga_write_common(uint32_t addr, uint8_t val, uint8_t linear, void *p)
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cycles -= video_timing_write_b;
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if (!linear) {
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addr &= svga->banked_mask;
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addr += svga->write_bank;
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memory_map_mode = (svga->gdcreg[6] >> 2) & 3;
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addr &= 0x1ffff;
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switch (memory_map_mode) {
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case 0:
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break;
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case 1:
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if (addr >= 0x10000)
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return;
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addr += svga->write_bank;
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break;
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case 2:
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addr -= 0x10000;
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if (addr >= 0x8000)
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return;
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break;
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default:
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case 3:
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addr -= 0x18000;
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if (addr >= 0x8000)
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return;
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break;
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}
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}
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if (!(svga->gdcreg[6] & 1))
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@@ -962,16 +985,37 @@ svga_read_common(uint32_t addr, uint8_t linear, void *p)
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{
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svga_t *svga = (svga_t *)p;
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uint32_t latch_addr = 0, ret;
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int readplane = svga->readplane;
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uint8_t ret8;
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int memory_map_mode, readplane = svga->readplane;
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cycles -= video_timing_read_b;
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egareads++;
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if (!linear) {
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addr &= svga->banked_mask;
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addr += svga->read_bank;
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memory_map_mode = (svga->gdcreg[6] >> 2) & 3;
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addr &= 0x1ffff;
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switch(memory_map_mode) {
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case 0:
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break;
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case 1:
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if (addr >= 0x10000)
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return 0xff;
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addr += svga->read_bank;
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break;
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case 2:
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addr -= 0x10000;
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if (addr >= 0x8000)
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return 0xff;
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break;
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default:
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case 3:
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addr -= 0x18000;
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if (addr >= 0x8000)
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return 0xff;
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break;
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}
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latch_addr = (addr << 2) & svga->decode_mask;
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}
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@@ -985,6 +1029,12 @@ svga_read_common(uint32_t addr, uint8_t linear, void *p)
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readplane = (readplane & 2) | (addr & 1);
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addr &= ~1;
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addr <<= 2;
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addr |= readplane;
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addr &= svga->decode_mask;
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if (addr >= svga->vram_max)
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return 0xff;
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addr &= svga->vram_mask;
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return svga->vram[addr];
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} else
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addr <<= 2;
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@@ -1014,15 +1064,14 @@ svga_read_common(uint32_t addr, uint8_t linear, void *p)
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if (!(svga->gdcreg[5] & 8)) {
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/* read mode 0 */
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return svga->vram[addr | readplane];
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return (svga->latch >> (readplane * 8)) & 0xff;
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} else {
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/* read mode 1 */
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ret = (svga->latch ^ mask16[svga->colourcompare & 0x0f]) & mask16[svga->colournocare & 0x0f];
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ret8 = (ret & 0xff);
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ret8 |= ((ret >> 24) & 0xff);
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ret8 |= ((ret >> 16) & 0xff);
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ret8 |= ((ret >> 8) & 0xff);
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return(~ret8);
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ret |= ret >> 16;
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ret |= ret >> 8;
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ret = (~ret) & 0xff;
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return(ret);
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}
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}
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