From 51ef58ad00cb27920289b92af8aa2b43ade57a46 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 19 Jun 2017 22:18:35 +0200 Subject: [PATCH 1/3] Fixed RTL8029AS PCI register write handlers; Disabled the Nation Semiconductors PC87306's IDE handler, the board replaces it with the PCI IDE device anyway; The Commodore PC 300 now remaps the top 384k of RAM; The network card is now initialized after the SCSI controller; The graphics cards remain on the INTA pin, but the network card is now on INTC, and the SCSI controller on INTB; S3 Vision/Trio emulation brought completely in line with mainline PCem, fixes Windows 2000 freezes. --- src/NETWORK/net_ne2000.c | 36 ++-- src/VIDEO/vid_s3.c | 403 ++++++++++++++++----------------------- src/model.c | 51 ++--- src/pc.c | 2 +- src/pc87306.c | 4 + src/scsi_buslogic.c | 6 +- 6 files changed, 228 insertions(+), 274 deletions(-) diff --git a/src/NETWORK/net_ne2000.c b/src/NETWORK/net_ne2000.c index 026e72619..d98fdf019 100644 --- a/src/NETWORK/net_ne2000.c +++ b/src/NETWORK/net_ne2000.c @@ -245,9 +245,9 @@ nic_interrupt(nic_t *dev, int set) { if (PCI && dev->is_pci) { if (set) - pci_set_irq(dev->card, PCI_INTA); + pci_set_irq(dev->card, PCI_INTC); else - pci_clear_irq(dev->card, PCI_INTA); + pci_clear_irq(dev->card, PCI_INTC); } else { if (set) picint(1<base_irq); @@ -1485,6 +1485,7 @@ nic_pci_read(int func, int addr, void *priv) ret = dev->pci_regs[addr]; break; +#if 0 case 0x0C: /* (reserved) */ ret = dev->pci_regs[addr]; break; @@ -1497,6 +1498,7 @@ nic_pci_read(int func, int addr, void *priv) case 0x0F: /* (reserved) */ ret = dev->pci_regs[addr]; break; +#endif case 0x10: /* PCI_BAR 7:5 */ ret = (dev->pci_bar[0].addr_regs[1] & 0xe0) | 0x01; @@ -1553,23 +1555,30 @@ static void nic_pci_write(int func, int addr, uint8_t val, void *priv) { nic_t *dev = (nic_t *)priv; + uint8_t valxor; nelog(2, "%s: PCI_Write(%d, %04x, %02x)\n", dev->name, func, addr, val); switch(addr) { case 0x04: /* PCI_COMMAND_LO */ - val &= 0x03; - nic_ioremove(dev, dev->base_address); - if (val & PCI_COMMAND_IO) - nic_ioset(dev, dev->base_address); + valxor = (val & 0x23) ^ dev->pci_regs[addr]; + if (valxor & PCI_COMMAND_IO) + { + nic_ioremove(dev, dev->base_address); + if ((dev->base_address != 0) && (val & PCI_COMMAND_IO)) + { + nic_ioset(dev, dev->base_address); + } + } #if 0 if (val & PCI_COMMAND_MEMORY) { ... } #endif - dev->pci_regs[addr] = val; + dev->pci_regs[addr] = val & 0x23; break; +#if 0 case 0x0C: /* (reserved) */ dev->pci_regs[addr] = val; break; @@ -1585,6 +1594,7 @@ nic_pci_write(int func, int addr, uint8_t val, void *priv) case 0x0F: /* (reserved) */ dev->pci_regs[addr] = val; break; +#endif case 0x10: /* PCI_BAR */ val &= 0xfc; /* 0xe0 acc to RTL DS */ @@ -1607,8 +1617,13 @@ nic_pci_write(int func, int addr, uint8_t val, void *priv) nelog(1, "%s: PCI: new I/O base is %04X\n", dev->name, dev->base_address); /* We're done, so get out of the here. */ - if (val & PCI_COMMAND_IO) - nic_ioset(dev, dev->base_address); + if (dev->pci_regs[4] & PCI_COMMAND_IO) + { + if (dev->base_address != 0) + { + nic_ioset(dev, dev->base_address); + } + } break; case 0x30: /* PCI_ROMBAR */ @@ -1938,8 +1953,7 @@ nic_init(int board) dev->pci_regs[0x2E] = (PCI_DEVID&0xff); dev->pci_regs[0x2F] = (PCI_DEVID>>8); - dev->pci_regs[0x3C] = dev->base_irq; /* PCI_ILR */ - dev->pci_regs[0x3D] = 0x01; /* PCI_IPR */ + dev->pci_regs[0x3D] = PCI_INTC; /* PCI_IPR */ /* Enable our address space in PCI. */ dev->pci_bar[0].addr_regs[0] = 0x01; diff --git a/src/VIDEO/vid_s3.c b/src/VIDEO/vid_s3.c index 61a24ce64..6cc18d7e9 100644 --- a/src/VIDEO/vid_s3.c +++ b/src/VIDEO/vid_s3.c @@ -1,36 +1,18 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Emulation of the S3 Trio32, S3 Trio64, and S3 Vision864 - * graphics cards. - * - * Version: @(#)vid_s3.c 1.0.1 2017/06/04 - * - * Authors: Sarah Walker, - * Miran Grca, - * Copyright 2008-2017 Sarah Walker. - * Copyright 2016-2017 Miran Grca. - */ +/*S3 emulation*/ #include #include "../ibm.h" +#include "../device.h" #include "../io.h" #include "../mem.h" #include "../pci.h" #include "../rom.h" -#include "../device.h" -#include "../win/plat_thread.h" +#include "../WIN/plat_thread.h" #include "video.h" #include "vid_s3.h" #include "vid_svga.h" #include "vid_svga_render.h" #include "vid_sdac_ramdac.h" - enum { S3_VISION864, @@ -93,15 +75,15 @@ typedef struct s3_t int chip; uint8_t id, id_ext, id_ext_pci; - - uint8_t int_line; + + uint8_t int_line; int packed_mmio; uint32_t linear_base, linear_size; uint8_t pci_regs[256]; - int card; + int card; uint32_t vram_mask; @@ -152,9 +134,8 @@ typedef struct s3_t int blitter_busy; uint64_t blitter_time; uint64_t status_time; - - uint8_t subsys_cntl, subsys_stat; - uint8_t status_9ae9; + + uint8_t subsys_cntl, subsys_stat; } s3_t; #define INT_VSY (1 << 0) @@ -170,7 +151,7 @@ void s3_accel_write_w(uint32_t addr, uint16_t val, void *p); void s3_accel_write_l(uint32_t addr, uint32_t val, void *p); uint8_t s3_accel_read(uint32_t addr, void *p); -static __inline void wake_fifo_thread(s3_t *s3) +static inline void wake_fifo_thread(s3_t *s3) { thread_set_event(s3->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/ } @@ -186,11 +167,6 @@ static void s3_wait_fifo_idle(s3_t *s3) static void s3_update_irqs(s3_t *s3) { - if (!PCI) - { - return; - } - if (s3->subsys_cntl & s3->subsys_stat & INT_MASK) pci_set_irq(s3->card, PCI_INTA); else @@ -444,88 +420,70 @@ static void s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val) static void s3_accel_out_fifo_w(s3_t *s3, uint16_t port, uint16_t val) { - if (port & 0x8000) - { - s3_accel_out_fifo(s3, port, val); - s3_accel_out_fifo(s3, port + 1, val >> 8); - } - else - { - if (s3->accel.cmd & 0x100) - { - if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80) - { - if (s3->accel.cmd & 0x1000) - val = (val >> 8) | (val << 8); - if ((s3->accel.cmd & 0x600) == 0x000) - s3_accel_start(8, 1, val | (val << 16), 0, s3); - else - s3_accel_start(16, 1, val | (val << 16), 0, s3); - } - else - { - if ((s3->accel.cmd & 0x600) == 0x000) - s3_accel_start(1, 1, 0xffffffff, val | (val << 16), s3); - else - s3_accel_start(2, 1, 0xffffffff, val | (val << 16), s3); - } - } - } + if (s3->accel.cmd & 0x100) + { + if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80) + { + if (s3->accel.cmd & 0x1000) + val = (val >> 8) | (val << 8); + if ((s3->accel.cmd & 0x600) == 0x000) + s3_accel_start(8, 1, val | (val << 16), 0, s3); + else + s3_accel_start(16, 1, val | (val << 16), 0, s3); + } + else + { + if ((s3->accel.cmd & 0x600) == 0x000) + s3_accel_start(1, 1, 0xffffffff, val | (val << 16), s3); + else + s3_accel_start(2, 1, 0xffffffff, val | (val << 16), s3); + } + } } static void s3_accel_out_fifo_l(s3_t *s3, uint16_t port, uint32_t val) { - if (port & 0x8000) - { - s3_accel_out_fifo(s3, port, val); - s3_accel_out_fifo(s3, port + 1, val >> 8); - s3_accel_out_fifo(s3, port + 2, val >> 16); - s3_accel_out_fifo(s3, port + 3, val >> 24); - } - else - { - if (s3->accel.cmd & 0x100) - { - if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80) - { - if (s3->accel.cmd & 0x400) - { - if (s3->accel.cmd & 0x1000) - val = ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24); - s3_accel_start(32, 1, val, 0, s3); - } - else if ((s3->accel.cmd & 0x600) == 0x200) - { - if (s3->accel.cmd & 0x1000) - val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8); - s3_accel_start(16, 1, val, 0, s3); - s3_accel_start(16, 1, val >> 16, 0, s3); - } - else - { - if (s3->accel.cmd & 0x1000) - val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8); - s3_accel_start(8, 1, val, 0, s3); - s3_accel_start(8, 1, val >> 16, 0, s3); - } - } - else - { - if (s3->accel.cmd & 0x400) - s3_accel_start(4, 1, 0xffffffff, val, s3); - else if ((s3->accel.cmd & 0x600) == 0x200) - { - s3_accel_start(2, 1, 0xffffffff, val, s3); - s3_accel_start(2, 1, 0xffffffff, val >> 16, s3); - } - else - { - s3_accel_start(1, 1, 0xffffffff, val, s3); - s3_accel_start(1, 1, 0xffffffff, val >> 16, s3); - } - } - } - } + if (s3->accel.cmd & 0x100) + { + if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80) + { + if (s3->accel.cmd & 0x400) + { + if (s3->accel.cmd & 0x1000) + val = ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24); + s3_accel_start(32, 1, val, 0, s3); + } + else if ((s3->accel.cmd & 0x600) == 0x200) + { + if (s3->accel.cmd & 0x1000) + val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8); + s3_accel_start(16, 1, val, 0, s3); + s3_accel_start(16, 1, val >> 16, 0, s3); + } + else + { + if (s3->accel.cmd & 0x1000) + val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8); + s3_accel_start(8, 1, val, 0, s3); + s3_accel_start(8, 1, val >> 16, 0, s3); + } + } + else + { + if (s3->accel.cmd & 0x400) + s3_accel_start(4, 1, 0xffffffff, val, s3); + else if ((s3->accel.cmd & 0x600) == 0x200) + { + s3_accel_start(2, 1, 0xffffffff, val, s3); + s3_accel_start(2, 1, 0xffffffff, val >> 16, s3); + } + else + { + s3_accel_start(1, 1, 0xffffffff, val, s3); + s3_accel_start(1, 1, 0xffffffff, val >> 16, s3); + } + } + } } static void s3_accel_write_fifo(s3_t *s3, uint32_t addr, uint8_t val) @@ -635,88 +593,88 @@ static void s3_accel_write_fifo(s3_t *s3, uint32_t addr, uint8_t val) static void s3_accel_write_fifo_w(s3_t *s3, uint32_t addr, uint16_t val) { - if (addr & 0x8000) - { - s3_accel_write_fifo(s3, addr, val); - s3_accel_write_fifo(s3, addr + 1, val >> 8); - } - else - { - if (s3->accel.cmd & 0x100) - { - if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80) - { - if (s3->accel.cmd & 0x1000) - val = (val >> 8) | (val << 8); - if ((s3->accel.cmd & 0x600) == 0x000) - s3_accel_start(8, 1, val | (val << 16), 0, s3); - else - s3_accel_start(16, 1, val | (val << 16), 0, s3); - } - else - { - if ((s3->accel.cmd & 0x600) == 0x000) - s3_accel_start(1, 1, 0xffffffff, val | (val << 16), s3); - else - s3_accel_start(2, 1, 0xffffffff, val | (val << 16), s3); - } - } - } + if (addr & 0x8000) + { + s3_accel_write_fifo(s3, addr, val); + s3_accel_write_fifo(s3, addr + 1, val >> 8); + } + else + { + if (s3->accel.cmd & 0x100) + { + if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80) + { + if (s3->accel.cmd & 0x1000) + val = (val >> 8) | (val << 8); + if ((s3->accel.cmd & 0x600) == 0x000) + s3_accel_start(8, 1, val | (val << 16), 0, s3); + else + s3_accel_start(16, 1, val | (val << 16), 0, s3); + } + else + { + if ((s3->accel.cmd & 0x600) == 0x000) + s3_accel_start(1, 1, 0xffffffff, val | (val << 16), s3); + else + s3_accel_start(2, 1, 0xffffffff, val | (val << 16), s3); + } + } + } } static void s3_accel_write_fifo_l(s3_t *s3, uint32_t addr, uint32_t val) { - if (addr & 0x8000) - { - s3_accel_write_fifo(s3, addr, val); - s3_accel_write_fifo(s3, addr + 1, val >> 8); - s3_accel_write_fifo(s3, addr + 2, val >> 16); - s3_accel_write_fifo(s3, addr + 3, val >> 24); - } - else - { - if (s3->accel.cmd & 0x100) - { - if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80) - { - if (s3->accel.cmd & 0x400) - { - if (s3->accel.cmd & 0x1000) - val = ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24); - s3_accel_start(32, 1, val, 0, s3); - } - else if ((s3->accel.cmd & 0x600) == 0x200) - { - if (s3->accel.cmd & 0x1000) - val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8); - s3_accel_start(16, 1, val, 0, s3); - s3_accel_start(16, 1, val >> 16, 0, s3); - } - else - { - if (s3->accel.cmd & 0x1000) - val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8); - s3_accel_start(8, 1, val, 0, s3); - s3_accel_start(8, 1, val >> 16, 0, s3); - } - } - else - { - if (s3->accel.cmd & 0x400) - s3_accel_start(4, 1, 0xffffffff, val, s3); - else if ((s3->accel.cmd & 0x600) == 0x200) - { - s3_accel_start(2, 1, 0xffffffff, val, s3); - s3_accel_start(2, 1, 0xffffffff, val >> 16, s3); - } - else - { - s3_accel_start(1, 1, 0xffffffff, val, s3); - s3_accel_start(1, 1, 0xffffffff, val >> 16, s3); - } - } - } - } + if (addr & 0x8000) + { + s3_accel_write_fifo(s3, addr, val); + s3_accel_write_fifo(s3, addr + 1, val >> 8); + s3_accel_write_fifo(s3, addr + 2, val >> 16); + s3_accel_write_fifo(s3, addr + 3, val >> 24); + } + else + { + if (s3->accel.cmd & 0x100) + { + if ((s3->accel.multifunc[0xa] & 0xc0) == 0x80) + { + if (s3->accel.cmd & 0x400) + { + if (s3->accel.cmd & 0x1000) + val = ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24); + s3_accel_start(32, 1, val, 0, s3); + } + else if ((s3->accel.cmd & 0x600) == 0x200) + { + if (s3->accel.cmd & 0x1000) + val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8); + s3_accel_start(16, 1, val, 0, s3); + s3_accel_start(16, 1, val >> 16, 0, s3); + } + else + { + if (s3->accel.cmd & 0x1000) + val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8); + s3_accel_start(8, 1, val, 0, s3); + s3_accel_start(8, 1, val >> 16, 0, s3); + } + } + else + { + if (s3->accel.cmd & 0x400) + s3_accel_start(4, 1, 0xffffffff, val, s3); + else if ((s3->accel.cmd & 0x600) == 0x200) + { + s3_accel_start(2, 1, 0xffffffff, val, s3); + s3_accel_start(2, 1, 0xffffffff, val >> 16, s3); + } + else + { + s3_accel_start(1, 1, 0xffffffff, val, s3); + s3_accel_start(1, 1, 0xffffffff, val >> 16, s3); + } + } + } + } } static void fifo_thread(void *param) @@ -834,14 +792,7 @@ void s3_out(uint16_t addr, uint8_t val, void *p) break; case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9: - if (s3->chip < S3_TRIO32) - { - sdac_ramdac_out(addr, val, &s3->ramdac, svga); - } - else - { - svga_out(addr, val, svga); - } + sdac_ramdac_out(addr, val, &s3->ramdac, svga); return; case 0x3D4: @@ -922,7 +873,7 @@ void s3_out(uint16_t addr, uint8_t val, void *p) svga->hwcursor.xoff = svga->crtc[0x4e] & 63; svga->hwcursor.yoff = svga->crtc[0x4f] & 63; svga->hwcursor.addr = ((((svga->crtc[0x4c] << 8) | svga->crtc[0x4d]) & 0xfff) * 1024) + (svga->hwcursor.yoff * 16); - if ((s3->chip == S3_TRIO32 || s3->chip == S3_TRIO64) && (svga->bpp == 32) && (s3->id == 0xe1)) + if ((s3->chip == S3_TRIO32 || s3->chip == S3_TRIO64) && svga->bpp == 32) svga->hwcursor.x <<= 1; break; @@ -979,14 +930,7 @@ uint8_t s3_in(uint16_t addr, void *p) break; case 0x3c6: case 0x3c7: case 0x3c8: case 0x3c9: - if (s3->chip < S3_TRIO32) - { - return sdac_ramdac_in(addr, &s3->ramdac, svga); - } - else - { - return svga_in(addr, svga); - } + return sdac_ramdac_in(addr, &s3->ramdac, svga); case 0x3d4: return svga->crtcreg; @@ -1002,10 +946,6 @@ uint8_t s3_in(uint16_t addr, void *p) case 0x51: return (svga->crtc[0x51] & 0xf0) | ((s3->bank >> 2) & 0xc) | ((s3->ma_ext >> 2) & 3); case 0x69: return s3->ma_ext; case 0x6a: return s3->bank; - case 0x6b: - pclog("Returning value: %02X\n", svga->crtc[0x6b]); - return 0xff; - break; } return svga->crtc[svga->crtcreg]; } @@ -1074,7 +1014,7 @@ void s3_recalctimings(svga_t *svga) void s3_updatemapping(s3_t *s3) { svga_t *svga = &s3->svga; - + if (!(s3->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) { mem_mapping_disable(&svga->mapping); @@ -1129,7 +1069,6 @@ void s3_updatemapping(s3_t *s3) break; } s3->linear_base &= ~(s3->linear_size - 1); - svga->linear_base = s3->linear_base; if (s3->linear_base == 0xa0000) { mem_mapping_disable(&s3->linear_mapping); @@ -1144,7 +1083,7 @@ void s3_updatemapping(s3_t *s3) } else mem_mapping_disable(&s3->linear_mapping); - + if (svga->crtc[0x53] & 0x10) /*Memory mapped IO*/ { mem_mapping_disable(&svga->mapping); @@ -1173,7 +1112,7 @@ static float s3_trio64_getclock(int clock, void *p) void s3_accel_out(uint16_t port, uint8_t val, void *p) { s3_t *s3 = (s3_t *)p; - + if (port >= 0x8000) { s3_queue(s3, port, val, FIFO_OUT_BYTE); @@ -1275,7 +1214,7 @@ uint8_t s3_accel_in(uint16_t port, void *p) if (!FIFO_EMPTY) temp |= 0x02; /*Hardware busy*/ else - temp |= s3->status_9ae9; /*FIFO empty*/ + temp |= 0x04; /*FIFO empty*/ if (FIFO_FULL) temp |= 0xf8; /*FIFO full*/ return temp; @@ -1998,8 +1937,6 @@ void s3_hwcursor_draw(svga_t *svga, int displine) uint16_t dat[2]; int xx; int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff; - int y_add = (enable_overscan && !suppress_overscan) ? 16 : 0; - int x_add = (enable_overscan && !suppress_overscan) ? 8 : 0; if (svga->interlace && svga->hwcursor_oddeven) svga->hwcursor_latch.addr += 16; @@ -2013,9 +1950,9 @@ void s3_hwcursor_draw(svga_t *svga, int displine) if (offset >= svga->hwcursor_latch.x) { if (!(dat[0] & 0x8000)) - ((uint32_t *)buffer32->line[displine + y_add])[offset + 32 + x_add] = (dat[1] & 0x8000) ? 0xffffff : 0; + ((uint32_t *)buffer32->line[displine])[offset + 32] = (dat[1] & 0x8000) ? 0xffffff : 0; else if (dat[1] & 0x8000) - ((uint32_t *)buffer32->line[displine + y_add])[offset + 32 + x_add] ^= 0xffffff; + ((uint32_t *)buffer32->line[displine])[offset + 32] ^= 0xffffff; } offset++; @@ -2088,7 +2025,6 @@ uint8_t s3_pci_read(int func, int addr, void *p) { s3_t *s3 = (s3_t *)p; svga_t *svga = &s3->svga; - /* pclog("S3 PCI read %08X\n", addr); */ switch (addr) { case 0x00: return 0x33; /*'S3'*/ @@ -2128,7 +2064,6 @@ void s3_pci_write(int func, int addr, uint8_t val, void *p) { s3_t *s3 = (s3_t *)p; svga_t *svga = &s3->svga; - /* pclog("s3_pci_write: addr=%02x val=%02x\n", addr, val); */ switch (addr) { case PCI_REG_COMMAND: @@ -2187,9 +2122,9 @@ static void *s3_init(wchar_t *bios_fn, int chip) svga_t *svga = &s3->svga; int vram; uint32_t vram_size; - + memset(s3, 0, sizeof(s3_t)); - + vram = device_get_config_int("memory"); if (vram) vram_size = vram << 20; @@ -2216,20 +2151,14 @@ static void *s3_init(wchar_t *bios_fn, int chip) else svga->crtc[0x36] = 1 | (3 << 2) | (1 << 4) | (vram_sizes[vram] << 5); svga->crtc[0x37] = 1 | (7 << 5); - - svga->vblank_start = s3_vblank_start; - - svga->crtc[0x53] = 1 << 3; - svga->crtc[0x59] = 0x70; + + svga->vblank_start = s3_vblank_start; s3_io_set(s3); - if (PCI) - { - s3->card = pci_add(s3_pci_read, s3_pci_write, s3); - } - - s3->pci_regs[0x04] = 3; + s3->card = pci_add(s3_pci_read, s3_pci_write, s3); + + s3->pci_regs[0x04] = 7; s3->pci_regs[0x30] = 0x00; s3->pci_regs[0x32] = 0x0c; @@ -2240,8 +2169,8 @@ static void *s3_init(wchar_t *bios_fn, int chip) s3->wake_fifo_thread = thread_create_event(); s3->fifo_not_full_event = thread_create_event(); s3->fifo_thread = thread_create(fifo_thread, s3); - - s3->int_line = 0; + + s3->int_line = 0; return s3; } @@ -2341,7 +2270,7 @@ int s3_9fx_available() int s3_phoenix_trio64_available() { - return rom_present(L"roms/86C764X1.bin"); + return rom_present(L"roms/86c764x1.bin"); } int s3_diamond_stealth64_available() diff --git a/src/model.c b/src/model.c index 776c99cff..8f76c06fb 100644 --- a/src/model.c +++ b/src/model.c @@ -88,6 +88,7 @@ extern void olim24_init(void); extern void at_init(void); extern void ibm_at_init(void); extern void at_ide_init(void); +extern void cmdpc30_init(void); extern void deskpro386_init(void); extern void ps1_m2011_init(void); extern void ps1_m2121_init(void); @@ -163,7 +164,7 @@ MODEL models[] = {"IBM AT", ROM_IBMAT, "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 256,15872, 128, 63, ibm_at_init, NULL}, {"Compaq Portable II", ROM_PORTABLEII, "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL}, {"Compaq Portable III", ROM_PORTABLEIII, "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL}, - {"Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 640,16384, 128, 127, at_ide_init, NULL}, + {"Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 640,16384, 128, 127, cmdpc30_init, NULL}, {"AMI 286 clone", ROM_AMI286, "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_neat_init, NULL}, {"Award 286 clone", ROM_AWARD286, "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL}, {"Hyundai Super-286TR", ROM_SUPER286TR, "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL}, @@ -432,6 +433,12 @@ void at_ide_init(void) ide_init(); } +void cmdpc30_init(void) +{ + at_ide_init(); + mem_remap_top_384k(); +} + void deskpro386_init(void) { at_init(); @@ -697,10 +704,10 @@ void at_mb500n_init(void) { at_ide_init(); pci_init(PCI_CONFIG_TYPE_1); - pci_slot(0x11); - pci_slot(0x12); - pci_slot(0x13); pci_slot(0x14); + pci_slot(0x13); + pci_slot(0x12); + pci_slot(0x11); i430fx_init(); piix_init(7, 0x14, 0x13, 0x12, 0x11); fdc37c665_init(); @@ -730,10 +737,10 @@ void at_p54tp4xe_init(void) at_ide_init(); memregs_init(); pci_init(PCI_CONFIG_TYPE_1); - pci_slot(9); - pci_slot(10); - pci_slot(11); pci_slot(12); + pci_slot(11); + pci_slot(10); + pci_slot(9); i430fx_init(); piix_init(7, 12, 11, 10, 9); fdc37c665_init(); @@ -763,12 +770,12 @@ void at_p55t2s_init(void) memregs_init(); powermate_memregs_init(); pci_init(PCI_CONFIG_TYPE_1); - pci_slot(0x11); pci_slot(0x12); - pci_slot(0x13); + pci_slot(0x11); pci_slot(0x14); + pci_slot(0x13); i430hx_init(); - piix_init(7, 0x12, 0x13, 0x14, 0x11); + piix_init(7, 0x12, 0x11, 0x14, 0x13); pc87306_init(); acerm3a_io_init(); device_add(&intel_flash_bxt_device); @@ -813,10 +820,10 @@ void at_p55t2p4_init(void) at_ide_init(); memregs_init(); pci_init(PCI_CONFIG_TYPE_1); - pci_slot(9); - pci_slot(10); - pci_slot(11); pci_slot(12); + pci_slot(11); + pci_slot(10); + pci_slot(9); i430hx_init(); piix3_init(7, 12, 11, 10, 9); w83877f_init(); @@ -845,10 +852,10 @@ void at_p55tvp4_init(void) at_ide_init(); memregs_init(); pci_init(PCI_CONFIG_TYPE_1); - pci_slot(9); - pci_slot(10); - pci_slot(11); pci_slot(12); + pci_slot(11); + pci_slot(10); + pci_slot(9); i430vx_init(); piix3_init(7, 12, 11, 10, 9); w83877f_init(); @@ -875,10 +882,10 @@ void at_i440fx_init(void) at_ide_init(); memregs_init(); pci_init(PCI_CONFIG_TYPE_1); - pci_slot(0xb); - pci_slot(0xc); - pci_slot(0xd); pci_slot(0xe); + pci_slot(0xd); + pci_slot(0xc); + pci_slot(0xb); i430vx_init(); piix3_init(7, 0xe, 0xd, 0xc, 0xb); fdc37c665_init(); @@ -890,10 +897,10 @@ void at_s1668_init(void) at_ide_init(); memregs_init(); pci_init(PCI_CONFIG_TYPE_1); - pci_slot(0xb); - pci_slot(0xc); - pci_slot(0xd); pci_slot(0xe); + pci_slot(0xd); + pci_slot(0xc); + pci_slot(0xb); i440fx_init(); piix3_init(7, 0xe, 0xd, 0xc, 0xb); fdc37c665_init(); diff --git a/src/pc.c b/src/pc.c index 3bdeabc71..64a85f616 100644 --- a/src/pc.c +++ b/src/pc.c @@ -502,7 +502,6 @@ void resetpchard_init(void) model_init(); video_init(); speaker_init(); - network_reset(); ide_ter_disable(); ide_qua_disable(); @@ -519,6 +518,7 @@ void resetpchard_init(void) resetide(); scsi_card_init(); + network_reset(); sound_card_init(); if (mpu401_standalone_enable) diff --git a/src/pc87306.c b/src/pc87306.c index c0887451b..b67aa5071 100644 --- a/src/pc87306.c +++ b/src/pc87306.c @@ -154,7 +154,9 @@ void pc87306_write(uint16_t port, uint8_t val, void *priv) { uint8_t index; uint8_t valxor; +#if 0 uint16_t or_value; +#endif index = (port & 1) ? 0 : 1; @@ -239,6 +241,7 @@ process_value: } if (valxor & 0xc0) { +#if 0 ide_pri_disable(); if (val & 0x80) { @@ -254,6 +257,7 @@ process_value: { ide_pri_enable_ex(); } +#endif } break; diff --git a/src/scsi_buslogic.c b/src/scsi_buslogic.c index cfc1188c2..2da990ee4 100644 --- a/src/scsi_buslogic.c +++ b/src/scsi_buslogic.c @@ -533,11 +533,11 @@ BuslogicInterrupt(Buslogic_t *bl, int set) { if (set) { - pci_set_irq(bl->Card, PCI_INTA); + pci_set_irq(bl->Card, PCI_INTB); } else { - pci_clear_irq(bl->Card, PCI_INTA); + pci_clear_irq(bl->Card, PCI_INTB); } } else @@ -2116,7 +2116,7 @@ BuslogicPCIRead(int func, int addr, void *p) case 0x3C: return bl->Irq; case 0x3D: - return PCI_INTA; + return PCI_INTB; } return(0); From ca53dd028075fcdbb46936cd8f04ff4e51f2e9e4 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Mon, 19 Jun 2017 22:32:16 +0200 Subject: [PATCH 2/3] S3 Trio/Vision changes (again x2): Trio32/64 with on-chip ramdac instead of SDAC. FIFO Empty/Full status from 9ae8/9ae9 no longer slowing down OS/2 when native drivers are installed. --- src/VIDEO/vid_s3.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/src/VIDEO/vid_s3.c b/src/VIDEO/vid_s3.c index 6cc18d7e9..3401ecd03 100644 --- a/src/VIDEO/vid_s3.c +++ b/src/VIDEO/vid_s3.c @@ -86,6 +86,7 @@ typedef struct s3_t int card; uint32_t vram_mask; + uint8_t status_9ae8; float (*getclock)(int clock, void *p); void *getclock_p; @@ -792,7 +793,12 @@ void s3_out(uint16_t addr, uint8_t val, void *p) break; case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9: - sdac_ramdac_out(addr, val, &s3->ramdac, svga); + if (s3->chip < S3_TRIO32) + { + sdac_ramdac_out(addr, val, &s3->ramdac, svga); + return; + } + svga_out(addr, val, svga); return; case 0x3D4: @@ -930,7 +936,10 @@ uint8_t s3_in(uint16_t addr, void *p) break; case 0x3c6: case 0x3c7: case 0x3c8: case 0x3c9: - return sdac_ramdac_in(addr, &s3->ramdac, svga); + if (s3->chip < S3_TRIO32) + return sdac_ramdac_in(addr, &s3->ramdac, svga); + + return svga_in(addr, svga); case 0x3d4: return svga->crtcreg; @@ -1214,7 +1223,7 @@ uint8_t s3_accel_in(uint16_t port, void *p) if (!FIFO_EMPTY) temp |= 0x02; /*Hardware busy*/ else - temp |= 0x04; /*FIFO empty*/ + temp |= s3->status_9ae8; /*FIFO empty*/ if (FIFO_FULL) temp |= 0xf8; /*FIFO full*/ return temp; @@ -1604,6 +1613,14 @@ void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat frgd_mix = (s3->accel.frgd_mix >> 5) & 3; bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3; + s3->status_9ae8 = 4; /*To avoid the spam from OS/2's drivers*/ + + if ((s3->accel.cmd & 0x100) && !cpu_input) + { + s3->status_9ae8 = 2; /*To avoid the spam from OS/2's drivers*/ + return; /*Wait for data from CPU*/ + } + while (count-- && s3->accel.sy >= 0) { if (s3->accel.cx >= clip_l && s3->accel.cx <= clip_r && @@ -1688,7 +1705,8 @@ void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3; if (!cpu_input && frgd_mix == 3 && !vram_mask && !compare_mode && - (s3->accel.cmd & 0xa0) == 0xa0 && (s3->accel.frgd_mix & 0xf) == 7) + (s3->accel.cmd & 0xa0) == 0xa0 && (s3->accel.frgd_mix & 0xf) == 7 && + (s3->accel.bkgd_mix & 0xf) == 7) { while (1) { From 310881dd63be4400aee0f22586d79992599c3a3c Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 19 Jun 2017 22:32:55 +0200 Subject: [PATCH 3/3] S3 Trio32 and Trio64 no longer use the SDAC RAMDAC. --- src/VIDEO/vid_s3.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/VIDEO/vid_s3.c b/src/VIDEO/vid_s3.c index 6cc18d7e9..c9691cf5d 100644 --- a/src/VIDEO/vid_s3.c +++ b/src/VIDEO/vid_s3.c @@ -792,8 +792,15 @@ void s3_out(uint16_t addr, uint8_t val, void *p) break; case 0x3C6: case 0x3C7: case 0x3C8: case 0x3C9: - sdac_ramdac_out(addr, val, &s3->ramdac, svga); - return; + if (s3->chip == S3_VISION864) + { + sdac_ramdac_out(addr, val, &s3->ramdac, svga); + return; + } + else + { + break; + } case 0x3D4: svga->crtcreg = val & 0x7f; @@ -930,7 +937,14 @@ uint8_t s3_in(uint16_t addr, void *p) break; case 0x3c6: case 0x3c7: case 0x3c8: case 0x3c9: - return sdac_ramdac_in(addr, &s3->ramdac, svga); + if (s3->chip == S3_VISION864) + { + return sdac_ramdac_in(addr, &s3->ramdac, svga); + } + else + { + break; + } case 0x3d4: return svga->crtcreg;