IDE fixes and finished the SiS 5511.
This commit is contained in:
@@ -86,6 +86,8 @@ enum {
|
||||
DEVICE_ONBOARD = 0x20000000, /* is on-board */
|
||||
DEVICE_EXTPARAMS = 0x40000000, /* accepts extended parameters */
|
||||
|
||||
DEVICE_PIT = 0x80000000, /* device is a PIT */
|
||||
|
||||
DEVICE_ALL = 0xffffffff /* match all devices */
|
||||
};
|
||||
|
||||
@@ -188,6 +190,7 @@ extern void device_cadd_inst_ex(const device_t *dev, const device_t *cd, void *
|
||||
extern void device_cadd_inst_ex_parameters(const device_t *dev, const device_t *cd, void *priv, int inst, void *params);
|
||||
extern void device_close_all(void);
|
||||
extern void device_reset_all(uint32_t match_flags);
|
||||
extern void *device_find_first_priv(uint32_t match_flags);
|
||||
extern void *device_get_priv(const device_t *dev);
|
||||
extern int device_available(const device_t *dev);
|
||||
extern int device_poll(const device_t *dev);
|
||||
|
||||
@@ -149,8 +149,8 @@ extern uint8_t ide_read_alt_status(uint16_t addr, void *priv);
|
||||
extern uint16_t ide_readw(uint16_t addr, void *priv);
|
||||
|
||||
extern void ide_set_bus_master(int board,
|
||||
int (*dma)(int channel, uint8_t *data, int transfer_length, int out, void *priv),
|
||||
void (*set_irq)(int channel, void *priv), void *priv);
|
||||
int (*dma)(uint8_t *data, int transfer_length, int out, void *priv),
|
||||
void (*set_irq)(uint8_t status, void *priv), void *priv);
|
||||
|
||||
extern void win_cdrom_eject(uint8_t id);
|
||||
extern void win_cdrom_reload(uint8_t id);
|
||||
@@ -180,10 +180,6 @@ extern void ide_set_board_callback(uint8_t board, double callback);
|
||||
extern void ide_padstr(char *str, const char *src, int len);
|
||||
extern void ide_padstr8(uint8_t *buf, int buf_size, const char *src);
|
||||
|
||||
extern int (*ide_bus_master_dma)(int channel, uint8_t *data, int transfer_length, int out, void *priv);
|
||||
extern void (*ide_bus_master_set_irq)(int channel, void *priv);
|
||||
extern void *ide_bus_master_priv[2];
|
||||
|
||||
extern uint8_t ide_read_ali_75(void);
|
||||
extern uint8_t ide_read_ali_76(void);
|
||||
|
||||
|
||||
@@ -20,52 +20,62 @@
|
||||
#ifndef EMU_HDC_IDE_SFF8038I_H
|
||||
#define EMU_HDC_IDE_SFF8038I_H
|
||||
|
||||
typedef struct sff8038i_t {
|
||||
enum
|
||||
{
|
||||
IRQ_MODE_LEGACY = 0,
|
||||
IRQ_MODE_PCI_IRQ_PIN,
|
||||
IRQ_MODE_PCI_IRQ_LINE,
|
||||
IRQ_MODE_ALI_ALADDIN,
|
||||
IRQ_MODE_MIRQ_0,
|
||||
IRQ_MODE_MIRQ_1,
|
||||
IRQ_MODE_MIRQ_2,
|
||||
IRQ_MODE_MIRQ_3,
|
||||
IRQ_MODE_SIS_551X
|
||||
};
|
||||
|
||||
typedef struct sff8038i_t
|
||||
{
|
||||
uint8_t command;
|
||||
uint8_t status;
|
||||
uint8_t ptr0;
|
||||
uint8_t enabled;
|
||||
uint8_t dma_mode;
|
||||
uint8_t irq_state;
|
||||
uint8_t pad;
|
||||
uint8_t pad0;
|
||||
uint8_t channel;
|
||||
uint8_t irq_line;
|
||||
uint16_t base;
|
||||
uint16_t pad1;
|
||||
uint16_t pad;
|
||||
uint32_t ptr;
|
||||
uint32_t ptr_cur;
|
||||
uint32_t addr;
|
||||
int count;
|
||||
int eot;
|
||||
int slot;
|
||||
int irq_mode[2];
|
||||
int irq_level[2];
|
||||
int irq_mode;
|
||||
int irq_level;
|
||||
int irq_pin;
|
||||
int irq_line;
|
||||
int pci_irq_line;
|
||||
} sff8038i_t;
|
||||
|
||||
extern const device_t sff8038i_device;
|
||||
|
||||
extern void sff_bus_master_handler(sff8038i_t *dev, int enabled, uint16_t base);
|
||||
|
||||
extern int sff_bus_master_dma_read(int channel, uint8_t *data, int transfer_length, void *priv);
|
||||
extern int sff_bus_master_dma_write(int channel, uint8_t *data, int transfer_length, void *priv);
|
||||
|
||||
extern void sff_bus_master_set_irq(int channel, void *priv);
|
||||
|
||||
extern int sff_bus_master_dma(int channel, uint8_t *data, int transfer_length, int out, void *priv);
|
||||
extern void sff_bus_master_set_irq(uint8_t status, void *priv);
|
||||
extern int sff_bus_master_dma(uint8_t *data, int transfer_length, int out, void *priv);
|
||||
|
||||
extern void sff_bus_master_write(uint16_t port, uint8_t val, void *priv);
|
||||
extern uint8_t sff_bus_master_read(uint16_t port, void *priv);
|
||||
|
||||
extern void sff_bus_master_reset(sff8038i_t *dev, uint16_t old_base);
|
||||
extern void sff_bus_master_reset(sff8038i_t *dev);
|
||||
|
||||
extern void sff_set_slot(sff8038i_t *dev, int slot);
|
||||
|
||||
extern void sff_set_irq_line(sff8038i_t *dev, int irq_line);
|
||||
|
||||
extern void sff_set_irq_mode(sff8038i_t *dev, int channel, int irq_mode);
|
||||
extern void sff_set_irq_mode(sff8038i_t *dev, int irq_mode);
|
||||
extern void sff_set_irq_pin(sff8038i_t *dev, int irq_pin);
|
||||
|
||||
extern void sff_set_irq_level(sff8038i_t *dev, int channel, int irq_level);
|
||||
extern void sff_set_irq_level(sff8038i_t *dev, int irq_level);
|
||||
|
||||
#endif /*EMU_HDC_IDE_SFF8038I_H*/
|
||||
|
||||
@@ -147,10 +147,14 @@
|
||||
|
||||
#define pci_set_mirq(mirq, level, irq_state) \
|
||||
pci_irq(PCI_MIRQ_BASE | (mirq), 0, level, 1, irq_state)
|
||||
#define pci_set_dirq(irq, irq_state) \
|
||||
pci_irq(PCI_DIRQ_BASE | (irq), 0, 1, 1, irq_state)
|
||||
#define pci_set_irq(slot, pci_int, irq_state) \
|
||||
pci_irq(slot, pci_int, 0, 1, irq_state)
|
||||
#define pci_clear_mirq(mirq, level, irq_state) \
|
||||
pci_irq(PCI_MIRQ_BASE | (mirq), 0, level, 0, irq_state)
|
||||
#define pci_clear_dirq(dirq, irq_state) \
|
||||
pci_irq(PCI_DIRQ_BASE | (irq), 0, 1, 0, irq_state)
|
||||
#define pci_clear_irq(slot, pci_int, irq_state) \
|
||||
pci_irq(slot, pci_int, 0, 0, irq_state)
|
||||
|
||||
@@ -216,7 +220,9 @@ extern uint32_t pci_size;
|
||||
extern void pci_set_irq_routing(int pci_int, int irq);
|
||||
extern void pci_set_irq_level(int pci_int, int level);
|
||||
extern void pci_enable_mirq(int mirq);
|
||||
extern void pci_set_mirq_routing(int mirq, int irq);
|
||||
extern void pci_set_mirq_routing(int mirq, uint8_t irq);
|
||||
extern uint8_t pci_get_mirq_level(int mirq);
|
||||
extern void pci_set_mirq_level(int mirq, uint8_t irq);
|
||||
|
||||
/* PCI raise IRQ: the first parameter is slot if < PCI_MIRQ_BASE, MIRQ if >= PCI_MIRQ_BASE
|
||||
and < PCI_DIRQ_BASE, and direct IRQ line if >= PCI_DIRQ_BASE (RichardG's
|
||||
|
||||
@@ -81,9 +81,11 @@ extern void pic_init_pcjr(void);
|
||||
extern void pic2_init(void);
|
||||
extern void pic_reset(void);
|
||||
|
||||
extern int picint_is_level(int irq);
|
||||
extern void picint_common(uint16_t num, int level, int set, uint8_t *irq_state);
|
||||
extern int picinterrupt(void);
|
||||
extern uint8_t pic_read_icw(uint8_t pic_id, uint8_t icw);
|
||||
extern uint8_t pic_read_ocw(uint8_t pic_id, uint8_t ocw);
|
||||
extern int picint_is_level(int irq);
|
||||
extern void picint_common(uint16_t num, int level, int set, uint8_t *irq_state);
|
||||
extern int picinterrupt(void);
|
||||
|
||||
#define PIC_IRQ_EDGE 0
|
||||
#define PIC_IRQ_LEVEL 1
|
||||
|
||||
@@ -131,6 +131,8 @@ extern void pit_nmi_timer_ps2(int new_out, int old_out);
|
||||
extern void pit_set_clock(uint32_t clock);
|
||||
extern void pit_handler(int set, uint16_t base, int size, void *priv);
|
||||
|
||||
extern uint8_t pit_read_reg(void *priv, uint8_t reg);
|
||||
|
||||
#ifdef EMU_DEVICE_H
|
||||
extern const device_t i8253_device;
|
||||
extern const device_t i8254_device;
|
||||
|
||||
@@ -69,6 +69,8 @@ typedef struct pitf_t {
|
||||
uint8_t ctrl;
|
||||
} pitf_t;
|
||||
|
||||
extern uint8_t pitf_read_reg(void *priv, uint8_t reg);
|
||||
|
||||
extern const pit_intf_t pit_fast_intf;
|
||||
|
||||
#ifdef EMU_DEVICE_H
|
||||
|
||||
Reference in New Issue
Block a user