From 8899b1411b0377aafb8de584f6697a587677559a Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Tue, 1 Oct 2024 09:56:40 +0200
Subject: [PATCH] AMD K6-2 onwards: EFER write GPF is now correctly on bits 5
 onwards, not on bits 1 onwards.

---
 src/cpu/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c
index 878c67b6a..0c6d36097 100644
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -3705,7 +3705,7 @@ cpu_WRMSR(void)
                 /* Extended Feature Enable Register */
                 case 0xc0000080:
                     temp = EAX | ((uint64_t) EDX << 32);
-                    if (temp & ~1ULL)
+                    if (temp & ~0x1fULL)
                         x86gpf(NULL, 0);
                     else
                         msr.amd_efer = temp;