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Don't depend on DEV_BRANCH

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Allows things to be compiled independently
This commit is contained in:
Jasmine Iwanek
2024-08-08 20:25:03 -04:00
parent 3cd59235c9
commit 892f066ffa
19 changed files with 163 additions and 163 deletions
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120
src/cpu/cpu.c
View File

@@ -47,7 +47,7 @@
#ifdef USE_DYNAREC
# include "codegen.h"
#endif
#endif /* USE_DYNAREC */
#include "x87_timings.h"
#define CCR1_USE_SMI (1 << 1)
@@ -119,7 +119,7 @@ const OpFn *x86_dynarec_opcodes_df_a32;
const OpFn *x86_dynarec_opcodes_REPE;
const OpFn *x86_dynarec_opcodes_REPNE;
const OpFn *x86_dynarec_opcodes_3DNOW;
#endif
#endif /* USE_DYNAREC */
const OpFn *x86_opcodes;
const OpFn *x86_opcodes_0f;
@@ -504,7 +504,7 @@ cpu_set(void)
#ifdef USE_ACYCS
acycs = 0;
#endif
#endif /* USE_ACYCS */
soft_reset_pci = 0;
cpu_init = 0;
@@ -576,7 +576,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_386_0f, dynarec_ops_386, dynarec_ops_386_0f);
#else
x86_setopcodes(ops_386, ops_386_0f);
#endif
#endif /* USE_DYNAREC */
x86_setopcodes_2386(ops_2386_386, ops_2386_386_0f);
x86_opcodes_REPE = ops_REPE;
x86_opcodes_REPNE = ops_REPNE;
@@ -587,7 +587,7 @@ cpu_set(void)
x86_dynarec_opcodes_REPE = dynarec_ops_REPE;
x86_dynarec_opcodes_REPNE = dynarec_ops_REPNE;
x86_dynarec_opcodes_3DNOW = dynarec_ops_3DNOW;
#endif
#endif /* USE_DYNAREC */
if (hasfpu) {
#ifdef USE_DYNAREC
@@ -626,7 +626,7 @@ cpu_set(void)
x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_df_a16;
x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_df_a32;
}
#endif
#endif /* USE_DYNAREC */
if (fpu_softfloat) {
x86_opcodes_d8_a16 = ops_sf_fpu_d8_a16;
x86_opcodes_d8_a32 = ops_sf_fpu_d8_a32;
@@ -714,7 +714,7 @@ cpu_set(void)
x86_dynarec_opcodes_de_a32 = dynarec_ops_nofpu_a32;
x86_dynarec_opcodes_df_a16 = dynarec_ops_nofpu_a16;
x86_dynarec_opcodes_df_a32 = dynarec_ops_nofpu_a32;
#endif
#endif /* USE_DYNAREC */
x86_opcodes_d8_a16 = ops_nofpu_a16;
x86_opcodes_d8_a32 = ops_nofpu_a32;
x86_opcodes_d9_a16 = ops_nofpu_a16;
@@ -752,7 +752,7 @@ cpu_set(void)
#ifdef USE_DYNAREC
codegen_timing_set(&codegen_timing_486);
#endif
#endif /* USE_DYNAREC */
memset(&msr, 0, sizeof(msr));
@@ -774,7 +774,7 @@ cpu_set(void)
x86_setopcodes(ops_186, ops_186_0f, dynarec_ops_186, dynarec_ops_186_0f);
#else
x86_setopcodes(ops_186, ops_186_0f);
#endif
#endif /* USE_DYNAREC */
x86_setopcodes_2386(ops_2386_186, ops_2386_186_0f);
break;
@@ -783,7 +783,7 @@ cpu_set(void)
x86_setopcodes(ops_286, ops_286_0f, dynarec_ops_286, dynarec_ops_286_0f);
#else
x86_setopcodes(ops_286, ops_286_0f);
#endif
#endif /* USE_DYNAREC */
x86_setopcodes_2386(ops_2386_286, ops_2386_286_0f);
if (fpu_type == FPU_287) {
@@ -819,7 +819,7 @@ cpu_set(void)
x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_287_df_a16;
x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_287_df_a32;
}
#endif
#endif /* USE_DYNAREC */
if (fpu_softfloat) {
x86_opcodes_d9_a16 = ops_sf_fpu_287_d9_a16;
x86_opcodes_d9_a32 = ops_sf_fpu_287_d9_a32;
@@ -921,7 +921,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_ibm486_0f, dynarec_ops_386, dynarec_ops_ibm486_0f);
#else
x86_setopcodes(ops_386, ops_ibm486_0f);
#endif
#endif /* USE_DYNAREC */
x86_setopcodes_2386(ops_2386_386, ops_2386_ibm486_0f);
cpu_features = CPU_FEATURE_MSR;
fallthrough;
@@ -961,7 +961,7 @@ cpu_set(void)
x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_287_df_a16;
x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_287_df_a32;
}
#endif
#endif /* USE_DYNAREC */
if (fpu_softfloat) {
x86_opcodes_d9_a16 = ops_sf_fpu_287_d9_a16;
x86_opcodes_d9_a32 = ops_sf_fpu_287_d9_a32;
@@ -1067,7 +1067,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
#else
x86_setopcodes(ops_386, ops_486_0f);
#endif
#endif /* USE_DYNAREC */
x86_setopcodes_2386(ops_2386_386, ops_2386_486_0f);
timing_rr = 1; /* register dest - register src */
@@ -1107,7 +1107,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
#else
x86_setopcodes(ops_386, ops_486_0f);
#endif
#endif /* USE_DYNAREC */
x86_setopcodes_2386(ops_2386_386, ops_2386_486_0f);
timing_rr = 1; /* register dest - register src */
@@ -1160,7 +1160,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
#else
x86_setopcodes(ops_386, ops_486_0f);
#endif
#endif /* USE_DYNAREC */
x86_setopcodes_2386(ops_2386_386, ops_2386_486_0f);
timing_rr = 1; /* register dest - register src */
@@ -1209,7 +1209,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_stpc_0f);
else
x86_setopcodes(ops_386, ops_c486_0f);
#endif
#endif /* USE_DYNAREC */
timing_rr = 1; /* register dest - register src */
timing_rm = 3; /* register dest - memory src */
@@ -1252,7 +1252,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_c486_0f, dynarec_ops_386, dynarec_ops_c486_0f);
#else
x86_setopcodes(ops_386, ops_c486_0f);
#endif
#endif /* USE_DYNAREC */
timing_rr = 1; /* register dest - register src */
timing_rm = 1; /* register dest - memory src */
@@ -1301,7 +1301,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_winchip2_0f);
else
x86_setopcodes(ops_386, ops_winchip_0f);
#endif
#endif /* USE_DYNAREC */
timing_rr = 1; /* register dest - register src */
timing_rm = 2; /* register dest - memory src */
@@ -1350,7 +1350,7 @@ cpu_set(void)
codegen_timing_set(&codegen_timing_winchip2);
else
codegen_timing_set(&codegen_timing_winchip);
#endif
#endif /* USE_DYNAREC */
break;
case CPU_P24T:
@@ -1366,7 +1366,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_pentiummmx_0f);
else
x86_setopcodes(ops_386, ops_pentium_0f);
#endif
#endif /* USE_DYNAREC */
timing_rr = 1; /* register dest - register src */
timing_rm = 2; /* register dest - memory src */
@@ -1409,10 +1409,10 @@ cpu_set(void)
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
#ifdef USE_DYNAREC
codegen_timing_set(&codegen_timing_pentium);
#endif
#endif /* USE_DYNAREC */
break;
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#ifdef USE_CYRIX_6X86
case CPU_Cx6x86:
case CPU_Cx6x86L:
case CPU_CxGX1:
@@ -1434,7 +1434,7 @@ cpu_set(void)
x86_dynarec_opcodes_df_a16 = dynarec_ops_fpu_686_df_a16;
x86_dynarec_opcodes_df_a32 = dynarec_ops_fpu_686_df_a32;
}
# endif
# endif /* USE_DYNAREC */
if (fpu_softfloat) {
x86_opcodes_da_a16 = ops_sf_fpu_686_da_a16;
x86_opcodes_da_a32 = ops_sf_fpu_686_da_a32;
@@ -1472,7 +1472,7 @@ cpu_set(void)
# if 0
x86_setopcodes(ops_386, ops_c6x86_0f);
# endif
# endif
# endif /* USE_DYNAREC */
timing_rr = 1; /* register dest - register src */
timing_rm = 1; /* register dest - memory src */
@@ -1524,19 +1524,19 @@ cpu_set(void)
# ifdef USE_DYNAREC
codegen_timing_set(&codegen_timing_686);
# endif
# endif /* USE_DYNAREC */
if ((cpu_s->cpu_type == CPU_Cx6x86L) || (cpu_s->cpu_type == CPU_Cx6x86MX))
ccr4 = 0x80;
else if (CPU_Cx6x86)
CPUID = 0; /* Disabled on powerup by default */
break;
#endif
#endif /* USE_CYRIX_6X86 */
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
#ifdef USE_AMD_K5
case CPU_K5:
case CPU_5K86:
#endif
#endif /* USE_AMD_K5 */
case CPU_K6:
case CPU_K6_2:
case CPU_K6_2C:
@@ -1546,7 +1546,7 @@ cpu_set(void)
#ifdef USE_DYNAREC
if (cpu_s->cpu_type >= CPU_K6_2)
x86_setopcodes(ops_386, ops_k62_0f, dynarec_ops_386, dynarec_ops_k62_0f);
# if defined(DEV_BRANCH) && defined(USE_AMD_K5)
# ifdef USE_AMD_K5
else if (cpu_s->cpu_type == CPU_K6)
x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f);
else
@@ -1554,11 +1554,11 @@ cpu_set(void)
# else
else
x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f);
# endif
# endif /* USE_AMD_K5 */
#else
if (cpu_s->cpu_type >= CPU_K6_2)
x86_setopcodes(ops_386, ops_k62_0f);
# if defined(DEV_BRANCH) && defined(USE_AMD_K5)
# ifdef USE_AMD_K5
else if (cpu_s->cpu_type == CPU_K6)
x86_setopcodes(ops_386, ops_k6_0f);
else
@@ -1566,14 +1566,14 @@ cpu_set(void)
# else
else
x86_setopcodes(ops_386, ops_k6_0f);
# endif
#endif
# endif /* USE_AMD_K5 */
#endif /* USE_DYNAREC */
if ((cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P)) {
x86_opcodes_3DNOW = ops_3DNOWE;
#ifdef USE_DYNAREC
x86_dynarec_opcodes_3DNOW = dynarec_ops_3DNOWE;
#endif
#endif /* USE_DYNAREC */
}
timing_rr = 1; /* register dest - register src */
@@ -1613,7 +1613,7 @@ cpu_set(void)
cpu_features |= CPU_FEATURE_3DNOW;
if ((cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P))
cpu_features |= CPU_FEATURE_3DNOWE;
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
#ifdef USE_AMD_K5
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE;
if (cpu_s->cpu_type >= CPU_K6) {
cpu_CR4_mask |= (CR4_VME | CR4_PVI | CR4_PSE);
@@ -1629,11 +1629,11 @@ cpu_set(void)
cpu_CR4_mask |= CR4_PCE;
else if (cpu_s->cpu_type >= CPU_K6_2C)
cpu_CR4_mask |= CR4_PGE;
#endif
#endif /* USE_AMD_K5 */
#ifdef USE_DYNAREC
codegen_timing_set(&codegen_timing_k6);
#endif
#endif /* USE_DYNAREC */
break;
case CPU_PENTIUMPRO:
@@ -1668,7 +1668,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_pentium2d_0f);
else
x86_setopcodes(ops_386, ops_pentium2_0f);
#endif
#endif /* USE_DYNAREC */
if (fpu_softfloat) {
x86_opcodes_da_a16 = ops_sf_fpu_686_da_a16;
x86_opcodes_da_a32 = ops_sf_fpu_686_da_a32;
@@ -1726,7 +1726,7 @@ cpu_set(void)
#ifdef USE_DYNAREC
codegen_timing_set(&codegen_timing_p6);
#endif
#endif /* USE_DYNAREC */
break;
case CPU_CYRIX3S:
@@ -1734,7 +1734,7 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_winchip2_0f, dynarec_ops_386, dynarec_ops_winchip2_0f);
#else
x86_setopcodes(ops_386, ops_winchip2_0f);
#endif
#endif /* USE_DYNAREC */
timing_rr = 1; /* register dest - register src */
timing_rm = 2; /* register dest - memory src */
timing_mr = 2; /* memory dest - register src */
@@ -1774,7 +1774,7 @@ cpu_set(void)
#ifdef USE_DYNAREC
codegen_timing_set(&codegen_timing_winchip);
#endif
#endif /* USE_DYNAREC */
break;
default:
@@ -1812,7 +1812,7 @@ cpu_set(void)
cpu_exec = exec386_dynarec;
cpu_use_exec = 1;
} else
#endif
#endif /* defined(USE_DYNAREC) && !defined(USE_GDBSTUB) */
/* Use exec386 for CPU_IBM486SLC because it can reach 100 MHz. */
if ((cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type == CPU_IBM486BL) ||
cpu_iscyrix || (cpu_s->cpu_type > CPU_486DLC) || cpu_override_interpreter) {
@@ -2065,7 +2065,7 @@ cpu_CPUID(void)
EAX = EBX = ECX = EDX = 0;
break;
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
#ifdef USE_AMD_K5
case CPU_K5:
if (!EAX) {
EAX = 0x00000001;
@@ -2123,7 +2123,7 @@ cpu_CPUID(void)
break;
}
break;
#endif
#endif /* USE_AMD_K5 */
case CPU_K6:
switch (EAX) {
@@ -2354,7 +2354,7 @@ cpu_CPUID(void)
EAX = EBX = ECX = EDX = 0;
break;
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#ifdef USE_CYRIX_6X86
case CPU_Cx6x86:
if (!EAX) {
EAX = 0x00000001;
@@ -2410,7 +2410,7 @@ cpu_CPUID(void)
} else
EAX = EBX = ECX = EDX = 0;
break;
#endif
#endif /* USE_CYRIX_6X86 */
case CPU_PENTIUMPRO:
if (!EAX) {
@@ -2565,10 +2565,10 @@ cpu_ven_reset(void)
msr.amd_psor = (cpu_s->cpu_type >= CPU_K6_3) ? 0x008cULL : 0x018cULL;
fallthrough;
case CPU_K6_2:
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
#ifdef USE_AMD_K5
case CPU_K5:
case CPU_5K86:
#endif
#endif /* USE_AMD_K5 */
case CPU_K6:
msr.amd_efer = (cpu_s->cpu_type >= CPU_K6_2C) ? 2ULL : 0ULL;
break;
@@ -2789,10 +2789,10 @@ cpu_RDMSR(void)
}
break;
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
#ifdef USE_AMD_K5
case CPU_K5:
case CPU_5K86:
#endif
#endif /* USE_AMD_K5 */
case CPU_K6:
case CPU_K6_2:
case CPU_K6_2C:
@@ -3075,7 +3075,7 @@ pentium_invalid_rdmsr:
cpu_log("RDMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
break;
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#ifdef USE_CYRIX_6X86
case CPU_Cx6x86:
case CPU_Cx6x86L:
case CPU_CxGX1:
@@ -3115,7 +3115,7 @@ pentium_invalid_rdmsr:
}
cpu_log("RDMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
break;
#endif
#endif /* USE_CYRIX_6X86 */
case CPU_PENTIUMPRO:
case CPU_PENTIUM2:
@@ -3638,10 +3638,10 @@ cpu_WRMSR(void)
}
break;
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
#ifdef USE_AMD_K5
case CPU_K5:
case CPU_5K86:
#endif
#endif /* USE_AMD_K5 */
case CPU_K6:
case CPU_K6_2:
case CPU_K6_2C:
@@ -3902,7 +3902,7 @@ pentium_invalid_wrmsr:
}
break;
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#ifdef USE_CYRIX_6X86
case CPU_Cx6x86:
case CPU_Cx6x86L:
case CPU_CxGX1:
@@ -3936,7 +3936,7 @@ pentium_invalid_wrmsr:
break;
}
break;
#endif
#endif /* USE_CYRIX_6X86 */
case CPU_PENTIUMPRO:
case CPU_PENTIUM2:
@@ -4249,14 +4249,14 @@ cpu_write(uint16_t addr, uint8_t val, UNUSED(void *priv))
case 0xe8: /* CCR4 */
if ((ccr3 & 0xf0) == 0x10) {
ccr4 = val;
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#ifdef USE_CYRIX_6X86
if (cpu_s->cpu_type >= CPU_Cx6x86) {
if (val & 0x80)
CPUID = cpu_s->cpuid_model;
else
CPUID = 0;
}
#endif
#endif /* USE_CYRIX_6X86 */
}
break;
case 0xe9: /* CCR5 */
@@ -4330,7 +4330,7 @@ x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f)
x86_opcodes = opcodes;
x86_opcodes_0f = opcodes_0f;
}
#endif
#endif /* USE_DYNAREC */
void
x86_setopcodes_2386(const OpFn *opcodes, const OpFn *opcodes_0f)

8
src/cpu/cpu_table.c
View File

@@ -4474,7 +4474,7 @@ const cpu_family_t cpu_families[] = {
{ .name = "", 0 }
}
},
#if defined(DEV_BRANCH) && defined(USE_AMD_K5)
#ifdef USE_AMD_K5
{
.package = CPU_PKG_SOCKET5_7,
.manufacturer = "AMD",
@@ -4629,7 +4629,7 @@ const cpu_family_t cpu_families[] = {
{ .name = "", 0 }
}
},
#endif
#endif /* USE_AMD_K5 */
{
.package = CPU_PKG_SOCKET5_7,
.manufacturer = "AMD",
@@ -5982,7 +5982,7 @@ const cpu_family_t cpu_families[] = {
{ .name = "", 0 }
}
},
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#ifdef USE_CYRIX_6X86
{
.package = CPU_PKG_SOCKET5_7,
.manufacturer = "Cyrix",
@@ -6342,7 +6342,7 @@ const cpu_family_t cpu_families[] = {
{ .name = "", 0 }
}
},
#endif
#endif /* USE_CYRIX_6X86 */
{
.package = CPU_PKG_SOCKET8,
.manufacturer = "Intel",

8
src/cpu/x86_ops.h
View File

@@ -90,10 +90,10 @@ extern const OpFn dynarec_ops_winchip2_0f[1024];
extern const OpFn dynarec_ops_pentium_0f[1024];
extern const OpFn dynarec_ops_pentiummmx_0f[1024];
# if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
# ifdef USE_CYRIX_6X86
extern const OpFn dynarec_ops_c6x86_0f[1024];
extern const OpFn dynarec_ops_c6x86mx_0f[1024];
# endif
# endif /* USE_CYRIX_6X86 */
extern const OpFn dynarec_ops_k6_0f[1024];
extern const OpFn dynarec_ops_k62_0f[1024];
@@ -232,10 +232,10 @@ extern const OpFn ops_winchip2_0f[1024];
extern const OpFn ops_pentium_0f[1024];
extern const OpFn ops_pentiummmx_0f[1024];
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#ifdef USE_CYRIX_6X86
extern const OpFn ops_c6x86_0f[1024];
extern const OpFn ops_c6x86mx_0f[1024];
#endif
#endif /* USE_CYRIX_6X86 */
extern const OpFn ops_k6_0f[1024];
extern const OpFn ops_k62_0f[1024];

4
src/cpu/x86_ops_mmx_mov.h
View File

@@ -110,7 +110,7 @@ opMOVD_mm_l_a32(uint32_t fetchdat)
return 0;
}
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#ifdef USE_CYRIX_6X86
/*Cyrix maps both MOVD and SMINT to the same opcode*/
static int
opMOVD_mm_l_a16_cx(uint32_t fetchdat)
@@ -170,7 +170,7 @@ opMOVD_mm_l_a32_cx(uint32_t fetchdat)
return 0;
}
#endif
#endif /* USE_CYRIX_6X86 */
static int
opMOVQ_q_mm_a16(uint32_t fetchdat)