diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 000000000..3a15916d4 --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1,2 @@ +patreon: 86box +custom: ["https://paypal.me/86Box"] diff --git a/README.md b/README.md index 977ab598d..080e2d1c9 100644 --- a/README.md +++ b/README.md @@ -54,3 +54,6 @@ Donations --------- We do not charge you for the emulator but donations are still welcome: https://paypal.me/86Box. + +You can now also support the project on Pateron: +https://www.patreon.com/86box. diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c index 43ad5abaf..c5e751c78 100644 --- a/src/chipset/intel_piix.c +++ b/src/chipset/intel_piix.c @@ -1040,7 +1040,10 @@ piix_reset_hard(piix_t *dev) fregs[0x09] = 0x80; fregs[0x0a] = 0x01; fregs[0x0b] = 0x01; if (dev->type == 5) { - fregs[0x10] = fregs[0x14] = fregs[0x18] = fregs[0x1c] = 0x01; + fregs[0x10] = 0xf1; fregs[0x11] = 0x01; + fregs[0x14] = 0xf5; fregs[0x15] = 0x03; + fregs[0x18] = 0x71; fregs[0x19] = 0x01; + fregs[0x1c] = 0x75; fregs[0x1d] = 0x03; } fregs[0x20] = 0x01; if (dev->type == 5) { diff --git a/src/chipset/opti283.c b/src/chipset/opti283.c index a4dad3d29..c0950e563 100644 --- a/src/chipset/opti283.c +++ b/src/chipset/opti283.c @@ -35,6 +35,9 @@ #include <86box/port_92.h> #include <86box/chipset.h> +#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY) + + typedef struct { uint8_t index, @@ -43,54 +46,46 @@ typedef struct static void opti283_shadow_recalc(opti283_t *dev) { -uint32_t base; -uint32_t shflags, i = 0; +uint32_t base, i; +uint32_t shflagsc, shflagsd, shflagse, shflagsf; -shadowbios = 0; -shadowbios_write = 0; +shadowbios = !(dev->regs[0x11] & 0x80); +shadowbios_write = (dev->regs[0x11] & 0x80); + +if(dev->regs[0x11] & 0x10){ + shflagsc = MEM_READ_INTERNAL; + shflagsc |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; +} else shflagsc = disabled_shadow; + +if(dev->regs[0x11] & 0x20){ + shflagsd = MEM_READ_INTERNAL; + shflagsd |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; +} else shflagsd = disabled_shadow; + +if(dev->regs[0x11] & 0x40){ + shflagse = MEM_READ_INTERNAL; + shflagse |= (dev->regs[0x11] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; +} else shflagse = disabled_shadow; - /* F0000 - FFFFF segmentation */ if(!(dev->regs[0x11] & 0x80)){ - shadowbios = 1; - shadowbios_write = 0; - mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED); -} else { - shadowbios = 0; - shadowbios_write = 1; - mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); -} + shflagsf = MEM_READ_INTERNAL | MEM_WRITE_DISABLED; +} else shflagsf = MEM_READ_EXTANY | MEM_WRITE_INTERNAL; + +mem_set_mem_state_both(0xf0000, 0x10000, shflagsf); - /* C0000 - CFFFF segmentation */ for(i = 4; i < 8; i++){ - base = 0xc0000 + ((i-4) << 14); - - if((dev->regs[0x13] & (1 << i)) & (dev->regs[0x11] & 0x10)){ - shflags = MEM_READ_INTERNAL; - shflags |= (!(dev->regs[0x11] & 0x01)) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED; - mem_set_mem_state_both(base, 0x4000, shflags); - } else { - mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); -} +base = 0xc0000 + ((i-4) << 14); +mem_set_mem_state_both(base, 0x4000, (dev->regs[0x13] & (1 << i)) ? shflagsc : disabled_shadow); } - /* D0000 - DFFFF segmentation */ for(i = 0; i < 4; i++){ - base = 0xd0000 + (i << 14); - if((dev->regs[0x12] & (1 << i)) & (dev->regs[0x11] & 0x20)){ - shflags = MEM_READ_INTERNAL; - shflags |= (!(dev->regs[0x11] & 0x02)) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED; - mem_set_mem_state(base, 0x4000, shflags); - } else mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); +base = 0xd0000 + (i << 14); +mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagsd : disabled_shadow); } - /* E0000 - EFFFF segmentation */ for(i = 4; i < 8; i++){ - base = 0xe0000 + ((i-4) << 14); - if((dev->regs[0x12] & (1 << i)) & (dev->regs[0x11] & 0x40)){ - shflags = MEM_READ_INTERNAL; - shflags |= (!(dev->regs[0x11] & 0x04)) ? MEM_WRITE_INTERNAL : MEM_WRITE_DISABLED; - mem_set_mem_state(base, 0x4000, shflags); - } else mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); +base = 0xe0000 + ((i-4) << 14); +mem_set_mem_state_both(base, 0x4000, (dev->regs[0x12] & (1 << i)) ? shflagse : disabled_shadow); } } @@ -105,12 +100,13 @@ opti283_write(uint16_t addr, uint8_t val, void *priv) dev->index = val; break; case 0x24: - /*pclog("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val);*/ + /* pclog("OPTi 283: dev->regs[%02x] = %02x\n", dev->index, val); */ dev->regs[dev->index] = val; switch(dev->index){ case 0x10: cpu_update_waitstates(); + break; case 0x11: case 0x12: diff --git a/src/chipset/opti495.c b/src/chipset/opti495.c index c3fa1bda4..688bbf492 100644 --- a/src/chipset/opti495.c +++ b/src/chipset/opti495.c @@ -131,12 +131,13 @@ opti495_write(uint16_t addr, uint8_t val, void *priv) switch (addr) { case 0x22: + opti495_log("[%04X:%08X] [W] dev->idx = %02X\n", CS, cpu_state.pc, val); dev->idx = val; break; case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2c)) { + if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { dev->regs[dev->idx] = val; - opti495_log("dev->regs[%04x] = %08x\n", dev->idx, val); + opti495_log("[%04X:%08X] [W] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, val); switch(dev->idx) { case 0x21: @@ -168,9 +169,14 @@ opti495_read(uint16_t addr, void *priv) opti495_t *dev = (opti495_t *) priv; switch (addr) { + case 0x22: + opti495_log("[%04X:%08X] [R] dev->idx = %02X\n", CS, cpu_state.pc, ret); + break; case 0x24: - if ((dev->idx >= 0x20) && (dev->idx <= 0x2c)) + if ((dev->idx >= 0x20) && (dev->idx <= 0x2d)) { ret = dev->regs[dev->idx]; + opti495_log("[%04X:%08X] [R] dev->regs[%04X] = %02X\n", CS, cpu_state.pc, dev->idx, ret); + } break; case 0xe1: case 0xe2: @@ -197,6 +203,8 @@ opti495_init(const device_t *info) opti495_t *dev = (opti495_t *) malloc(sizeof(opti495_t)); memset(dev, 0, sizeof(opti495_t)); + device_add(&port_92_device); + io_sethandler(0x0022, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev); io_sethandler(0x0024, 0x0001, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev); diff --git a/src/chipset/opti5x7.c b/src/chipset/opti5x7.c index ef43b5343..af224437d 100644 --- a/src/chipset/opti5x7.c +++ b/src/chipset/opti5x7.c @@ -45,35 +45,38 @@ static void opti5x7_recalc(opti5x7_t *dev) { uint32_t base; - uint32_t i, j, shflags = 0; + uint32_t i, shflags = 0; uint32_t reg, lowest_bit; - uint32_t write = 0; + + shadowbios = 0; + shadowbios_write = 0; for (i = 0; i < 8; i++) { - j = i / 2.01; /*Probably not a great way of doing this, but it does work*/ - base = 0xc0000 + (j << 14); - - lowest_bit = j * 2; - reg = 0x04 + ((base >> 16) & 0x01); - - shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : write; - write = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY; - mem_set_mem_state(base, 0x4000, shflags); + base = 0xc0000 + (i << 14); + + lowest_bit = (i << 1) & 0x07; + reg = 0x04 + ((base >> 16) & 0x01); + + shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; + shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; + mem_set_mem_state(base, 0x4000, shflags); } + shadowbios |= !!(dev->regs[0x06] & 0x05); + shadowbios_write |= !!(dev->regs[0x06] & 0x0a); + shflags = (dev->regs[0x06] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : write; - write = (dev->regs[0x06] & 0x01) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY; + shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; mem_set_mem_state(0xe0000, 0x10000, shflags); shflags = (dev->regs[0x06] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; - shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : write; - write = (dev->regs[0x06] & 0x04) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY; + shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; mem_set_mem_state(0xf0000, 0x10000, shflags); flushmmucache(); } + + static void opti5x7_write(uint16_t addr, uint8_t val, void *priv) { @@ -90,7 +93,7 @@ opti5x7_write(uint16_t addr, uint8_t val, void *priv) case 0x02: cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x04 & 0x08); break; - + case 0x04: case 0x05: case 0x06: @@ -138,9 +141,6 @@ opti5x7_init(const device_t *info) io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev); dev->port_92 = device_add(&port_92_device); -// pclog("OPTi 5x7 init\n"); - opti5x7_recalc(dev); - return dev; } diff --git a/src/chipset/stpc.c b/src/chipset/stpc.c new file mode 100644 index 000000000..a4dc8df96 --- /dev/null +++ b/src/chipset/stpc.c @@ -0,0 +1,725 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of the STPC series of SoCs. + * + * + * + * Authors: RichardG, + * + * Copyright 2020 RichardG. + */ +#include +#include +#include +#include +#include +#include +#define HAVE_STDARG_H +#include <86box/86box.h> +#include <86box/mem.h> +#include <86box/io.h> +#include <86box/rom.h> +#include <86box/pci.h> +#include <86box/device.h> +#include <86box/keyboard.h> +#include <86box/port_92.h> +#include <86box/usb.h> +#include <86box/chipset.h> + + +#define STPC_NB_CLIENT 0x01 +#define STPC_ISAB_CLIENT 0x02 +#define STPC_ISAB_CONSUMER2 0x04 +#define STPC_IDE_ATLAS 0x08 +#define STPC_USB 0x10 + + +typedef struct stpc_t +{ + uint32_t local; + + /* Main registers (port 22h/23h) */ + uint8_t reg_offset; + uint8_t regs[256]; + + /* Host bus interface */ + uint16_t host_base; + uint8_t host_offset; + uint8_t host_regs[256]; + + /* Local bus */ + uint16_t localbus_base; + uint8_t localbus_offset; + uint8_t localbus_regs[256]; + + /* PCI devices */ + uint8_t pci_conf[4][256]; + usb_t *usb; +} stpc_t; + + +#define ENABLE_STPC_LOG 1 +#ifdef ENABLE_STPC_LOG +int stpc_do_log = ENABLE_STPC_LOG; + + +static void +stpc_log(const char *fmt, ...) +{ + va_list ap; + + if (stpc_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } +} +#else +#define stpc_log(fmt, ...) +#endif + + +static void +stpc_recalcmapping(stpc_t *dev) +{ + uint8_t reg, bitpair; + uint32_t base, size; + int state; + + shadowbios = 0; + shadowbios_write = 0; + + for (reg = 0; reg <= 3; reg++) { + for (bitpair = 0; bitpair <= (reg == 3 ? 0 : 3); bitpair++) { + if (reg == 3) { + size = 0x10000; + base = 0xf0000; + } else { + size = 0x4000; + base = 0xc0000 + (size * ((reg * 4) + bitpair)); + } + stpc_log("STPC: Shadowing for %05x-%05x (reg %02x bp %d wmask %02x rmask %02x) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1)); + + state = 0; + if (dev->regs[0x25 + reg] & (1 << (bitpair * 2))) { + stpc_log(" w on"); + state |= MEM_WRITE_INTERNAL; + if (base >= 0xe0000) + shadowbios_write |= 1; + } else { + stpc_log(" w off"); + state |= MEM_WRITE_EXTANY; + } + if (dev->regs[0x25 + reg] & (1 << ((bitpair * 2) + 1))) { + stpc_log("; r on\n"); + state |= MEM_READ_INTERNAL; + if (base >= 0xe0000) + shadowbios |= 1; + } else { + stpc_log("; r off\n"); + state |= MEM_READ_EXTANY; + } + + mem_set_mem_state(base, size, state); + } + } + + flushmmucache(); +} + + +static void +stpc_smram_map(int smm, uint32_t addr, uint32_t size, int is_smram) +{ + mem_set_mem_state_smram(smm, addr, size, is_smram); +} + + +static void +stpc_host_write(uint16_t addr, uint8_t val, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + + stpc_log("STPC: host_write(%04x, %02x)\n", addr, val); + + if (addr == dev->host_base) + dev->host_offset = val; + else if (addr == dev->host_base + 4) + dev->host_regs[dev->host_offset] = val; +} + + +static uint8_t +stpc_host_read(uint16_t addr, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + uint8_t ret; + + if (addr == dev->host_base) + ret = dev->host_offset; + else if (addr == dev->host_base + 4) + ret = dev->host_regs[dev->host_offset]; + else + ret = 0xff; + + stpc_log("STPC: host_read(%04x) = %02x\n", addr, ret); + return ret; +} + + +static void +stpc_localbus_write(uint16_t addr, uint8_t val, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + + stpc_log("STPC: localbus_write(%04x, %02x)\n", addr, val); + + if (addr == dev->localbus_base) + dev->localbus_offset = val; + else if (addr == dev->localbus_base + 4) + dev->localbus_regs[addr] = val; +} + + +static uint8_t +stpc_localbus_read(uint16_t addr, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + uint8_t ret; + + if (addr == dev->localbus_base) + ret = dev->localbus_offset; + else if (addr == dev->localbus_base + 4) + ret = dev->localbus_regs[dev->localbus_offset]; + else + ret = 0xff; + + stpc_log("STPC: localbus_read(%04x) = %02x\n", addr, ret); + return ret; +} + + +static void +stpc_nb_write(int func, int addr, uint8_t val, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + + stpc_log("STPC: nb_write(%d, %02x, %02x)\n", func, addr, val); + + if (func > 0) + return; + + switch (addr) { + case 0x00: case 0x01: case 0x02: case 0x03: + case 0x04: case 0x06: case 0x07: case 0x08: + case 0x09: case 0x0a: case 0x0b: case 0x0e: + case 0x51: case 0x53: case 0x54: + return; + + case 0x05: + val &= 0x01; + break; + + case 0x50: + val &= 0x1f; + break; + + case 0x52: + val &= 0x70; + break; + } + + dev->pci_conf[0][addr] = val; +} + + +static uint8_t +stpc_nb_read(int func, int addr, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + uint8_t ret; + + if (func > 0) + ret = 0xff; + else + ret = dev->pci_conf[0][addr]; + + stpc_log("STPC: nb_read(%d, %02x) = %02x\n", func, addr, ret); + return ret; +} + + +static void +stpc_ide_write(int func, int addr, uint8_t val, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + + stpc_log("STPC: ide_write(%d, %02x, %02x)\n", func, addr, val); + + if (func > 0) + return; + + switch (addr) { + case 0x00: case 0x01: case 0x02: case 0x03: + case 0x04: case 0x06: case 0x07: case 0x08: + case 0x09: case 0x0a: case 0x0b: case 0x0e: + return; + + case 0x05: + val &= 0x01; + break; + } + + dev->pci_conf[2][addr] = val; +} + + +static uint8_t +stpc_ide_read(int func, int addr, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + uint8_t ret; + + if (func > 0) + ret = 0xff; + else + ret = dev->pci_conf[2][addr]; + + stpc_log("STPC: ide_read(%d, %02x) = %02x\n", func, addr, ret); + return ret; +} + + +static void +stpc_isab_write(int func, int addr, uint8_t val, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + + if (func == 1 && !(dev->local & STPC_IDE_ATLAS)) { + stpc_ide_write(0, addr, val, priv); + return; + } + + stpc_log("STPC: isab_write(%d, %02x, %02x)\n", func, addr, val); + + if (func > 0) + return; + + switch (addr) { + case 0x00: case 0x01: case 0x02: case 0x03: + case 0x04: case 0x06: case 0x07: case 0x08: + case 0x09: case 0x0a: case 0x0b: case 0x0e: + return; + + case 0x05: + val &= 0x01; + break; + } + + dev->pci_conf[1][addr] = val; +} + + +static uint8_t +stpc_isab_read(int func, int addr, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + uint8_t ret; + + if (func == 1 && !(dev->local & STPC_IDE_ATLAS)) + return stpc_ide_read(0, addr, priv); + else if (func > 0) + ret = 0xff; + else + ret = dev->pci_conf[1][addr]; + + stpc_log("STPC: isab_read(%d, %02x) = %02x\n", func, addr, ret); + return ret; +} + + +static void +stpc_usb_write(int func, int addr, uint8_t val, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + + stpc_log("STPC: usb_write(%d, %02x, %02x)\n", func, addr, val); + + if (func > 0) + return; + + switch (addr) { + case 0x00: case 0x01: case 0x02: case 0x03: + case 0x04: case 0x06: case 0x07: case 0x08: + case 0x09: case 0x0a: case 0x0b: case 0x0e: + case 0x10: + return; + + case 0x05: + val &= 0x01; + break; + + case 0x11: + dev->pci_conf[3][addr] = val & 0xf0; + ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1); + break; + + case 0x12: case 0x13: + dev->pci_conf[3][addr] = val; + ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1); + break; + } + + dev->pci_conf[3][addr] = val; +} + + +static uint8_t +stpc_usb_read(int func, int addr, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + uint8_t ret; + + if (func > 0) + ret = 0xff; + else + ret = dev->pci_conf[3][addr]; + + stpc_log("STPC: usb_read(%d, %02x) = %02x\n", func, addr, ret); + return ret; +} + + +static void +stpc_remap_host(stpc_t *dev, uint16_t host_base) +{ + stpc_log("STPC: Remapping host bus from %04x to %04x\n", dev->host_base, host_base); + + io_removehandler(dev->host_base, 5, + stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev); + if (host_base) { + io_sethandler(host_base, 5, + stpc_host_read, NULL, NULL, stpc_host_write, NULL, NULL, dev); + } + dev->host_base = host_base; +} + + +static void +stpc_remap_localbus(stpc_t *dev, uint16_t localbus_base) +{ + stpc_log("STPC: Remapping local bus from %04x to %04x\n", dev->localbus_base, localbus_base); + + io_removehandler(dev->localbus_base, 5, + stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev); + if (localbus_base) { + io_sethandler(localbus_base, 5, + stpc_localbus_read, NULL, NULL, stpc_localbus_write, NULL, NULL, dev); + } + dev->localbus_base = localbus_base; +} + + +static void +stpc_reg_write(uint16_t addr, uint8_t val, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + + stpc_log("STPC: reg_write(%04x, %02x)\n", addr, val); + + if (addr == 0x22) { + dev->reg_offset = val; + } else { + stpc_log("STPC: regs[%02x] = %02x\n", dev->reg_offset, val); + + switch (dev->reg_offset) { + case 0x12: + if (dev->regs[0x10] == 0x07) + stpc_remap_host(dev, (dev->host_base & 0xff00) | val); + else if (dev->regs[0x10] == 0x06) + stpc_remap_localbus(dev, (dev->localbus_base & 0xff00) | val); + break; + + case 0x13: + if (dev->regs[0x10] == 0x07) + stpc_remap_host(dev, (dev->host_base & 0x00ff) | (val << 8)); + else if (dev->regs[0x10] == 0x06) + stpc_remap_localbus(dev, (dev->localbus_base & 0x00ff) | (val << 8)); + break; + + case 0x21: + val &= 0xfe; + break; + + case 0x22: + val &= 0x7f; + break; + + case 0x25: case 0x26: case 0x27: case 0x28: + if (dev->reg_offset == 0x28) { + val &= 0xe3; + stpc_smram_map(0, smram[0].host_base, smram[0].size, !!(val & 0x80)); + } + dev->regs[dev->reg_offset] = val; + stpc_recalcmapping(dev); + break; + + case 0x29: + val &= 0x0f; + break; + + case 0x36: + val &= 0x3f; + break; + } + + dev->regs[dev->reg_offset] = val; + } +} + + +static uint8_t +stpc_reg_read(uint16_t addr, void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + uint8_t ret; + + if (addr == 0x22) + ret = dev->reg_offset; + else if (dev->reg_offset >= 0xc0) + return 0xff; /* Cyrix CPU registers: let the CPU code handle those */ + else + ret = dev->regs[dev->reg_offset]; + + stpc_log("STPC: reg_read(%04x) = %02x\n", addr, ret); + return ret; +} + + +static void +stpc_reset(void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + + stpc_log("STPC: reset()\n"); + + memset(dev->regs, 0, sizeof(dev->regs)); + dev->regs[0x7b] = 0xff; + + io_removehandler(0x22, 2, + stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev); + io_sethandler(0x22, 2, + stpc_reg_read, NULL, NULL, stpc_reg_write, NULL, NULL, dev); +} + + +static void +stpc_setup(stpc_t *dev) +{ + stpc_log("STPC: setup()\n"); + + /* Northbridge */ + dev->pci_conf[0][0x00] = 0x4a; + dev->pci_conf[0][0x01] = 0x10; + if (dev->local & STPC_NB_CLIENT) { + dev->pci_conf[0][0x02] = 0x64; + dev->pci_conf[0][0x03] = 0x05; + } else { + dev->pci_conf[0][0x02] = 0x0a; + dev->pci_conf[0][0x03] = 0x02; + } + + dev->pci_conf[0][0x04] = 0x07; + + dev->pci_conf[0][0x06] = 0x80; + dev->pci_conf[0][0x07] = 0x02; + + dev->pci_conf[0][0x0b] = 0x06; + + /* ISA Bridge */ + dev->pci_conf[1][0x00] = 0x4a; + dev->pci_conf[1][0x01] = 0x10; + if (dev->local & STPC_ISAB_CLIENT) { + dev->pci_conf[1][0x02] = 0xcc; + dev->pci_conf[1][0x03] = 0x55; + } else if (dev->local & STPC_ISAB_CONSUMER2) { + dev->pci_conf[1][0x02] = 0x0b; + dev->pci_conf[1][0x03] = 0x02; + } else { + dev->pci_conf[1][0x02] = 0x10; + dev->pci_conf[1][0x03] = 0x02; + } + + dev->pci_conf[1][0x04] = 0x0f; + + dev->pci_conf[1][0x06] = 0x80; + dev->pci_conf[1][0x07] = 0x02; + + dev->pci_conf[1][0x0a] = 0x01; + dev->pci_conf[1][0x0b] = 0x06; + + dev->pci_conf[1][0x0e] = 0x40; + + /* IDE */ + dev->pci_conf[2][0x00] = 0x4a; + dev->pci_conf[2][0x01] = 0x10; + if (dev->local & STPC_IDE_ATLAS) { + dev->pci_conf[2][0x02] = 0x28; + dev->pci_conf[2][0x03] = 0x02; + } else { + dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02]; + dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03]; + } + + dev->pci_conf[2][0x06] = 0x80; + dev->pci_conf[2][0x07] = 0x02; + + dev->pci_conf[2][0x09] = 0x8a; + dev->pci_conf[2][0x0a] = 0x01; + dev->pci_conf[2][0x0b] = 0x01; + + dev->pci_conf[2][0x0e] = 0x40; + + dev->pci_conf[2][0x10] = 0x01; + dev->pci_conf[2][0x14] = 0x01; + dev->pci_conf[2][0x18] = 0x01; + dev->pci_conf[2][0x1c] = 0x01; + + dev->pci_conf[2][0x40] = 0x60; + dev->pci_conf[2][0x41] = 0x97; + dev->pci_conf[2][0x42] = 0x60; + dev->pci_conf[2][0x43] = 0x97; + dev->pci_conf[2][0x44] = 0x60; + dev->pci_conf[2][0x45] = 0x97; + dev->pci_conf[2][0x46] = 0x60; + dev->pci_conf[2][0x47] = 0x97; + + /* USB */ + if (dev->usb) { + dev->pci_conf[3][0x00] = 0x4a; + dev->pci_conf[3][0x01] = 0x10; + dev->pci_conf[3][0x02] = 0x30; + dev->pci_conf[3][0x03] = 0x02; + + dev->pci_conf[3][0x06] = 0x80; + dev->pci_conf[3][0x07] = 0x02; + + dev->pci_conf[3][0x09] = 0x10; + dev->pci_conf[3][0x0a] = 0x03; + dev->pci_conf[3][0x0b] = 0x0c; + + dev->pci_conf[3][0x0e] = 0x40; + } +} + + +static void +stpc_close(void *priv) +{ + stpc_t *dev = (stpc_t *) priv; + + stpc_log("STPC: close()\n"); + + free(dev); +} + + +static void * +stpc_init(const device_t *info) +{ + stpc_log("STPC: init()\n"); + + stpc_t *dev = (stpc_t *) malloc(sizeof(stpc_t)); + memset(dev, 0, sizeof(stpc_t)); + + dev->local = info->local; + + pci_add_card(0x0B, stpc_nb_read, stpc_nb_write, dev); + pci_add_card(0x0C, stpc_isab_read, stpc_isab_write, dev); + if (dev->local & STPC_IDE_ATLAS) + pci_add_card(0x0D, stpc_ide_read, stpc_ide_write, dev); + if (dev->local & STPC_USB) { + dev->usb = device_add(&usb_device); + pci_add_card(0x0E, stpc_usb_read, stpc_usb_write, dev); + } + + stpc_setup(dev); + stpc_reset(dev); + + smram[0].host_base = 0x000a0000; + smram[0].ram_base = 0x000a0000; + smram[0].size = 0x00020000; + + mem_mapping_set_addr(&ram_smram_mapping[0], smram[0].host_base, smram[0].size); + mem_mapping_set_exec(&ram_smram_mapping[0], ram + smram[0].ram_base); + + stpc_smram_map(0, smram[0].host_base, smram[0].size, 0); + stpc_smram_map(1, smram[0].host_base, smram[0].size, 1); + + device_add(&port_92_pci_device); + + return dev; +} + + +const device_t stpc_client_device = +{ + "STPC Client", + DEVICE_PCI, + STPC_NB_CLIENT | STPC_ISAB_CLIENT, + stpc_init, + stpc_close, + stpc_reset, + NULL, + NULL, + NULL, + NULL +}; + +const device_t stpc_consumer2_device = +{ + "STPC Consumer-II", + DEVICE_PCI, + STPC_ISAB_CONSUMER2, + stpc_init, + stpc_close, + stpc_reset, + NULL, + NULL, + NULL, + NULL +}; + +const device_t stpc_elite_device = +{ + "STPC Elite", + DEVICE_PCI, + 0, + stpc_init, + stpc_close, + stpc_reset, + NULL, + NULL, + NULL, + NULL +}; + +const device_t stpc_atlas_device = +{ + "STPC Atlas", + DEVICE_PCI, + STPC_IDE_ATLAS | STPC_USB, + stpc_init, + stpc_close, + stpc_reset, + NULL, + NULL, + NULL, + NULL +}; diff --git a/src/codegen_new/codegen_backend_x86.c b/src/codegen_new/codegen_backend_x86.c index 1e22caa2e..036e8a621 100644 --- a/src/codegen_new/codegen_backend_x86.c +++ b/src/codegen_new/codegen_backend_x86.c @@ -304,12 +304,20 @@ void codegen_backend_init() block_write_data = NULL; cpu_state.old_fp_control = 0; +#ifndef _MSC_VER asm( "fstcw %0\n" "stmxcsr %1\n" : "=m" (cpu_state.old_fp_control2), "=m" (cpu_state.old_fp_control) ); +#else + __asm + { + fstcw cpu_state.old_fp_control2 + stmxcsr cpu_state.old_fp_control + } +#endif cpu_state.trunc_fp_control = cpu_state.old_fp_control | 0x6000; } diff --git a/src/config.c b/src/config.c index 5d3962c6f..bbc672935 100644 --- a/src/config.c +++ b/src/config.c @@ -745,9 +745,9 @@ load_ports(void) char temp[512]; int c, d; - for (c = 0; c < 2; c++) { + for (c = 0; c < 4; c++) { sprintf(temp, "serial%d_enabled", c + 1); - serial_enabled[c] = !!config_get_int(cat, temp, 1); + serial_enabled[c] = !!config_get_int(cat, temp, (c >= 2) ? 0 : 1); } for (c = 0; c < 3; c++) { @@ -1352,6 +1352,8 @@ config_load(void) hdc_current = hdc_get_from_internal_name("none"); serial_enabled[0] = 1; serial_enabled[1] = 1; + serial_enabled[2] = 0; + serial_enabled[3] = 0; lpt_ports[0].enabled = 1; lpt_ports[1].enabled = 0; lpt_ports[2].enabled = 0; @@ -1521,7 +1523,7 @@ save_machine(void) if (fpu_type == 0) config_delete_var(cat, "fpu_type"); else - config_set_string(cat, "fpu_type", fpu_get_internal_name(machine, cpu_manufacturer, cpu, fpu_type)); + config_set_string(cat, "fpu_type", (char *) fpu_get_internal_name(machine, cpu_manufacturer, cpu, fpu_type)); if (mem_size == 4096) config_delete_var(cat, "mem_size"); @@ -1709,9 +1711,9 @@ save_ports(void) char temp[512]; int c, d; - for (c = 0; c < 2; c++) { + for (c = 0; c < 4; c++) { sprintf(temp, "serial%d_enabled", c + 1); - if (serial_enabled[c]) + if (((c < 2) && serial_enabled[c]) || ((c >= 2) && !serial_enabled[c])) config_delete_var(cat, temp); else config_set_int(cat, temp, serial_enabled[c]); diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c index 7cdd36ed4..b60ea5b21 100644 --- a/src/cpu/cpu.c +++ b/src/cpu/cpu.c @@ -399,10 +399,10 @@ cpu_set(void) hasfpu = (fpu_type != FPU_NONE); hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL); #if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86) - cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1); -#else - cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86); -#endif + cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx486DX2 || cpu_s->cpu_type == CPU_Cx486DX4 || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1); +#else + cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx486DX2 || cpu_s->cpu_type == CPU_Cx486DX4 || cpu_s->cpu_type == CPU_Cx5x86); +#endif cpu_16bitbus = (cpu_s->cpu_type == CPU_286 || cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC ); cpu_64bitbus = (cpu_s->cpu_type >= CPU_WINCHIP); @@ -935,6 +935,7 @@ cpu_set(void) case CPU_Cx486S: case CPU_Cx486DX: case CPU_Cx486DX2: + case CPU_Cx486DX4: #ifdef USE_DYNAREC x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); #else diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h index cf99c0ae1..3aaed7075 100644 --- a/src/cpu/cpu.h +++ b/src/cpu/cpu.h @@ -132,15 +132,19 @@ extern CPU cpus_Am386SX[]; extern CPU cpus_Am386DX[]; extern CPU cpus_486SLC[]; extern CPU cpus_486DLC[]; -extern CPU cpus_IBM386SLC[]; -extern CPU cpus_IBM486SLC[]; -extern CPU cpus_IBM486BL[]; -extern CPU cpus_i486S1[]; +extern CPU cpus_IBM386SLC[]; +extern CPU cpus_IBM486SLC[]; +extern CPU cpus_IBM486BL[]; +extern CPU cpus_i486S1[]; extern CPU cpus_Am486S1[]; extern CPU cpus_Cx486S1[]; extern CPU cpus_i486[]; extern CPU cpus_Am486[]; extern CPU cpus_Cx486[]; +#if defined(DEV_BRANCH) && defined(USE_STPC) +extern CPU cpus_STPC6675[]; +extern CPU cpus_STPC133[]; +#endif extern CPU cpus_WinChip[]; extern CPU cpus_WinChip_SS7[]; extern CPU cpus_Pentium5V[]; @@ -156,10 +160,8 @@ extern CPU cpus_K56_SS7[]; #if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86) extern CPU cpus_6x863V[]; extern CPU cpus_6x86[]; -#ifdef USE_NEW_DYNAREC extern CPU cpus_6x86SS7[]; #endif -#endif extern CPU cpus_Cyrix3[]; extern CPU cpus_PentiumPro[]; extern CPU cpus_PentiumII66[]; @@ -293,10 +295,10 @@ typedef struct { #ifdef USE_NEW_DYNAREC uint32_t old_fp_control, new_fp_control; -#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ +#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 uint16_t old_fp_control2, new_fp_control2; #endif -#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined __amd64__ +#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64 uint32_t trunc_fp_control; #endif #endif diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c index 71df19605..ca84055db 100644 --- a/src/cpu/cpu_table.c +++ b/src/cpu/cpu_table.c @@ -366,6 +366,20 @@ CPU cpus_Cx486[] = { {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }; +#if defined(DEV_BRANCH) && defined(USE_STPC) +/* All STPC timings and Cyrix CPUID values assumed. */ +CPU cpus_STPC6675[] = { + {"STPC 66", CPU_Cx486DX, fpus_internal, 66666666, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"STPC 75", CPU_Cx486DX, fpus_internal, 75000000, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_STPC133[] = { + {"STPC 133", CPU_Cx486DX2, fpus_internal, 133333333, 2.0, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif + #if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86) CPU cpus_6x863V[] = { /*Cyrix 6x86*/ diff --git a/src/device/serial.c b/src/device/serial.c index e5490d763..d8bf13280 100644 --- a/src/device/serial.c +++ b/src/device/serial.c @@ -684,9 +684,13 @@ serial_init(const device_t *info) dev->sd = &(serial_devices[next_inst]); dev->sd->serial = dev; serial_reset_port(dev); - if (next_inst || (info->flags & DEVICE_PCJR)) + if (next_inst == 3) + serial_setup(dev, SERIAL4_ADDR, SERIAL4_IRQ); + else if (next_inst == 2) + serial_setup(dev, SERIAL3_ADDR, SERIAL3_IRQ); + else if ((next_inst == 1) || (info->flags & DEVICE_PCJR)) serial_setup(dev, SERIAL2_ADDR, SERIAL2_IRQ); - else + else if (next_inst == 0) serial_setup(dev, SERIAL1_ADDR, SERIAL1_IRQ); /* Default to 1200,N,7. */ @@ -716,8 +720,17 @@ serial_standalone_init(void) { if (next_inst == 0) { device_add_inst(&i8250_device, 1); device_add_inst(&i8250_device, 2); - } else if (next_inst == 1) + device_add_inst(&i8250_device, 3); + device_add_inst(&i8250_device, 4); + } else if (next_inst == 1) { device_add_inst(&i8250_device, 2); + device_add_inst(&i8250_device, 3); + device_add_inst(&i8250_device, 4); + } else if (next_inst == 2) { + device_add_inst(&i8250_device, 3); + device_add_inst(&i8250_device, 4); + } else + device_add_inst(&i8250_device, 4); }; diff --git a/src/disk/hdc_ide_cmd640.c b/src/disk/hdc_ide_cmd640.c new file mode 100644 index 000000000..6e5353629 --- /dev/null +++ b/src/disk/hdc_ide_cmd640.c @@ -0,0 +1,462 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of the CMD PCI-0640B controller. + + * Authors: Miran Grca, + * + * Copyright 2020 Miran Grca. + */ +#include +#include +#include +#include +#include +#include +#define HAVE_STDARG_H +#include <86box/86box.h> +#include <86box/cdrom.h> +#include <86box/scsi_device.h> +#include <86box/scsi_cdrom.h> +#include <86box/dma.h> +#include <86box/io.h> +#include <86box/device.h> +#include <86box/keyboard.h> +#include <86box/mem.h> +#include <86box/pci.h> +#include <86box/pic.h> +#include <86box/timer.h> +#include <86box/hdc.h> +#include <86box/hdc_ide.h> +#include <86box/hdc_ide_sff8038i.h> +#include <86box/zip.h> + + +typedef struct +{ + uint8_t vlb_idx, id, + in_cfg, + regs[256]; + int slot, irq_mode[2], + irq_pin, irq_line; +} cmd640_t; + + +static int next_id = 0; + + +void +cmd640_set_irq(int channel, void *priv) +{ + cmd640_t *dev = (cmd640_t *) priv; + dev->regs[0x50] &= ~0x04; + dev->regs[0x50] |= (channel >> 4); + + channel &= 0x01; + if (dev->regs[0x50] & 0x04) { + if (dev->irq_mode[channel] == 1) + pci_set_irq(dev->slot, dev->irq_pin); + else + picint(1 << (14 + channel)); + } else { + if (dev->irq_mode[channel] == 1) + pci_clear_irq(dev->slot, dev->irq_pin); + else + picintc(1 << (14 + channel)); + } +} + + +static void +cmd640_ide_handlers(cmd640_t *dev) +{ + uint16_t main, side; + + ide_pri_disable(); + + if ((dev->regs[0x09] & 0x01) && (dev->regs[0x50] & 0x40)) { + main = (dev->regs[0x11] << 8) | (dev->regs[0x10] & 0xf8); + side = ((dev->regs[0x15] << 8) | (dev->regs[0x14] & 0xfc)) + 2; + } else { + main = 0x1f0; + side = 0x3f6; + } + + ide_set_base(0, main); + ide_set_side(0, side); + + if (dev->regs[0x04] & 0x01) + ide_pri_enable(); + + ide_sec_disable(); + + if ((dev->regs[0x09] & 0x04) && (dev->regs[0x50] & 0x40)) { + main = (dev->regs[0x19] << 8) | (dev->regs[0x18] & 0xf8); + side = ((dev->regs[0x1d] << 8) | (dev->regs[0x1c] & 0xfc)) + 2; + } else { + main = 0x170; + side = 0x376; + } + + ide_set_base(1, main); + ide_set_side(1, side); + + if ((dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08)) + ide_sec_enable(); +} + + +static void +cmd640_common_write(int addr, uint8_t val, cmd640_t *dev) +{ + switch (addr) { + case 0x51: + dev->regs[addr] = val; + cmd640_ide_handlers(dev); + break; + case 0x52: case 0x54: case 0x56: case 0x58: + case 0x59: + dev->regs[addr] = val; + break; + case 0x53: case 0x55: + dev->regs[addr] = val & 0xc0; + break; + case 0x57: + dev->regs[addr] = val & 0xdc; + break; + } +} + + +static void +cmd640_vlb_write(uint16_t addr, uint8_t val, void *priv) +{ + cmd640_t *dev = (cmd640_t *) priv; + + addr &= 0x00ff; + + switch (addr) { + case 0x0078: + if (dev->in_cfg) + dev->vlb_idx = val; + else if ((dev->regs[0x50] & 0x80) && (val == dev->id)) + dev->in_cfg = 1; + break; + case 0x007c: + cmd640_common_write(dev->vlb_idx, val, dev); + if (dev->regs[0x50] & 0x80) + dev->in_cfg = 0; + break; + } +} + + +static void +cmd640_vlb_writew(uint16_t addr, uint16_t val, void *priv) +{ + cmd640_vlb_write(addr, val & 0xff, priv); + cmd640_vlb_write(addr + 1, val >> 8, priv); +} + + +static void +cmd640_vlb_writel(uint16_t addr, uint32_t val, void *priv) +{ + cmd640_vlb_writew(addr, val & 0xffff, priv); + cmd640_vlb_writew(addr + 2, val >> 16, priv); +} + + +static uint8_t +cmd640_vlb_read(uint16_t addr, void *priv) +{ + uint8_t ret = 0xff; + cmd640_t *dev = (cmd640_t *) priv; + + addr &= 0x00ff; + + switch (addr) { + case 0x0078: + if (dev->in_cfg) + ret = dev->vlb_idx; + break; + case 0x007c: + ret = dev->regs[dev->vlb_idx]; + if (dev->vlb_idx == 0x50) + dev->regs[0x50] &= ~0x04; + if (dev->regs[0x50] & 0x80) + dev->in_cfg = 0; + break; + } + + return ret; +} + + +static uint16_t +cmd640_vlb_readw(uint16_t addr, void *priv) +{ + uint16_t ret = 0xffff; + + ret = cmd640_vlb_read(addr, priv); + ret |= (cmd640_vlb_read(addr + 1, priv) << 8); + + return ret; +} + + +static uint32_t +cmd640_vlb_readl(uint16_t addr, void *priv) +{ + uint32_t ret = 0xffffffff; + + ret = cmd640_vlb_readw(addr, priv); + ret |= (cmd640_vlb_readw(addr + 2, priv) << 16); + + return ret; +} + + +static void +cmd640_pci_write(int func, int addr, uint8_t val, void *priv) +{ + cmd640_t *dev = (cmd640_t *) priv; + + if (func == 0x00) switch (addr) { + case 0x04: + dev->regs[addr] = (val & 0x41); + cmd640_ide_handlers(dev); + break; + case 0x07: + dev->regs[addr] &= ~(val & 0x80); + break; + case 0x09: + if ((dev->regs[addr] & 0x0a) == 0x0a) { + dev->regs[addr] = (dev->regs[addr] & 0x0a) | (val & 0x05); + dev->irq_mode[0] = !!(val & 0x01); + dev->irq_mode[1] = !!(val & 0x04); + cmd640_ide_handlers(dev); + } + break; + case 0x10: + if (dev->regs[0x50] & 0x40) { + dev->regs[0x10] = (val & 0xf8) | 1; + cmd640_ide_handlers(dev); + } + break; + case 0x11: + if (dev->regs[0x50] & 0x40) { + dev->regs[0x11] = val; + cmd640_ide_handlers(dev); + } + break; + case 0x14: + if (dev->regs[0x50] & 0x40) { + dev->regs[0x14] = (val & 0xfc) | 1; + cmd640_ide_handlers(dev); + } + break; + case 0x15: + if (dev->regs[0x50] & 0x40) { + dev->regs[0x15] = val; + cmd640_ide_handlers(dev); + } + break; + case 0x18: + if (dev->regs[0x50] & 0x40) { + dev->regs[0x18] = (val & 0xf8) | 1; + cmd640_ide_handlers(dev); + } + break; + case 0x19: + if (dev->regs[0x50] & 0x40) { + dev->regs[0x19] = val; + cmd640_ide_handlers(dev); + } + break; + case 0x1c: + if (dev->regs[0x50] & 0x40) { + dev->regs[0x1c] = (val & 0xfc) | 1; + cmd640_ide_handlers(dev); + } + break; + case 0x1d: + if (dev->regs[0x50] & 0x40) { + dev->regs[0x1d] = val; + cmd640_ide_handlers(dev); + } + break; + default: + cmd640_common_write(addr, val, dev); + break; + } +} + + +static uint8_t +cmd640_pci_read(int func, int addr, void *priv) +{ + cmd640_t *dev = (cmd640_t *) priv; + uint8_t ret = 0xff; + + if (func == 0x00) { + ret = dev->regs[addr]; + if (addr == 0x50) + dev->regs[0x50] &= ~0x04; + } + + return ret; +} + + +static void +cmd640_reset(void *p) +{ + int i = 0; + + for (i = 0; i < CDROM_NUM; i++) { + if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && + (cdrom[i].ide_channel < 4) && cdrom[i].priv) + scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv); + } + for (i = 0; i < ZIP_NUM; i++) { + if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && + (zip_drives[i].ide_channel < 4) && zip_drives[i].priv) + zip_reset((scsi_common_t *) zip_drives[i].priv); + } + + cmd640_set_irq(0x00, p); + cmd640_set_irq(0x01, p); +} + + +static void +cmd640_close(void *priv) +{ + cmd640_t *dev = (cmd640_t *) priv; + + free(dev); + + next_id = 0; +} + + +static void * +cmd640_init(const device_t *info) +{ + cmd640_t *dev = (cmd640_t *) malloc(sizeof(cmd640_t)); + memset(dev, 0x00, sizeof(cmd640_t)); + + dev->id = next_id | 0x60; + + dev->regs[0x50] = 0x02; /* Revision 02 */ + dev->regs[0x50] |= (next_id << 3); /* Device ID: 00 = 60h, 01 = 61h, 10 = 62h, 11 = 63h */ + + dev->regs[0x59] = 0x40; + + if (info->flags & DEVICE_PCI) { + if (info->local == 0x0a) { + dev->regs[0x50] |= 0x40; /* Enable Base address register R/W; + If 0, they return 0 and are read-only 8 */ + } + + dev->regs[0x00] = 0x95; /* CMD */ + dev->regs[0x01] = 0x10; + dev->regs[0x02] = 0x40; /* PCI-0640B */ + dev->regs[0x03] = 0x06; + dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */ + dev->regs[0x08] = 0x02; /* Revision 02 */ + dev->regs[0x09] = info->local; /* Programming interface */ + dev->regs[0x0a] = 0x01; /* IDE controller */ + dev->regs[0x0b] = 0x01; /* Mass storage controller */ + + /* Base addresses (1F0, 3F4, 170, 374) */ + if (dev->regs[0x50] & 0x40) { + dev->regs[0x10] = 0xf1; dev->regs[0x11] = 0x01; + dev->regs[0x14] = 0xf5; dev->regs[0x15] = 0x03; + dev->regs[0x18] = 0x71; dev->regs[0x19] = 0x01; + dev->regs[0x1c] = 0x75; dev->regs[0x1d] = 0x03; + } + + dev->regs[0x3c] = 0x14; /* IRQ 14 */ + dev->regs[0x3d] = 0x01; /* INTA */ + + device_add(&ide_vlb_2ch_device); + + dev->slot = pci_add_card(PCI_ADD_NORMAL, cmd640_pci_read, cmd640_pci_write, dev); + dev->irq_mode[0] = dev->irq_mode[1] = 0; + dev->irq_pin = PCI_INTA; + dev->irq_line = 14; + + ide_set_bus_master(0, NULL, cmd640_set_irq, dev); + ide_set_bus_master(1, NULL, cmd640_set_irq, dev); + + /* The CMD PCI-0640B IDE controller has no DMA capability, + so set our devices IDE devices to force ATA-3 (no DMA). */ + ide_board_set_force_ata3(0, 1); + ide_board_set_force_ata3(1, 1); + + ide_pri_disable(); + } else if (info->flags & DEVICE_VLB) { + if (info->local == 0x0078) + dev->regs[0x50] |= 0x20; /* 0 = 178h, 17Ch; 1 = 078h, 07Ch */ + /* If bit 7 is 1, then device ID has to be written on port x78h before + accessing the configuration registers */ + dev->in_cfg = 1; /* Configuration register are accessible */ + + device_add(&ide_pci_2ch_device); + + io_sethandler(0x0078, 0x0008, + cmd640_vlb_read, cmd640_vlb_readw, cmd640_vlb_readl, + cmd640_vlb_write, cmd640_vlb_writew, cmd640_vlb_writel, + dev); + } + + ide_sec_disable(); + + next_id++; + + return dev; +} + + +const device_t ide_cmd640_vlb_device = { + "CMD PCI-0640B VLB", + DEVICE_VLB, + 0x0078, + cmd640_init, cmd640_close, NULL, + NULL, NULL, NULL, + NULL +}; + +const device_t ide_cmd640_vlb_178_device = { + "CMD PCI-0640B VLB (Port 178h)", + DEVICE_VLB, + 0x0178, + cmd640_init, cmd640_close, NULL, + NULL, NULL, NULL, + NULL +}; + +const device_t ide_cmd640_pci_device = { + "CMD PCI-0640B PCI", + DEVICE_PCI, + 0x0a, + cmd640_init, cmd640_close, cmd640_reset, + NULL, NULL, NULL, + NULL +}; + +const device_t ide_cmd640_pci_legacy_only_device = { + "CMD PCI-0640B PCI (Legacy Mode Only)", + DEVICE_PCI, + 0x00, + cmd640_init, cmd640_close, cmd640_reset, + NULL, NULL, NULL, + NULL +}; diff --git a/src/disk/hdc_ide_opti611.c b/src/disk/hdc_ide_opti611.c new file mode 100644 index 000000000..19c298396 --- /dev/null +++ b/src/disk/hdc_ide_opti611.c @@ -0,0 +1,322 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of the OPTi 82C611/611A VLB IDE controller. + + * Authors: Miran Grca, + * + * Copyright 2020 Miran Grca. + */ +#include +#include +#include +#include +#include +#include +#define HAVE_STDARG_H +#include <86box/86box.h> +#include "cpu.h" +#include <86box/timer.h> +#include <86box/io.h> +#include <86box/device.h> +#include <86box/keyboard.h> +#include <86box/mem.h> +#include <86box/hdc.h> +#include <86box/hdc_ide.h> + + +typedef struct +{ + uint8_t tries, + in_cfg, cfg_locked, + regs[19]; +} opti611_t; + + +static void opti611_ide_handler(opti611_t *dev); + + +static void +opti611_cfg_write(uint16_t addr, uint8_t val, void *priv) +{ + opti611_t *dev = (opti611_t *) priv; + + addr &= 0x0007; + + switch (addr) { + case 0x0000: + case 0x0001: + dev->regs[((dev->regs[0x06] & 0x01) << 4) + addr] = val; + break; + case 0x0002: + dev->regs[0x12] = (val & 0xc1) | 0x02; + if (val & 0xc0) { + dev->in_cfg = 0; + opti611_ide_handler(dev); + } + if (val & 0x40) + dev->cfg_locked = 1; + break; + case 0x0003: + dev->regs[0x03] = (val & 0xdf); + break; + case 0x0005: + dev->regs[0x05] = (dev->regs[0x05] & 0x78) | (val & 0x87); + break; + case 0x0006: + dev->regs[0x06] = val; + break; + } +} + + +static void +opti611_cfg_writew(uint16_t addr, uint16_t val, void *priv) +{ + opti611_cfg_write(addr, val & 0xff, priv); + opti611_cfg_write(addr + 1, val >> 8, priv); +} + + +static void +opti611_cfg_writel(uint16_t addr, uint32_t val, void *priv) +{ + opti611_cfg_writew(addr, val & 0xffff, priv); + opti611_cfg_writew(addr + 2, val >> 16, priv); +} + + +static uint8_t +opti611_cfg_read(uint16_t addr, void *priv) +{ + uint8_t ret = 0xff; + opti611_t *dev = (opti611_t *) priv; + + addr &= 0x0007; + + switch (addr) { + case 0x0000: + case 0x0001: + ret = dev->regs[((dev->regs[0x06] & 0x01) << 4) + addr]; + break; + case 0x0002: + ret = ((!!in_smm) << 7); + if (ret & 0x80) + ret |= (dev->regs[addr] & 0x7f); + break; + case 0x0003: case 0x0004: case 0x0005: case 0x0006: + ret = dev->regs[addr]; + break; + } + + return ret; +} + + +static uint16_t +opti611_cfg_readw(uint16_t addr, void *priv) +{ + uint16_t ret = 0xffff; + + ret = opti611_cfg_read(addr, priv); + ret |= (opti611_cfg_read(addr + 1, priv) << 8); + + return ret; +} + + +static uint32_t +opti611_cfg_readl(uint16_t addr, void *priv) +{ + uint32_t ret = 0xffffffff; + + ret = opti611_cfg_readw(addr, priv); + ret |= (opti611_cfg_readw(addr + 2, priv) << 16); + + return ret; +} + + +static void +opti611_ide_write(uint16_t addr, uint8_t val, void *priv) +{ + opti611_t *dev = (opti611_t *) priv; + + uint8_t smia9 = (!!(addr & 0x0200)) << 5; + uint8_t smia2 = (!!(addr & 0x0004)) << 4; + uint8_t smibe = (addr & 0x0003); + + if (dev->regs[0x03] & 0x02) { + smi_line = 1; + dev->regs[0x02] = smia9 | smia2 | smibe; + dev->regs[0x04] = val; + } +} + + +static void +opti611_ide_writew(uint16_t addr, uint16_t val, void *priv) +{ + opti611_t *dev = (opti611_t *) priv; + + uint8_t smia9 = (!!(addr & 0x0200)) << 5; + uint8_t smia2 = (!!(addr & 0x0004)) << 4; + uint8_t smibe = (addr & 0x0002) | 0x0001; + + if (dev->regs[0x03] & 0x02) { + smi_line = 1; + dev->regs[0x02] = smia9 | smia2 | smibe; + dev->regs[0x04] = 0x00; + } +} + + +static void +opti611_ide_writel(uint16_t addr, uint32_t val, void *priv) +{ + opti611_t *dev = (opti611_t *) priv; + + uint8_t smia9 = (!!(addr & 0x0200)) << 5; + uint8_t smia2 = (!!(addr & 0x0004)) << 4; + + if (dev->regs[0x03] & 0x02) { + smi_line = 1; + dev->regs[0x02] = smia9 | smia2 | 0x0003; + dev->regs[0x04] = 0x00; + } +} + + +static uint8_t +opti611_ide_read(uint16_t addr, void *priv) +{ + opti611_t *dev = (opti611_t *) priv; + + uint8_t smia9 = (!!(addr & 0x0200)) << 5; + uint8_t smia2 = (!!(addr & 0x0004)) << 4; + uint8_t smibe = (addr & 0x0003); + + if (dev->regs[0x03] & 0x02) { + smi_line = 1; + dev->regs[0x02] = smia9 | smia2 | smibe; + dev->regs[0x04] = 0x00; + } + + return 0xff; +} + + +static uint16_t +opti611_ide_readw(uint16_t addr, void *priv) +{ + opti611_t *dev = (opti611_t *) priv; + + uint8_t smia9 = (!!(addr & 0x0200)) << 5; + uint8_t smia2 = (!!(addr & 0x0004)) << 4; + uint8_t smibe = (addr & 0x0002) | 0x0001; + + if ((addr & 0x0007) == 0x0001) { + dev->tries = (dev->tries + 1) & 0x01; + if ((dev->tries == 0x00) && !dev->cfg_locked) { + dev->in_cfg = 1; + opti611_ide_handler(dev); + } + } + + if (dev->regs[0x03] & 0x02) { + smi_line = 1; + dev->regs[0x02] = smia9 | smia2 | smibe; + dev->regs[0x04] = 0x00; + } + + return 0xffff; +} + + +static uint32_t +opti611_ide_readl(uint16_t addr, void *priv) +{ + opti611_t *dev = (opti611_t *) priv; + + uint8_t smia9 = (!!(addr & 0x0200)) << 5; + uint8_t smia2 = (!!(addr & 0x0004)) << 4; + + if (dev->regs[0x03] & 0x02) { + smi_line = 1; + dev->regs[0x02] = smia9 | smia2 | 0x0003; + dev->regs[0x04] = 0x00; + } + + return 0xffffffff; +} + + +static void +opti611_ide_handler(opti611_t *dev) +{ + ide_pri_disable(); + io_removehandler(0x01f0, 0x0007, + opti611_ide_read, opti611_ide_readw, opti611_ide_readl, + opti611_ide_write, opti611_ide_writew, opti611_ide_writel, + dev); + io_removehandler(0x01f0, 0x0007, + opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl, + opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel, + dev); + + if (dev->in_cfg && !dev->cfg_locked) { + io_sethandler(0x01f0, 0x0007, + opti611_cfg_read, opti611_cfg_readw, opti611_cfg_readl, + opti611_cfg_write, opti611_cfg_writew, opti611_cfg_writel, + dev); + } else { + if (dev->regs[0x03] & 0x01) + ide_pri_enable(); + io_sethandler(0x01f0, 0x0007, + opti611_ide_read, opti611_ide_readw, opti611_ide_readl, + opti611_ide_write, opti611_ide_writew, opti611_ide_writel, + dev); + } +} + + +static void +opti611_close(void *priv) +{ + opti611_t *dev = (opti611_t *) priv; + + free(dev); +} + + +static void * +opti611_init(const device_t *info) +{ + opti611_t *dev = (opti611_t *) malloc(sizeof(opti611_t)); + memset(dev, 0, sizeof(opti611_t)); + + dev->regs[0x12] = 0x80; + dev->regs[0x03] = 0x01; + dev->regs[0x05] = 0x20; + + device_add(&ide_vlb_device); + + opti611_ide_handler(dev); + + return dev; +} + + +const device_t ide_opti611_vlb_device = { + "OPTi 82C611/82C611A VLB", + 0, + 0, + opti611_init, opti611_close, NULL, + NULL, NULL, NULL, + NULL +}; diff --git a/src/include/86box/86box.h b/src/include/86box/86box.h index e97967cec..11c250201 100644 --- a/src/include/86box/86box.h +++ b/src/include/86box/86box.h @@ -21,8 +21,8 @@ /* Configuration values. */ -#define SERIAL_MAX 2 -#define PARALLEL_MAX 1 +#define SERIAL_MAX 4 +#define PARALLEL_MAX 3 #define SCREEN_RES_X 640 #define SCREEN_RES_Y 480 diff --git a/src/include/86box/chipset.h b/src/include/86box/chipset.h index a73c81726..a7f313627 100644 --- a/src/include/86box/chipset.h +++ b/src/include/86box/chipset.h @@ -84,6 +84,14 @@ extern const device_t sis_85c496_ls486e_device; extern const device_t sis_85c50x_device; #endif +/* ST */ +#if defined(DEV_BRANCH) && defined(USE_STPC) +extern const device_t stpc_client_device; +extern const device_t stpc_consumer2_device; +extern const device_t stpc_elite_device; +extern const device_t stpc_atlas_device; +#endif + /* VIA */ extern const device_t via_vpx_device; extern const device_t via_vp3_device; diff --git a/src/include/86box/hdc.h b/src/include/86box/hdc.h index 10bf2885a..df83c33bd 100644 --- a/src/include/86box/hdc.h +++ b/src/include/86box/hdc.h @@ -13,8 +13,8 @@ * Authors: Miran Grca, * Fred N. van Kempen, * - * Copyright 2016-2019 Miran Grca. - * Copyright 2017-2019 Fred N. van Kempen. + * Copyright 2016-2020 Miran Grca. + * Copyright 2017-2020 Fred N. van Kempen. */ #ifndef EMU_HDC_H # define EMU_HDC_H @@ -50,6 +50,13 @@ extern const device_t ide_vlb_2ch_device; /* vlb_ide_2ch */ extern const device_t ide_pci_device; /* pci_ide */ extern const device_t ide_pci_2ch_device; /* pci_ide_2ch */ +extern const device_t ide_cmd640_vlb_device; /* CMD PCI-640B VLB */ +extern const device_t ide_cmd640_vlb_178_device; /* CMD PCI-640B VLB (Port 178h) */ +extern const device_t ide_cmd640_pci_device; /* CMD PCI-640B PCI */ +extern const device_t ide_cmd640_pci_legacy_only_device; /* CMD PCI-640B PCI (Legacy Mode Only) */ + +extern const device_t ide_opti611_vlb_device; /* OPTi 82c611/611A VLB */ + extern const device_t ide_ter_device; extern const device_t ide_qua_device; diff --git a/src/include/86box/machine.h b/src/include/86box/machine.h index 2899658c7..918d007f5 100644 --- a/src/include/86box/machine.h +++ b/src/include/86box/machine.h @@ -282,6 +282,12 @@ extern int machine_at_4dps_init(const machine_t *); extern int machine_at_alfredo_init(const machine_t *); extern int machine_at_486sp3g_init(const machine_t *); extern int machine_at_486ap4_init(const machine_t *); +#if defined(DEV_BRANCH) && defined(USE_STPC) +extern int machine_at_itoxstar_init(const machine_t *); +extern int machine_at_arb1479_init(const machine_t *); +extern int machine_at_pcm9340_init(const machine_t *); +extern int machine_at_pcm5330_init(const machine_t *); +#endif #ifdef EMU_DEVICE_H extern const device_t *at_acera1g_get_device(void); diff --git a/src/include/86box/resource.h b/src/include/86box/resource.h index afcb33e5b..f3f962404 100644 --- a/src/include/86box/resource.h +++ b/src/include/86box/resource.h @@ -164,9 +164,11 @@ #define IDC_COMBO_LPT3 1112 #define IDC_CHECK_SERIAL1 1113 #define IDC_CHECK_SERIAL2 1114 -#define IDC_CHECK_PARALLEL1 1115 -#define IDC_CHECK_PARALLEL2 1116 -#define IDC_CHECK_PARALLEL3 1117 +#define IDC_CHECK_SERIAL3 1115 +#define IDC_CHECK_SERIAL4 1116 +#define IDC_CHECK_PARALLEL1 1117 +#define IDC_CHECK_PARALLEL2 1118 +#define IDC_CHECK_PARALLEL3 1119 #define IDC_OTHER_PERIPH 1120 /* other periph config */ #define IDC_COMBO_SCSI 1121 diff --git a/src/include/86box/serial.h b/src/include/86box/serial.h index 90159cfae..37cb9b179 100644 --- a/src/include/86box/serial.h +++ b/src/include/86box/serial.h @@ -32,6 +32,10 @@ #define SERIAL1_IRQ 4 #define SERIAL2_ADDR 0x02f8 #define SERIAL2_IRQ 3 +#define SERIAL3_ADDR 0x03e8 +#define SERIAL3_IRQ 4 +#define SERIAL4_ADDR 0x02e8 +#define SERIAL4_IRQ 3 struct serial_device_s; diff --git a/src/include/86box/sio.h b/src/include/86box/sio.h index cb38a9e53..29ab81fa6 100644 --- a/src/include/86box/sio.h +++ b/src/include/86box/sio.h @@ -40,8 +40,10 @@ extern const device_t w83877f_president_device; extern const device_t w83877tf_device; extern const device_t w83877tf_acorp_device; extern const device_t w83977f_device; +extern const device_t w83977f_370_device; extern const device_t w83977tf_device; extern const device_t w83977ef_device; +extern const device_t w83977ef_370_device; #endif /*EMU_SIO_H*/ diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index 9876fd498..90e1ac223 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -40,6 +40,7 @@ #include <86box/video.h> #include <86box/flash.h> #include <86box/scsi_ncr53c8xx.h> +#include <86box/hwm.h> #include <86box/machine.h> int @@ -610,3 +611,138 @@ machine_at_486ap4_init(const machine_t *model) return ret; } + + +#if defined(DEV_BRANCH) && defined(USE_STPC) +int +machine_at_itoxstar_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/itoxstar/stara.rom", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x1F, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&w83977f_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&stpc_client_device); + device_add(&ide_vlb_device); + device_add(&sst_flash_29ee020_device); + + hwm_values_t machine_hwm = { + { /* fan speeds (incorrect divisor for some reason) */ + 3000, /* Chassis */ + 3000 /* CPU */ + }, { /* temperatures */ + 30, /* Chassis */ + 30 /* CPU */ + }, { /* voltages */ + 0, /* unused */ + 0, /* unused */ + 3300, /* Vio */ + RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */ + RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */ + RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */ + RESISTOR_DIVIDER(5000, 1, 2) /* -5V (divider values bruteforced) */ + } + }; + hwm_set_values(machine_hwm); + device_add(&w83781d_device); + + return ret; +} + + +int +machine_at_arb1479_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/arb1479/1479a.rom", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x1F, PCI_CARD_NORMAL, 1, 0, 0, 0); + pci_register_slot(0x1E, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x1D, PCI_CARD_NORMAL, 3, 4, 1, 2); + device_add(&w83977f_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&stpc_consumer2_device); + device_add(&ide_vlb_2ch_device); + device_add(&sst_flash_29ee020_device); + + return ret; +} + + +int +machine_at_pcm9340_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/pcm9340/9340v110.bin", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x1D, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x1E, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x1F, PCI_CARD_NORMAL, 2, 3, 4, 1); + device_add(&w83977f_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&stpc_elite_device); + device_add(&ide_vlb_device); + device_add(&sst_flash_29ee020_device); + + return ret; +} + + +int +machine_at_pcm5330_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/pcm5330/5330_13b.bin", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x0B, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x0C, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x0D, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_SPECIAL, 0, 0, 0, 0); + device_add(&w83977f_370_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&stpc_atlas_device); + device_add(&ide_vlb_device); + device_add(&sst_flash_29ee020_device); + + return ret; +} +#endif diff --git a/src/machine/m_at_socket4_5.c b/src/machine/m_at_socket4_5.c index 5fa8c341c..f7287a093 100644 --- a/src/machine/m_at_socket4_5.c +++ b/src/machine/m_at_socket4_5.c @@ -53,8 +53,8 @@ machine_at_excalibur_init(const machine_t *model) machine_at_common_init(model); - device_add(&ide_vlb_device); device_add(&opti5x7_device); + device_add(&ide_opti611_vlb_device); device_add(&fdc37c661_device); device_add(&keyboard_at_ami_device); @@ -160,6 +160,38 @@ machine_at_valuepointp60_init(const machine_t *model) } #endif + +int +machine_at_pb502r_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear_combined(L"roms/machines/revenge/1009af2_.bio", + L"roms/machines/revenge/1009af2_.bi1", 0x1c000, 128); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x01, PCI_CARD_SPECIAL, 0, 0, 0, 0); + pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4); + pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + device_add(&i430lx_device); + device_add(&keyboard_ps2_pci_device); + device_add(&sio_device); + device_add(&ide_cmd640_pci_device); + device_add(&fdc37c665_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + + int machine_at_opti560l_init(const machine_t *model) { @@ -182,14 +214,15 @@ machine_at_opti560l_init(const machine_t *model) pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4); pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); device_add(&i430lx_device); - device_add(&keyboard_ps2_intel_ami_pci_device); + device_add(&keyboard_ps2_pci_device); device_add(&sio_device); device_add(&fdc37c665_device); - device_add(&intel_flash_bxt_ami_device); + device_add(&intel_flash_bxt_device); return ret; } + #if defined(DEV_BRANCH) && defined(USE_DELLXP60) int machine_at_dellxp60_init(const machine_t *model) // Doesn't like the regular SMC 665 @@ -213,15 +246,16 @@ machine_at_dellxp60_init(const machine_t *model) // Doesn't like the regular SMC pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4); pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); device_add(&i430lx_device); - device_add(&keyboard_ps2_intel_ami_pci_device); + device_add(&keyboard_ps2_pci_device); device_add(&sio_device); device_add(&fdc37c665_device); - device_add(&intel_flash_bxt_ami_device); + device_add(&intel_flash_bxt_device); return ret; } #endif + int machine_at_p5mp3_init(const machine_t *model) { @@ -252,6 +286,7 @@ machine_at_p5mp3_init(const machine_t *model) return ret; } + int machine_at_586mc1_init(const machine_t *model) { diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 117b850a0..01524ead3 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -171,10 +171,11 @@ const machine_t machines[] = { { "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL }, { "[NEAT] Goldstar 386", "goldstar386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_goldstar386_init, NULL }, { "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL }, + { "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL }, { "[Intel 82335] ADI 386SX", "adi386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_adi386sx_init, NULL }, { "[OPTi 291] DTK Award 386SX", "awardsx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_awardsx_init, NULL }, - + /* 386SX machines which utilize the MCA bus */ { "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL }, @@ -195,14 +196,14 @@ const machine_t machines[] = { { "[MCA] IBM PS/2 model 80", "ibmps2_m80", MACHINE_TYPE_386DX, {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 12, 1, 63, machine_ps2_model_80_init, NULL }, /* 486 machines with just the ISA slot */ - { "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 4, 36, 1, 127, machine_at_pb410a_init, NULL }, + { "[ACC 2168] Packard Bell PB410A", "pb410a", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 4, 36, 1, 127, machine_at_pb410a_init, NULL }, /* 486 machines */ - { "[OPTi 283] RYC Leopard LX", "rycleopardlx", MACHINE_TYPE_486, {{"IBM", cpus_IBM486SLC}, {"", NULL}, {"", NULL},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_rycleopardlx_init, NULL }, - { "[OPTi 495] Award 486 clone", "award486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL }, + { "[OPTi 283] RYC Leopard LX", "rycleopardlx", MACHINE_TYPE_486, {{"IBM", cpus_IBM486SLC}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_rycleopardlx_init, NULL }, + { "[OPTi 495] Award 486 clone", "award486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL }, { "[OPTi 495] MR 486 clone", "mr486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL }, { "[OPTi 495] Dataexpert SX495 (486)", "ami486", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL }, - { "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT, 1, 64, 1, 127, machine_at_403tg_init, NULL }, + { "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT, 1, 64, 1, 127, machine_at_403tg_init, NULL }, { "[SiS 471] ASUS VL/I-486SV2G (GX4)", "vli486sv2g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_vli486sv2g_init, NULL }, { "[SiS 471] AMI 486 Clone", "ami471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_ami471_init, NULL }, #if defined(DEV_BRANCH) && defined(USE_WIN471) @@ -210,10 +211,10 @@ const machine_t machines[] = { #endif { "[SiS 471] DTK PKM-0038S E-2", "dtk486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_dtk486_init, NULL }, { "[SiS 471] Phoenix SiS 471", "px471", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_px471_init, NULL }, - { "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_PS2, 4, 36, 1, 127, machine_at_acera1g_init, at_acera1g_get_device }, + { "[ALi M1429G] Acer A1G", "acera1g", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_PS2, 4, 36, 1, 127, machine_at_acera1g_init, at_acera1g_get_device }, { "[ALi M1429] Olystar LIL1429", "ali1429", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_ali1429_init, NULL }, { "[ALi M1429] AMI WinBIOS 486", "win486", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_winbios1429_init, NULL }, - { "[VLSI 82c480] IBM PS/1 model 2133", "ibmps1_2133", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI | MACHINE_VIDEO, 1, 64, 1, 127, machine_ps1_m2133_init, ps1_m2133_get_device }, + { "[VLSI 82C480] IBM PS/1 model 2133", "ibmps1_2133", MACHINE_TYPE_486, {{"Intel", cpus_i486S1}, {"AMD", cpus_Am486S1}, {"Cyrix", cpus_Cx486S1},{"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_NONMI | MACHINE_VIDEO, 1, 64, 1, 127, machine_ps1_m2133_init, ps1_m2133_get_device }, /* 486 machines with utilize the MCA bus */ #if defined(DEV_BRANCH) && defined(USE_PS2M70T4) @@ -227,6 +228,12 @@ const machine_t machines[] = { { "[SiS 496] Lucky Star LS-486E", "ls486e", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 255, machine_at_ls486e_init, NULL }, { "[SiS 496] Rise Computer R418", "r418", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 255, machine_at_r418_init, NULL }, { "[SiS 496] Zida Tomato 4DP", "4dps", MACHINE_TYPE_486, {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 255, machine_at_4dps_init, NULL }, +#if defined(DEV_BRANCH) && defined(USE_STPC) + { "[STPC Client] ITOX STAR", "itoxstar", MACHINE_TYPE_486, {{"ST", cpus_STPC6675}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_itoxstar_init, NULL }, + { "[STPC Consumer-II] Acrosser AR-B1479", "arb1479", MACHINE_TYPE_486, {{"ST", cpus_STPC133}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 32, 160, 8, 255, machine_at_arb1479_init, NULL }, + { "[STPC Elite] Advantech PCM-9340", "pcm9340", MACHINE_TYPE_486, {{"ST", cpus_STPC133}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 32, 32, 0, 255, machine_at_pcm9340_init, NULL }, + { "[STPC Atlas] AAEON PCM-5330", "pcm5330", MACHINE_TYPE_486, {{"ST", cpus_STPC133}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 64, 64, 0, 255, machine_at_pcm5330_init, NULL }, +#endif /* Socket 4 machines */ /* OPTi 596/597 */ @@ -238,12 +245,15 @@ const machine_t machines[] = { { "[i430LX] IBM PS/ValuePoint P60", "valuepointp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_valuepointp60_init, NULL }, #endif { "[i430LX] Intel Premiere/PCI", "revenge", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_batman_init, NULL }, - { "[i430LX] Dell OptiPlex 560L", "opti560l", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_opti560l_init, NULL }, + { "[i430LX] Dell OptiPlex 560L", "opti560l", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_opti560l_init, NULL }, #if defined(DEV_BRANCH) && defined(USE_VPP60) - { "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_dellxp60_init, NULL }, + { "[i430LX] Dell Dimension XPS P60", "dellxp60", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_dellxp60_init, NULL }, #endif - { "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 192, 2, 127, machine_at_p5mp3_init, NULL }, + { "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 192, 2, 127, machine_at_p5mp3_init, NULL }, { "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL }, +#ifdef UNFINISHED + { "[i430LX] Packard Bell PB520R", "pb520r", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 2, 128, 2, 127, machine_at_pb520r_init, at_pb520r_get_device }, +#endif /* Socket 5 machines */ /* 430NX */ diff --git a/src/sio/sio_fdc37c661.c b/src/sio/sio_fdc37c661.c index 6936dff7c..c742b71d0 100644 --- a/src/sio/sio_fdc37c661.c +++ b/src/sio/sio_fdc37c661.c @@ -161,7 +161,6 @@ fdc37c661_write(uint16_t port, uint8_t val, void *priv) case 0: if (valxor & 0x10) fdc_handler(dev); - break; case 1: if (valxor & 3) diff --git a/src/sio/sio_w83977f.c b/src/sio/sio_w83977f.c index 469428fe6..6796acb2d 100644 --- a/src/sio/sio_w83977f.c +++ b/src/sio/sio_w83977f.c @@ -39,16 +39,20 @@ typedef struct { - uint8_t tries, regs[48], + uint8_t id, tries, + regs[48], dev_regs[256][208]; int locked, rw_locked, cur_reg, base_address, - type; + type, hefras; fdc_t *fdc; serial_t *uart[2]; } w83977f_t; +static int next_id = 0; + + static void w83977f_write(uint16_t port, uint8_t val, void *priv); static uint8_t w83977f_read(uint16_t port, void *priv); @@ -86,6 +90,9 @@ w83977f_fdc_handler(w83977f_t *dev) { uint16_t io_base = (dev->dev_regs[0][0x30] << 8) | dev->dev_regs[0][0x31]; + if (dev->id == 1) + return; + fdc_remove(dev->fdc); if ((dev->dev_regs[0][0x00] & 0x01) && (dev->regs[0x22] & 0x01) && (io_base >= 0x100) && (io_base <= 0xff8)) @@ -105,12 +112,21 @@ w83977f_lpt_handler(w83977f_t *dev) if (io_len == 8) io_mask = 0xff8; - lpt1_remove(); + if (dev->id == 1) { + lpt2_remove(); - if ((dev->dev_regs[1][0x00] & 0x01) && (dev->regs[0x22] & 0x08) && (io_base >= 0x100) && (io_base <= io_mask)) - lpt1_init(io_base); + if ((dev->dev_regs[1][0x00] & 0x01) && (dev->regs[0x22] & 0x08) && (io_base >= 0x100) && (io_base <= io_mask)) + lpt2_init(io_base); - lpt1_irq(dev->dev_regs[1][0x40] & 0x0f); + lpt2_irq(dev->dev_regs[1][0x40] & 0x0f); + } else { + lpt1_remove(); + + if ((dev->dev_regs[1][0x00] & 0x01) && (dev->regs[0x22] & 0x08) && (io_base >= 0x100) && (io_base <= io_mask)) + lpt1_init(io_base); + + lpt1_irq(dev->dev_regs[1][0x40] & 0x0f); + } } @@ -249,6 +265,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv) case 0xf0: switch (ld) { case 0x00: + if (dev->id == 1) + break; + if (valxor & 0x20) fdc_update_drv2en(dev->fdc, (val & 0x20) ? 0 : 1); if (valxor & 0x10) @@ -269,6 +288,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv) case 0xf1: switch (ld) { case 0x00: + if (dev->id == 1) + break; + if (valxor & 0xc0) fdc_update_boot_drive(dev->fdc, (val & 0xc0) >> 6); if (valxor & 0x0c) @@ -283,6 +305,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv) case 0xf2: switch (ld) { case 0x00: + if (dev->id == 1) + break; + if (valxor & 0xc0) fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6); if (valxor & 0x30) @@ -297,6 +322,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv) case 0xf4: case 0xf5: case 0xf6: case 0xf7: switch (ld) { case 0x00: + if (dev->id == 1) + break; + if (valxor & 0x18) fdc_update_drvrate(dev->fdc, dev->cur_reg & 0x03, (val & 0x18) >> 3); break; @@ -351,13 +379,18 @@ w83977f_reset(w83977f_t *dev) } dev->regs[0x22] = 0xff; dev->regs[0x24] = dev->type ? 0x84 : 0xa4; + dev->regs[0x26] = dev->hefras; /* WARNING: Array elements are register - 0x30. */ /* Logical Device 0 (FDC) */ dev->dev_regs[0][0x00] = 0x01; if (!dev->type) dev->dev_regs[0][0x01] = 0x02; - dev->dev_regs[0][0x30] = 0x03; dev->dev_regs[0][0x31] = 0xf0; + if (next_id == 1) { + dev->dev_regs[0][0x30] = 0x03; dev->dev_regs[0][0x31] = 0x70; + } else { + dev->dev_regs[0][0x30] = 0x03; dev->dev_regs[0][0x31] = 0xf0; + } dev->dev_regs[0][0x40] = 0x06; if (!dev->type) dev->dev_regs[0][0x41] = 0x02; /* Read-only */ @@ -368,8 +401,13 @@ w83977f_reset(w83977f_t *dev) dev->dev_regs[1][0x00] = 0x01; if (!dev->type) dev->dev_regs[1][0x01] = 0x02; - dev->dev_regs[1][0x30] = 0x03; dev->dev_regs[1][0x31] = 0x78; - dev->dev_regs[1][0x40] = 0x07; + if (next_id == 1) { + dev->dev_regs[1][0x30] = 0x02; dev->dev_regs[1][0x31] = 0x78; + dev->dev_regs[1][0x40] = 0x05; + } else { + dev->dev_regs[1][0x30] = 0x03; dev->dev_regs[1][0x31] = 0x78; + dev->dev_regs[1][0x40] = 0x07; + } if (!dev->type) dev->dev_regs[1][0x41] = 0x01 /*0x02*/; /* Read-only */ dev->dev_regs[1][0x44] = 0x04; @@ -379,7 +417,11 @@ w83977f_reset(w83977f_t *dev) dev->dev_regs[2][0x00] = 0x01; if (!dev->type) dev->dev_regs[2][0x01] = 0x02; - dev->dev_regs[2][0x30] = 0x03; dev->dev_regs[2][0x31] = 0xf8; + if (next_id == 1) { + dev->dev_regs[2][0x30] = 0x03; dev->dev_regs[2][0x31] = 0xe8; + } else { + dev->dev_regs[2][0x30] = 0x03; dev->dev_regs[2][0x31] = 0xf8; + } dev->dev_regs[2][0x40] = 0x04; if (!dev->type) dev->dev_regs[2][0x41] = 0x02; /* Read-only */ @@ -388,7 +430,11 @@ w83977f_reset(w83977f_t *dev) dev->dev_regs[3][0x00] = 0x01; if (!dev->type) dev->dev_regs[3][0x01] = 0x02; - dev->dev_regs[3][0x30] = 0x02; dev->dev_regs[3][0x31] = 0xf8; + if (next_id == 1) { + dev->dev_regs[3][0x30] = 0x02; dev->dev_regs[3][0x31] = 0xe8; + } else { + dev->dev_regs[3][0x30] = 0x02; dev->dev_regs[3][0x31] = 0xf8; + } dev->dev_regs[3][0x40] = 0x03; if (!dev->type) dev->dev_regs[3][0x41] = 0x02; /* Read-only */ @@ -460,12 +506,18 @@ w83977f_reset(w83977f_t *dev) dev->dev_regs[10][0xc0] = 0x8f; } - fdc_reset(dev->fdc); + if (next_id == 1) { + serial_setup(dev->uart[0], SERIAL3_ADDR, SERIAL3_IRQ); + serial_setup(dev->uart[1], SERIAL4_ADDR, SERIAL4_IRQ); + } else { + fdc_reset(dev->fdc); - serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ); - serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ); + serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ); + serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ); + + w83977f_fdc_handler(dev); + } - w83977f_fdc_handler(dev); w83977f_lpt_handler(dev); w83977f_serial_handler(dev, 0); w83977f_serial_handler(dev, 1); @@ -482,6 +534,8 @@ w83977f_close(void *priv) { w83977f_t *dev = (w83977f_t *) priv; + next_id = 0; + free(dev); } @@ -492,15 +546,23 @@ w83977f_init(const device_t *info) w83977f_t *dev = (w83977f_t *) malloc(sizeof(w83977f_t)); memset(dev, 0, sizeof(w83977f_t)); - dev->type = info->local; + dev->type = info->local & 0x0f; + dev->hefras = info->local & 0x40; - dev->fdc = device_add(&fdc_at_smc_device); + dev->id = next_id; - dev->uart[0] = device_add_inst(&ns16550_device, 1); - dev->uart[1] = device_add_inst(&ns16550_device, 2); + if (next_id == 1) + dev->hefras ^= 0x40; + else + dev->fdc = device_add(&fdc_at_smc_device); + + dev->uart[0] = device_add_inst(&ns16550_device, (next_id << 1) + 1); + dev->uart[1] = device_add_inst(&ns16550_device, (next_id << 1) + 2); w83977f_reset(dev); + next_id++; + return dev; } @@ -515,6 +577,16 @@ const device_t w83977f_device = { }; +const device_t w83977f_370_device = { + "Winbond W83977F Super I/O (Port 370h)", + 0, + 0x40, + w83977f_init, w83977f_close, NULL, + NULL, NULL, NULL, + NULL +}; + + const device_t w83977tf_device = { "Winbond W83977TF Super I/O", 0, @@ -533,3 +605,13 @@ const device_t w83977ef_device = { NULL, NULL, NULL, NULL }; + + +const device_t w83977ef_370_device = { + "Winbond W83977TF Super I/O (Port 370h)", + 0, + 0x42, + w83977f_init, w83977f_close, NULL, + NULL, NULL, NULL, + NULL +}; diff --git a/src/video/vid_paradise.c b/src/video/vid_paradise.c index 3b6f3acab..48e86544a 100644 --- a/src/video/vid_paradise.c +++ b/src/video/vid_paradise.c @@ -122,6 +122,7 @@ void paradise_out(uint16_t addr, uint8_t val, void *p) { svga->gdcreg[0xe] = val; paradise_remap(paradise); + svga_recalctimings(svga); return; } break; @@ -251,9 +252,11 @@ void paradise_recalctimings(svga_t *svga) if (paradise->type == WD90C30) svga->interlace = (svga->crtc[0x2d] & 0x20); - svga->lowres = !(svga->gdcreg[0xe] & 0x01); - if (svga->bpp == 8 && !svga->lowres) + if (svga->gdcreg[0xe] & 0x01) { + svga->bpp = 8; + svga->lowres = 0; svga->render = svga_render_8bpp_highres; + } } static void paradise_write(uint32_t addr, uint8_t val, void *p) @@ -299,7 +302,7 @@ void *paradise_init(const device_t *info, uint32_t memsize) switch(info->local) { case PVGA1A: svga_init(info, ¶dise->svga, paradise, memsize, /*256kb*/ - NULL, + paradise_recalctimings, paradise_in, paradise_out, NULL, NULL); diff --git a/src/win/86Box.rc b/src/win/86Box.rc index 1265799cf..9db8502f1 100644 --- a/src/win/86Box.rc +++ b/src/win/86Box.rc @@ -459,7 +459,7 @@ BEGIN PUSHBUTTON "Configure",IDC_CONFIGURE_NET,214,43,46,12 END -DLG_CFG_PORTS DIALOG DISCARDABLE 97, 0, 267, 117 +DLG_CFG_PORTS DIALOG DISCARDABLE 97, 0, 267, 135 STYLE DS_CONTROL | WS_CHILD FONT 9, "Segoe UI" BEGIN @@ -479,13 +479,17 @@ BEGIN BS_AUTOCHECKBOX | WS_TABSTOP,7,64,94,10 CONTROL "Serial port 2",IDC_CHECK_SERIAL2,"Button", BS_AUTOCHECKBOX | WS_TABSTOP,147,64,94,10 + CONTROL "Serial port 3",IDC_CHECK_SERIAL3,"Button", + BS_AUTOCHECKBOX | WS_TABSTOP,7,82,94,10 + CONTROL "Serial port 4",IDC_CHECK_SERIAL4,"Button", + BS_AUTOCHECKBOX | WS_TABSTOP,147,82,94,10 CONTROL "Parallel port 1",IDC_CHECK_PARALLEL1,"Button", - BS_AUTOCHECKBOX | WS_TABSTOP,7,82,94,10 - CONTROL "Parallel port 2",IDC_CHECK_PARALLEL2,"Button", - BS_AUTOCHECKBOX | WS_TABSTOP,147,82,94,10 - CONTROL "Parallel port 3",IDC_CHECK_PARALLEL3,"Button", BS_AUTOCHECKBOX | WS_TABSTOP,7,100,94,10 + CONTROL "Parallel port 2",IDC_CHECK_PARALLEL2,"Button", + BS_AUTOCHECKBOX | WS_TABSTOP,147,100,94,10 + CONTROL "Parallel port 3",IDC_CHECK_PARALLEL3,"Button", + BS_AUTOCHECKBOX | WS_TABSTOP,7,118,94,10 END DLG_CFG_PERIPHERALS DIALOG DISCARDABLE 97, 0, 267, 220 diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index 2743019eb..2776af130 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -42,6 +42,9 @@ ifeq ($(DEV_BUILD), y) ifndef CL5422 CL5422 := y endif + ifndef CYRIX_6X86 + CYRIX_6X86 := y + endif ifndef LASERXT LASERXT := y endif @@ -69,6 +72,9 @@ ifeq ($(DEV_BUILD), y) ifndef SIEMENS SIEMENS := y endif + ifndef STPC + STPC := y + endif ifndef VGAWONDER VGAWONDER := y endif @@ -106,6 +112,9 @@ else ifndef CL5422 CL5422 := n endif + ifndef CYRIX_6X86 + CYRIX_6X86 := n + endif ifndef LASERXT LASERXT := n endif @@ -133,6 +142,9 @@ else ifndef SIEMENS SIEMENS := n endif + ifndef STPC + STPC := y + endif ifndef VGAWONDER VGAWONDER := n endif @@ -473,6 +485,10 @@ ifeq ($(CL5422), y) OPTS += -DUSE_CL5422 endif +ifeq ($(CYRIX_6X86), y) +OPTS += -DUSE_CYRIX_6X86 +endif + ifeq ($(LASERXT), y) OPTS += -DUSE_LASERXT DEVBROBJ += m_xt_laserxt.o @@ -512,6 +528,11 @@ ifeq ($(SIEMENS), y) OPTS += -DUSE_SIEMENS endif +ifeq ($(STPC), y) +OPTS += -DUSE_STPC +STPCOBJ := stpc.o +endif + ifeq ($(596B), y) OPTS += -DUSE_596B endif @@ -572,7 +593,7 @@ CPUOBJ := cpu.o cpu_table.o \ CHIPSETOBJ := acc2168.o cs8230.o ali1429.o headland.o i82335.o \ intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \ neat.o opti495.o opti895.o opti5x7.o scamp.o scat.o \ - sis_85c310.o sis_85c471.o sis_85c496.o opti283.o opti291.o \ + sis_85c310.o sis_85c471.o sis_85c496.o opti283.o opti291.o $(STPCOBJ) \ via_apollo.o via_vpx.o via_vt82c586b.o via_vt82c596b.o wd76c10.o vl82c480.o \ amd640.o @@ -626,7 +647,8 @@ HDDOBJ := hdd.o \ hdc_xta.o \ hdc_esdi_at.o hdc_esdi_mca.o \ hdc_xtide.o hdc_ide.o \ - hdc_ide_sff8038i.o + hdc_ide_opti611.o \ + hdc_ide_cmd640.o hdc_ide_sff8038i.o CDROMOBJ := cdrom.o \ cdrom_image_backend.o cdrom_image.o diff --git a/src/win/win_settings.c b/src/win/win_settings.c index 8eb444253..0bbdf75a6 100644 --- a/src/win/win_settings.c +++ b/src/win/win_settings.c @@ -94,7 +94,7 @@ static char temp_pcap_dev[522]; /* Ports category */ static int temp_lpt_devices[3]; -static int temp_serial[2], temp_lpt[3]; +static int temp_serial[4], temp_lpt[3]; /* Other peripherals category */ static int temp_fdc_card, temp_hdc, temp_scsi_card, temp_ide_ter, temp_ide_qua; @@ -262,7 +262,7 @@ win_settings_init(void) temp_lpt_devices[i] = lpt_ports[i].device; temp_lpt[i] = lpt_ports[i].enabled; } - for (i = 0; i < 2; i++) + for (i = 0; i < 4; i++) temp_serial[i] = serial_enabled[i]; /* Other peripherals category */ @@ -372,7 +372,7 @@ win_settings_changed(void) i = i || (temp_lpt_devices[j] != lpt_ports[j].device); i = i || (temp_lpt[j] != lpt_ports[j].enabled); } - for (j = 0; j < 2; j++) + for (j = 0; j < 4; j++) i = i || (temp_serial[j] != serial_enabled[j]); /* Peripherals category */ @@ -484,7 +484,7 @@ win_settings_save(void) lpt_ports[i].device = temp_lpt_devices[i]; lpt_ports[i].enabled = temp_lpt[i]; } - for (i = 0; i < 2; i++) + for (i = 0; i < 4; i++) serial_enabled[i] = temp_serial[i]; /* Peripherals category */ @@ -627,7 +627,7 @@ win_settings_machine_recalc_cpu_m(HWND hdlg) SendMessage(h, CB_ADDSTRING, 0, (LPARAM)(LPCSTR)lptsTemp); c++; } - EnableWindow(h, TRUE); + EnableWindow(h, (c == 1) ? FALSE : TRUE); if (temp_cpu >= c) temp_cpu = (c - 1); SendMessage(h, CB_SETCURSEL, temp_cpu, 0); @@ -1563,7 +1563,7 @@ win_settings_ports_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam) EnableWindow(h, temp_lpt[i] ? TRUE : FALSE); } - for (i = 0; i < 2; i++) { + for (i = 0; i < 4; i++) { h=GetDlgItem(hdlg, IDC_CHECK_SERIAL1 + i); SendMessage(h, BM_SETCHECK, temp_serial[i], 0); } @@ -1602,7 +1602,7 @@ win_settings_ports_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam) temp_lpt[i] = SendMessage(h, BM_GETCHECK, 0, 0); } - for (i = 0; i < 2; i++) { + for (i = 0; i < 4; i++) { h = GetDlgItem(hdlg, IDC_CHECK_SERIAL1 + i); temp_serial[i] = SendMessage(h, BM_GETCHECK, 0, 0); }