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Fix TSS trap-bit handling

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Cacodemon345
2024-01-15 00:05:48 +06:00
parent c3fa0fc18b
commit 8c6fc11bb2
1 changed files with 2 additions and 1 deletions
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3
src/cpu/386_dynarec.c
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@@ -268,7 +268,7 @@ exec386_dynarec_int(void)
cpu_block_end = 0; cpu_block_end = 0;
x86_was_reset = 0; x86_was_reset = 0;
if (trap == 2) { if (trap & 2) {
/* Handle the T bit in the new TSS first. */ /* Handle the T bit in the new TSS first. */
CPU_BLOCK_END(); CPU_BLOCK_END();
goto block_ended; goto block_ended;
@@ -342,6 +342,7 @@ exec386_dynarec_int(void)
block_ended: block_ended:
if (!cpu_state.abrt && trap) { if (!cpu_state.abrt && trap) {
//pclog("Debug trap 0x%X\n", trap);
if (trap & 2) dr[6] |= 0x8000; if (trap & 2) dr[6] |= 0x8000;
if (trap & 1) dr[6] |= 0x4000; if (trap & 1) dr[6] |= 0x4000;