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Merge pull request #1571 from 86Box/master

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Bring the branch up to par with master.
This commit is contained in:
Miran Grča
2021-08-02 06:58:22 +02:00
committed by GitHub
parent 4a6c064d0f 07e7c1dd9e
commit 8ca1328c7e
83 changed files with 3364 additions and 788 deletions
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64
src/chipset/intel_piix.c
View File

@@ -589,18 +589,13 @@ piix_write(int func, int addr, uint8_t val, void *priv)
} else if (func == 1) switch(addr) { /* IDE */
case 0x04:
fregs[0x04] = (val & 5);
if (dev->type < 3)
if (dev->type <= 3)
fregs[0x04] |= 0x02;
piix_ide_handlers(dev, 0x03);
piix_ide_bm_handlers(dev);
break;
case 0x07:
if (val & 0x20)
fregs[0x07] &= 0xdf;
if (val & 0x10)
fregs[0x07] &= 0xef;
if (val & 0x08)
fregs[0x07] &= 0xf7;
fregs[0x07] &= ~(val & 0x38);
break;
case 0x09:
if (dev->type == 5) {
@@ -613,36 +608,52 @@ piix_write(int func, int addr, uint8_t val, void *priv)
fregs[0x0d] = val & 0xf0;
break;
case 0x10:
fregs[0x10] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x01);
if (dev->type == 5) {
fregs[0x10] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x11:
fregs[0x11] = val;
piix_ide_handlers(dev, 0x01);
if (dev->type == 5) {
fregs[0x11] = val;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x14:
fregs[0x14] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x01);
if (dev->type == 5) {
fregs[0x14] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x15:
fregs[0x15] = val;
piix_ide_handlers(dev, 0x01);
if (dev->type == 5) {
fregs[0x15] = val;
piix_ide_handlers(dev, 0x01);
}
break;
case 0x18:
fregs[0x18] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x02);
if (dev->type == 5) {
fregs[0x18] = (val & 0xf8) | 1;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x19:
fregs[0x19] = val;
piix_ide_handlers(dev, 0x02);
if (dev->type == 5) {
fregs[0x19] = val;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x1c:
fregs[0x1c] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x02);
if (dev->type == 5) {
fregs[0x1c] = (val & 0xfc) | 1;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x1d:
fregs[0x1d] = val;
piix_ide_handlers(dev, 0x02);
if (dev->type == 5) {
fregs[0x1d] = val;
piix_ide_handlers(dev, 0x02);
}
break;
case 0x20:
fregs[0x20] = (val & 0xf0) | 1;
@@ -653,7 +664,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
piix_ide_bm_handlers(dev);
break;
case 0x3c:
fregs[0x3c] = val;
if (dev->type == 5)
fregs[0x3c] = val;
break;
case 0x3d:
if (dev->type == 5)
@@ -690,6 +702,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
if (dev->type > 4)
fregs[addr] = val;
break;
default:
break;
} else if (func == 2) switch(addr) { /* USB */
case 0x04:
if (dev->type > 4) {
@@ -1035,6 +1049,8 @@ piix_reset_hard(piix_t *dev)
/* Function 1: IDE */
fregs = (uint8_t *) dev->regs[1];
piix_log("PIIX Function 1: %02X%02X:%02X%02X\n", fregs[0x01], fregs[0x00], fregs[0x03], fregs[0x02]);
if (dev->type < 4)
fregs[0x04] = 0x02;
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
if (dev->type == 4)
fregs[0x08] = dev->rev & 0x07;

21
src/chipset/sis_85c4xx.c
View File

@@ -37,7 +37,7 @@ typedef struct
{
uint8_t cur_reg, tries,
reg_base, reg_last,
is_471,
reg_00, is_471,
regs[39], scratch[2];
smram_t *smram;
port_92_t *port_92;
@@ -78,7 +78,7 @@ sis_85c4xx_recalcmapping(sis_85c4xx_t *dev)
mem_set_mem_state(base, 0x8000, readext | writeext);
}
flushmmucache();
flushmmucache_nopc();
}
@@ -195,7 +195,8 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
}
break;
}
}
} else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00))
dev->reg_00 = val;
dev->cur_reg = 0x00;
break;
@@ -217,9 +218,15 @@ sis_85c4xx_in(uint16_t port, void *priv)
case 0x23:
if (dev->is_471 && (dev->cur_reg == 0x1c))
ret = inb(0x70);
if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last))
/* On the SiS 40x, the shadow RAM read and write enable bits are write-only! */
if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x62))
ret = dev->regs[rel_reg] & 0x3f;
else if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last))
ret = dev->regs[rel_reg];
dev->cur_reg = 0x00;
else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00))
ret = dev->reg_00;
if (dev->reg_base != 0x60)
dev->cur_reg = 0x00;
break;
case 0xe1: case 0xe2:
@@ -341,6 +348,10 @@ sis_85c4xx_init(const device_t *info)
} else {
dev->reg_last = dev->reg_base + 0x11;
/* Bits 6 and 7 must be clear on the SiS 40x. */
if (dev->reg_base == 0x60)
dev->reg_00 = 0x24;
switch (mem_size_mb) {
case 1:
default:

48
src/chipset/via_apollo.c
View File

@@ -340,37 +340,36 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x61: /* Shadow RAM Control 1 */
if ((dev->pci_conf[0x61] ^ val) & 0x03)
apollo_map(0xc0000, 0x04000, val & 0x03);
if ((dev->pci_conf[0x61] ^ val) & 0x0c)
apollo_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
if ((dev->pci_conf[0x61] ^ val) & 0x30)
apollo_map(0xc8000, 0x04000, (val & 0x30) >> 4);
if ((dev->pci_conf[0x61] ^ val) & 0xc0)
apollo_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
apollo_map(0xc0000, 0x04000, val & 0x03);
apollo_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
apollo_map(0xc8000, 0x04000, (val & 0x30) >> 4);
apollo_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
dev->pci_conf[0x61] = val;
break;
case 0x62: /* Shadow RAM Control 2 */
if ((dev->pci_conf[0x62] ^ val) & 0x03)
apollo_map(0xd0000, 0x04000, val & 0x03);
if ((dev->pci_conf[0x62] ^ val) & 0x0c)
apollo_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
if ((dev->pci_conf[0x62] ^ val) & 0x30)
apollo_map(0xd8000, 0x04000, (val & 0x30) >> 4);
if ((dev->pci_conf[0x62] ^ val) & 0xc0)
apollo_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
apollo_map(0xd0000, 0x04000, val & 0x03);
apollo_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
apollo_map(0xd8000, 0x04000, (val & 0x30) >> 4);
apollo_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
dev->pci_conf[0x62] = val;
break;
case 0x63: /* Shadow RAM Control 3 */
if ((dev->pci_conf[0x63] ^ val) & 0x30) {
apollo_map(0xf0000, 0x10000, (val & 0x30) >> 4);
shadowbios = (((val & 0x30) >> 4) & 0x02);
}
if ((dev->pci_conf[0x63] ^ val) & 0xc0)
apollo_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
shadowbios = 0;
shadowbios_write = 0;
apollo_map(0xf0000, 0x10000, (val & 0x30) >> 4);
shadowbios = (((val & 0x30) >> 4) & 0x02);
shadowbios_write = (((val & 0x30) >> 4) & 0x01);
apollo_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
shadowbios |= (((val & 0xc0) >> 6) & 0x02);
shadowbios_write |= (((val & 0xc0) >> 6) & 0x01);
dev->pci_conf[0x63] = val;
smram_disable_all();
if (dev->id >= VIA_691) switch (val & 0x03) {
if (dev->id >= VIA_691) switch (val & 0x03) {
case 0x00:
default:
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
@@ -679,7 +678,8 @@ via_apollo_init(const device_t *info)
memset(dev, 0, sizeof(via_apollo_t));
dev->smram = smram_add();
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
if (dev->id != VIA_8601)
apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
pci_add_card(PCI_ADD_NORTHBRIDGE, via_apollo_read, via_apollo_write, dev);

15
src/chipset/via_pipc.c
View File

@@ -285,7 +285,7 @@ pipc_reset_hard(void *priv)
dev->power_regs[0x34] = 0x68;
dev->power_regs[0x40] = 0x20;
dev->power_regs[0x42] = 0xd0;
dev->power_regs[0x42] = 0x50;
dev->power_regs[0x48] = 0x01;
if (dev->local == VIA_PIPC_686B) {
@@ -359,6 +359,9 @@ pipc_reset_hard(void *priv)
ide_pri_disable();
ide_sec_disable();
nvr_via_wp_set(0x00, 0x32, dev->nvr);
nvr_via_wp_set(0x00, 0x0d, dev->nvr);
}
@@ -502,7 +505,7 @@ nvr_update_io_mapping(pipc_t *dev)
if (dev->nvr_enabled)
nvr_at_handler(0, 0x0074, dev->nvr);
if ((dev->pci_isa_regs[0x5b] & 0x02) && (dev->pci_isa_regs[0x48] & 0x08))
if ((dev->pci_isa_regs[0x5b] & 0x02) || (dev->pci_isa_regs[0x48] & 0x08))
nvr_at_handler(1, 0x0074, dev->nvr);
}
@@ -682,6 +685,8 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
case 0x77:
if (val & 0x10)
pclog("PIPC: Warning: Internal I/O APIC enabled.\n");
nvr_via_wp_set(!!(val & 0x04), 0x32, dev->nvr);
nvr_via_wp_set(!!(val & 0x02), 0x0d, dev->nvr);
break;
case 0x80: case 0x86: case 0x87:
@@ -922,8 +927,8 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x42:
dev->power_regs[addr] &= ~0x0f;
dev->power_regs[addr] |= val & 0x0f;
dev->power_regs[addr] &= ~0x2f;
dev->power_regs[addr] |= val & 0x2f;
acpi_set_irq_line(dev->acpi, dev->power_regs[addr]);
break;
@@ -1013,6 +1018,8 @@ pipc_reset(void *p)
pipc_write(1, 0x40, 0x04, p);
else
pipc_write(1, 0x40, 0x00, p);
pipc_write(0, 0x77, 0x00, p);
}