From 8dc0beaeec0224ecb780e5e7ba7c35ed6b4bcab2 Mon Sep 17 00:00:00 2001
From: Dmitry Borisov <di.sean@protonmail.com>
Date: Sun, 5 Jan 2025 12:15:01 +0600
Subject: [PATCH] pc87307: Fix GPIO base address configuration

Don't clobber the GPIO I/O Base value.

According to the PC87307 datasheet, port 0x60 bits [2:7] are read-only
for the Parallel Port (4) device and cannot be altered by software.
For others devices, the 0x60 port may be written with any value.

The SGI firmware emits the following PC87307 initialization sequence
after each reset:

/* Select the GPIO device (7) */
SIO IDX: 2E <-- 07
SIO DAT: 2F <-- 07

/* I/O Base MSB = 0x0F */
SIO IDX: 2E <-- 60
SIO DAT: 2F <-- 0F

/* I/O Base LSB = 0xC0 */
SIO IDX: 2E <-- 61
SIO DAT: 2F <-- C0

/* Enable address decoding (I/O Base = 0xFC0) */
SIO IDX: 2E <-- 30
SIO DAT: 2F <-- 01

The GPIO I/O Base is erroneously assigned to 0x7C0. Fix by removing the 0x07 mask.
---
 src/sio/sio_pc87307.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/sio/sio_pc87307.c b/src/sio/sio_pc87307.c
index 63e19c03d..cb772aa5b 100644
--- a/src/sio/sio_pc87307.c
+++ b/src/sio/sio_pc87307.c
@@ -34,6 +34,7 @@
 #include <86box/fdd.h>
 #include <86box/fdc.h>
 #include <86box/sio.h>
+#include <86box/plat_fallthrough.h>
 
 typedef struct pc87307_t {
     uint8_t   id;
@@ -323,8 +324,12 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
             }
             break;
         case 0x60:
+            if (dev->regs[0x07] == 0x04) {
+                val &= 0x03;
+            }
+            fallthrough;
         case 0x62:
-            dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x07;
+            dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val;
             if ((dev->cur_reg == 0x62) && (dev->regs[0x07] != 0x07))
                 break;
             switch (dev->regs[0x07]) {