Universalize the keyboard and mouse latches again, fixes #3280.

src/chipset/ali1489.c

@@ -180,9 +180,6 @@ ali1489_defaults(ali1489_t *dev)
     dev->regs[0x3d] = 0x01;
     dev->regs[0x40] = 0x03;
 
-    pic_kbd_latch(0x01);
-    pic_mouse_latch(0x00);
-
     ali1489_shadow_recalc(dev);
     cpu_cache_int_enabled = 0;
     cpu_cache_ext_enabled = 0;
@@ -298,7 +295,6 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
 
                     case 0x2a: /* I/O Recovery Register */
                         dev->regs[dev->index] = val;
-                        pic_mouse_latch(val & 0x80);
                         break;
 
                     case 0x2b: /* Turbo Function Register */

src/chipset/ali1543.c

@@ -151,12 +151,6 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
             break;
 
         case 0x41:
-            pic_kbd_latch(1);
-            // pic_kbd_latch(!!(val & 0x80));
-            if (dev->type == 1)
-                pic_mouse_latch(!!(val & 0x40) || !(dev->pci_conf[0x78] & 0x02));
-            else
-                pic_mouse_latch(!!(val & 0x40));
             dev->pci_conf[addr] = val;
             break;
 
@@ -433,7 +427,6 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
             if (dev->type == 1) {
                 ali1543_log("PCI78 = %02X\n", val);
                 dev->pci_conf[addr] = val & 0x33;
-                pic_mouse_latch(!!(dev->pci_conf[0x41] & 0x40) || !(val & 0x02));
             }
             break;
 

src/chipset/ali6117.c

@@ -302,7 +302,6 @@ ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
                 case 0x36:
                     val &= 0xf0;
                     val |= dev->regs[dev->reg_offset];
-                    pic_mouse_latch(val & 0x40);
                     break;
 
                 case 0x37:
@@ -427,8 +426,6 @@ ali6117_reset(void *priv)
         /* On-board memory 15-16M is enabled by default. */
         mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
         ali6117_bank_recalc(dev);
-
-        pic_mouse_latch(0x00);
     }
 }
 
@@ -478,9 +475,6 @@ ali6117_init(const device_t *info)
         }
     }
 
-    if (!(dev->local & 0x08))
-        pic_kbd_latch(0x01);
-
     ali6117_reset(dev);
 
     if (!(dev->local & 0x08))

src/chipset/ims8848.c

@@ -389,9 +389,6 @@ ims8848_init(const device_t *info)
 
     ims8848_reset(dev);
 
-    pic_kbd_latch(0x01);
-    pic_mouse_latch(0x01);
-
     return dev;
 }
 

src/chipset/intel_420ex.c

@@ -218,7 +218,6 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
             break;
         case 0x4e:
             dev->regs[addr] = (val & 0xf7);
-            pic_mouse_latch(!!(val & 0x10));
             break;
         case 0x50:
             dev->regs[addr] = (val & 0x0f);
@@ -389,7 +388,6 @@ i420ex_reset_hard(void *priv)
 
     dev->regs[0x4c] = 0x4d;
     dev->regs[0x4e] = 0x03;
-    pic_mouse_latch(0x00);
    /* Bits 2:1 of register 50h are 00 is 25 MHz, and 01 if 33 MHz, 10 and 11 are reserved. */
     if (cpu_busspeed >= 33333333)
         dev->regs[0x50] |= 0x02;
@@ -526,8 +524,6 @@ i420ex_init(const device_t *info)
 
     i420ex_reset_hard(dev);
 
-    pic_kbd_latch(0x01);
-
     return dev;
 }
 

src/chipset/intel_piix.c

@@ -512,7 +512,6 @@ piix_write(int func, int addr, uint8_t val, void *priv)
                 break;
             case 0x4e:
                 fregs[0x4e] = val;
-                pic_mouse_latch(!!(val & 0x10));
                 if (dev->type >= 4)
                     kbc_alias_update_io_mapping(dev);
                 break;
@@ -1275,7 +1274,6 @@ piix_reset_hard(piix_t *dev)
     fregs[0x0e] = ((dev->type > 1) || (dev->rev != 2)) ? 0x80 : 0x00;
     fregs[0x4c] = 0x4d;
     fregs[0x4e] = 0x03;
-    pic_mouse_latch(0x00);
     fregs[0x60] = fregs[0x61] = fregs[0x62] = fregs[0x63] = 0x80;
     fregs[0x64]                                           = (dev->type > 3) ? 0x10 : 0x00;
     fregs[0x69]                                           = 0x02;
@@ -1681,8 +1679,6 @@ piix_init(const device_t *info)
 
     // device_add(&i8254_sec_device);
 
-    pic_kbd_latch(0x01);
-
     return dev;
 }
 

src/chipset/intel_sio.c

@@ -204,7 +204,6 @@ sio_write(int func, int addr, uint8_t val, void *priv)
             break;
         case 0x4d:
             dev->regs[addr] = (val & 0x7f);
-            // pic_mouse_latch(!!(val & 0x10));
             break;
         case 0x4f:
             dev->regs[addr] = val;
@@ -396,7 +395,6 @@ sio_reset_hard(void *priv)
     dev->regs[0x4b] = 0x0f;
     dev->regs[0x4c] = 0x56;
     dev->regs[0x4d] = 0x40;
-    // pic_mouse_latch(0x00);
     dev->regs[0x4e] = 0x07;
     dev->regs[0x4f] = 0x4f;
     dev->regs[0x57] = 0x04;
@@ -546,20 +544,6 @@ sio_init(const device_t *info)
 
     // device_add(&i8254_sec_device);
 
-    // pic_kbd_latch(0x01);
-
-    /* The situation is as follow: SIO.AB has the IRQ 1 latch but SIO.IB and SIO.ZB do not,
-       and I suspect that because of that, the IRQ 12 latch on SIO.IB and SIO.ZB, while
-       evidently planned and documented in the datashet, was basically non-functional, and
-       motherboard manufacturers had to install their own latches to use PS/2 keyboards
-       and/or mice. One such example is the AMI Excalibur PCI Pentium, which never enables
-       the SIO.ZB's IRQ 12 latch but clearly expects one since otherwise, the PS/2 mouse
-       behaves erractically in the WinBIOS CMOS Setup. */
-    if (machine_has_bus(machine, MACHINE_BUS_PS2)) {
-        pic_kbd_latch(0x01);
-        pic_mouse_latch(0x01);
-    }
-
     return dev;
 }
 

src/chipset/sis_5571.c

@@ -726,9 +726,6 @@ sis_5571_init(const device_t *info)
 
     sis_5571_reset(dev);
 
-    pic_kbd_latch(0x01);
-    pic_mouse_latch(0x01);
-
     return dev;
 }
 

src/chipset/sis_85c50x.c

@@ -418,11 +418,6 @@ sis_85c50x_init(const device_t *info)
 
     sis_85c50x_reset(dev);
 
-    if (machine_has_bus(machine, MACHINE_BUS_PS2)) {
-        pic_kbd_latch(0x01);
-        pic_mouse_latch(0x01);
-    }
-
     return dev;
 }
 

src/chipset/umc_8886.c

@@ -374,9 +374,6 @@ umc_8886_init(const device_t *info)
 
     umc_8886_reset(dev);
 
-    pic_kbd_latch(0x01);
-    pic_mouse_latch(0x01);
-
     return dev;
 }
 

src/chipset/via_pipc.c

@@ -222,9 +222,6 @@ pipc_reset_hard(void *priv)
     dev->pci_isa_regs[0x0b] = 0x06;
     dev->pci_isa_regs[0x0e] = 0x80;
 
-    pic_kbd_latch(0x01);
-    pic_mouse_latch(dev->local >= VIA_PIPC_586B);
-
     dev->pci_isa_regs[0x48] = 0x01;
     dev->pci_isa_regs[0x4a] = 0x04;
     dev->pci_isa_regs[0x4f] = 0x03;
@@ -1067,8 +1064,7 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
                 break;
 
             case 0x44:
-                if (dev->local < VIA_PIPC_586B)
+                dev->pci_isa_regs[0x44] = val;
-                    pic_mouse_latch(val & 0x01);
                 break;
 
             case 0x47:

src/machine/m_ps2_mca.c

@@ -1343,9 +1343,6 @@ machine_ps2_common_init(const machine_t *model)
     nmi_mask = 0x80;
 
     ps2.uart = device_add_inst(&ns16550_device, 1);
-
-    pic_kbd_latch(0x01);
-    pic_mouse_latch(0x01);
 }
 
 int

src/pic.c

@@ -570,9 +570,17 @@ pic_reset_hard(void)
 {
     pic_reset();
 
+    /* The situation is as follows: There is a giant mess when it comes to these latches on real hardware,
+       to the point that there's even boards with board-level latched that get used in place of the latches
+       on the chipset, therefore, I'm just doing this here for the sake of simplicity. */
+    if (machine_has_bus(machine, MACHINE_BUS_PS2)) {
+        pic_kbd_latch(0x01);
+        pic_mouse_latch(0x01);
+    } else {
         pic_kbd_latch(0x00);
         pic_mouse_latch(0x00);
     }
+}
 
 void
 pic_init(void)