Next round of sonarlint cleanups
This commit is contained in:
Jasmine Iwanek
232
src/cpu/cpu.h
232
src/cpu/cpu.h
@@ -150,8 +150,10 @@ typedef struct {
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uint32_t cpuid_model;
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uint16_t cyrix_id;
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uint8_t cpu_flags;
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int8_t mem_read_cycles, mem_write_cycles;
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int8_t cache_read_cycles, cache_write_cycles;
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int8_t mem_read_cycles;
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int8_t mem_write_cycles;
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int8_t cache_read_cycles;
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int8_t cache_write_cycles;
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int8_t atclk_div;
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} CPU;
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@@ -215,17 +217,19 @@ typedef union {
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uint32_t l;
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uint16_t w;
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struct {
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uint8_t l,
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h;
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uint8_t l;
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uint8_t h;
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} b;
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} x86reg;
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typedef struct {
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uint32_t base;
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uint32_t limit;
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uint8_t access, ar_high;
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uint8_t access;
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uint8_t ar_high;
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uint16_t seg;
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uint32_t limit_low, limit_high;
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uint32_t limit_low;
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uint32_t limit_high;
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int checked; /*Non-zero if selector is known to be valid*/
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} x86seg;
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@@ -243,8 +247,9 @@ typedef union {
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typedef struct {
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/* IDT WinChip and WinChip 2 MSR's */
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uint32_t tr1, tr12; /* 0x00000002, 0x0000000e */
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uint32_t cesr; /* 0x00000011 */
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uint32_t tr1; /* 0x00000002, 0x0000000e */
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uint32_t tr12; /* 0x00000002, 0x0000000e */
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uint32_t cesr; /* 0x00000011 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */
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@@ -259,8 +264,9 @@ typedef struct {
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uint64_t mtrr_cap; /* 0x000000fe */
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/* IDT WinChip and WinChip 2 MSR's that are also on the VIA Cyrix III */
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uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
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uint64_t fcr2, fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
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uint64_t fcr2; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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uint64_t fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx116; /* 0x00000116 */
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@@ -276,8 +282,9 @@ typedef struct {
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uint64_t mcg_ctl; /* 0x0000017b - Machine Check Architecture */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx186, ecx187; /* 0x00000186, 0x00000187 */
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uint64_t ecx1e0; /* 0x000001e0 */
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uint64_t ecx186; /* 0x00000186, 0x00000187 */
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uint64_t ecx187; /* 0x00000186, 0x00000187 */
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uint64_t ecx1e0; /* 0x000001e0 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
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on the VIA Cyrix III */
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@@ -325,7 +332,8 @@ typedef struct {
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uint64_t amd_epmr; /* 0xc0000086 */
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/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_psor, amd_pfir; /* 0xc0000087, 0xc0000088 */
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uint64_t amd_psor; /* 0xc0000087, 0xc0000088 */
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uint64_t amd_pfir; /* 0xc0000087, 0xc0000088 */
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/* K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_l2aar; /* 0xc0000089 */
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@@ -345,33 +353,38 @@ typedef struct {
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uint32_t eaaddr;
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int flags_op;
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uint32_t flags_res,
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flags_op1, flags_op2;
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uint32_t flags_res;
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uint32_t flags_op1;
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uint32_t flags_op2;
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uint32_t pc,
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oldpc, op32;
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uint32_t pc;
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uint32_t oldpc;
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uint32_t op32;
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int TOP;
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union {
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struct {
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int8_t rm,
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mod,
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reg;
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int8_t rm;
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int8_t mod;
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int8_t reg;
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} rm_mod_reg;
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int32_t rm_mod_reg_data;
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} rm_data;
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uint8_t ssegs, ismmx,
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abrt, _smi_line;
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uint8_t ssegs;
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uint8_t ismmx;
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uint8_t abrt;
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uint8_t _smi_line;
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int _cycles;
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#ifdef FPU_CYCLES
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int _cycles, _fpu_cycles, _in_smm;
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#else
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int _cycles, _in_smm;
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int _fpu_cycles;
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#endif
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int _in_smm;
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uint16_t npxs, npxc;
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uint16_t npxs;
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uint16_t npxc;
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double ST[8];
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@@ -380,26 +393,34 @@ typedef struct {
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MMX_REG MM[8];
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#ifdef USE_NEW_DYNAREC
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uint32_t old_fp_control, new_fp_control;
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uint32_t old_fp_control;
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uint32_t new_fp_control;
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# if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
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uint16_t old_fp_control2, new_fp_control2;
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uint16_t old_fp_control2;
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uint16_t new_fp_control2;
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# endif
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# if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64
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uint32_t trunc_fp_control;
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uint32_t trunc_fp_control;
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# endif
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#else
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uint16_t old_npxc, new_npxc;
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uint16_t old_npxc;
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uint16_t new_npxc;
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#endif
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x86seg seg_cs, seg_ds, seg_es, seg_ss,
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seg_fs, seg_gs;
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x86seg seg_cs;
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x86seg seg_ds;
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x86seg seg_es;
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x86seg seg_ss;
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x86seg seg_fs;
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x86seg seg_gs;
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union {
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uint32_t l;
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uint16_t w;
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} CR0;
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uint16_t flags, eflags;
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uint16_t flags;
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uint16_t eflags;
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uint32_t _smbase;
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} cpu_state_t;
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@@ -415,13 +436,15 @@ typedef struct {
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uint16_t fds;
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floatx80 st_space[8];
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unsigned char tos;
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unsigned char align1, align2, align3;
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unsigned char align1;
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unsigned char align2;
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unsigned char align3;
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} fpu_state_t;
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#define in_smm cpu_state._in_smm
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#define smi_line cpu_state._smi_line
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#define smbase cpu_state._smbase
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#define smbase cpu_state._smbase
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/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block
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to be valid*/
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@@ -508,7 +531,8 @@ extern int cpu_override;
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extern int cpu_isintel;
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extern int cpu_iscyrix;
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extern int cpu_16bitbus, cpu_64bitbus;
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extern int cpu_16bitbus;
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extern int cpu_64bitbus;
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extern int cpu_pci_speed;
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extern int cpu_multi;
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extern double cpu_dmulti;
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@@ -517,8 +541,19 @@ extern double cpu_busspeed;
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extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
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penalties when crossing 8-byte boundaries*/
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extern int is8086, is186, is286, is386, is6117, is486;
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extern int is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
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extern int is8086;
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extern int is186;
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extern int is286;
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extern int is386;
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extern int is6117;
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extern int is486;
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extern int is_am486;
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extern int is_am486dxl;
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extern int is_pentium;
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extern int is_k5;
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extern int is_k6;
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extern int is_p6;
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extern int is_cxsmm;
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extern int hascache;
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extern int isibm486;
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extern int is_nec;
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@@ -536,7 +571,8 @@ extern int hasfpu;
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extern uint32_t cpu_features;
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extern int smi_latched, smm_in_hlt;
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extern int smi_latched;
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extern int smm_in_hlt;
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extern int smi_block;
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#ifdef USE_NEW_DYNAREC
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@@ -552,12 +588,21 @@ extern int cgate16;
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extern int cpl_override;
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extern int CPUID;
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extern uint64_t xt_cpu_multi;
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extern int isa_cycles, cpu_inited;
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extern uint32_t oldds, oldss, olddslimit, oldsslimit, olddslimitw, oldsslimitw;
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extern int isa_cycles;
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extern int cpu_inited;
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extern uint32_t oldds;
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extern uint32_t oldss;
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extern uint32_t olddslimit;
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extern uint32_t oldsslimit;
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extern uint32_t olddslimitw;
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extern uint32_t oldsslimitw;
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extern uint32_t pccache;
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extern uint8_t *pccache2;
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extern double bus_timing, isa_timing, pci_timing, agp_timing;
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extern double bus_timing;
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extern double isa_timing;
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extern double pci_timing;
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extern double agp_timing;
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extern uint64_t pmc[2];
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extern uint16_t temp_seg_data[4];
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extern uint16_t cs_msr;
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@@ -565,13 +610,16 @@ extern uint32_t esp_msr;
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extern uint32_t eip_msr;
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/* For the AMD K6. */
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extern uint64_t amd_efer, star;
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extern uint64_t amd_efer;
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extern uint64_t star;
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#define FPU_CW_Reserved_Bits (0xe0c0)
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#define cr0 cpu_state.CR0.l
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#define msw cpu_state.CR0.w
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extern uint32_t cr2, cr3, cr4;
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#define cr0 cpu_state.CR0.l
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#define msw cpu_state.CR0.w
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extern uint32_t cr2;
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extern uint32_t cr3;
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extern uint32_t cr4;
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extern uint32_t dr[8];
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extern uint32_t _tr[8];
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extern uint32_t cache_index;
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@@ -581,7 +629,10 @@ extern uint8_t _cache[2048];
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_cs,_ds,_es,_ss are the segment structures
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CS,DS,ES,SS is the 16-bit data
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cs,ds,es,ss are defines to the bases*/
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extern x86seg gdt, ldt, idt, tr;
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extern x86seg gdt;
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extern x86seg ldt;
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extern x86seg idt;
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extern x86seg tr;
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extern x86seg _oldds;
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#define CS cpu_state.seg_cs.seg
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#define DS cpu_state.seg_ds.seg
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@@ -598,37 +649,67 @@ extern x86seg _oldds;
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#define ISA_CYCLES(x) (x * isa_cycles)
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extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
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extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
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extern int cpu_cycles_read;
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extern int cpu_cycles_read_l;
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extern int cpu_cycles_write;
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extern int cpu_cycles_write_l;
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extern int cpu_prefetch_cycles;
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extern int cpu_prefetch_width;
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extern int cpu_mem_prefetch_cycles;
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extern int cpu_rom_prefetch_cycles;
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extern int cpu_waitstates;
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extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
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extern int cpu_isa_speed, cpu_pci_speed, cpu_agp_speed;
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extern int cpu_cache_int_enabled;
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extern int cpu_cache_ext_enabled;
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extern int cpu_isa_speed;
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extern int cpu_pci_speed;
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extern int cpu_agp_speed;
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extern int timing_rr;
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extern int timing_mr, timing_mrl;
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extern int timing_rm, timing_rml;
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extern int timing_mm, timing_mml;
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extern int timing_bt, timing_bnt;
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extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm;
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extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm;
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extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm;
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extern int timing_call_pm_gate, timing_call_pm_gate_inner;
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extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
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extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
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extern int timing_mr;
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extern int timing_mrl;
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extern int timing_rm;
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extern int timing_rml;
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extern int timing_mm;
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extern int timing_mml;
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extern int timing_bt;
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extern int timing_bnt;
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extern int timing_int;
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extern int timing_int_rm;
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extern int timing_int_v86;
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extern int timing_int_pm;
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extern int timing_int_pm_outer;
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extern int timing_iret_rm;
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extern int timing_iret_v86;
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extern int timing_iret_pm;
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extern int timing_iret_pm_outer;
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extern int timing_call_rm;
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extern int timing_call_pm;
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extern int timing_call_pm_gate;
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extern int timing_call_pm_gate_inner;
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extern int timing_retf_rm;
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extern int timing_retf_pm;
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extern int timing_retf_pm_outer;
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extern int timing_jmp_rm;
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extern int timing_jmp_pm;
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extern int timing_jmp_pm_gate;
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extern int timing_misaligned;
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extern int in_sys, unmask_a20_in_smm;
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extern int in_sys;
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extern int unmask_a20_in_smm;
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extern int cycles_main;
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extern uint32_t old_rammask;
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#ifdef USE_ACYCS
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extern int acycs;
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#endif
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extern int pic_pending, is_vpc;
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extern int soft_reset_mask, alt_access;
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extern int pic_pending;
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extern int is_vpc;
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extern int soft_reset_mask;
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extern int alt_access;
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extern int cpu_end_block_after_ins;
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extern uint16_t cpu_fast_off_count, cpu_fast_off_val;
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extern uint16_t cpu_fast_off_count;
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extern uint16_t cpu_fast_off_val;
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extern uint32_t cpu_fast_off_flags;
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/* Functions. */
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@@ -703,7 +784,8 @@ extern void x87_dumpregs(void);
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extern void x87_reset(void);
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#endif
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extern int cpu_effective, cpu_alt_reset;
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extern int cpu_effective;
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extern int cpu_alt_reset;
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extern void cpu_dynamic_switch(int new_cpu);
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extern void cpu_ven_reset(void);
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@@ -728,22 +810,23 @@ void cyrix_write_seg_descriptor(uint32_t addr, x86seg *seg);
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#define SMHR_VALID (1 << 0)
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#define SMHR_ADDR_MASK (0xfffffffc)
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typedef struct
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{
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struct
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{
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typedef struct {
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struct {
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uint32_t base;
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uint64_t size;
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} arr[8];
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uint32_t smhr;
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} cyrix_t;
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extern uint32_t addr64, addr64_2;
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extern uint32_t addr64a[8], addr64a_2[8];
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extern uint32_t addr64;
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extern uint32_t addr64_2;
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extern uint32_t addr64a[8];
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extern uint32_t addr64a_2[8];
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extern int soft_reset_pci;
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extern int reset_on_hlt, hlt_reset_pending;
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extern int reset_on_hlt;
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extern int hlt_reset_pending;
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extern cyrix_t cyrix;
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@@ -751,7 +834,8 @@ extern uint8_t use_custom_nmi_vector;
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extern uint32_t custom_nmi_vector;
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extern void (*cpu_exec)(int cycs);
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extern uint8_t do_translate, do_translate2;
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extern uint8_t do_translate;
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extern uint8_t do_translate2;
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extern void SF_FPU_reset(void);
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