Implemented the Intel 420EX combined northbridge and southbridge, added the ASUS PVI-486AP4, and overhauled SMRAM handling (which also implements some previously missing extended SMRAM features of the 440BX+ and VIA Apollo series of chipsets).

2020-06-12 23:29:12 +02:00
parent 2920ad25f3
commit 92a1425896
14 changed files with 1109 additions and 169 deletions
--- a/src/intel_sio.c
+++ b/src/intel_sio.c
@@ -173,7 +173,7 @@ sio_write(int func, int addr, uint8_t val, void *priv)
 				return;

 			dma_alias_remove();
-			if (val & 0x40)
+			if (!(val & 0x40))
 				dma_alias_set();
 		} else
 			dev->regs[addr] = (val & 0x3f);