Merge pull request #996 from richardg867/master
ALi M6117 SoC implementation
This commit is contained in:
Miran Grča
GitHub
343
src/chipset/ali6117.c
Normal file
343
src/chipset/ali6117.c
Normal file
@@ -0,0 +1,343 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the ALi M6117D SoC.
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*
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*
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*
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* Authors: RichardG, <richardg867@gmail.com>
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*
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* Copyright 2020 RichardG.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdarg.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/rom.h>
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#include <86box/pci.h>
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#include <86box/pic.h>
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#include <86box/timer.h>
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#include <86box/pit.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/port_92.h>
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#include <86box/usb.h>
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#include <86box/hdc.h>
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#include <86box/chipset.h>
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typedef struct ali6117_t
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{
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uint32_t local;
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/* Main registers (port 22h/23h) */
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uint8_t unlocked;
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uint8_t reg_offset;
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uint8_t regs[256];
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} ali6117_t;
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#ifdef ENABLE_ALI6117_LOG
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int ali6117_do_log = ENABLE_ALI6117_LOG;
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static void
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ali6117_log(const char *fmt, ...)
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{
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va_list ap;
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if (ali6117_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define ali6117_log(fmt, ...)
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#endif
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static void
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ali6117_recalcmapping(ali6117_t *dev)
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{
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uint8_t reg, bitpair;
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uint32_t base, size;
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int state;
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shadowbios = 0;
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shadowbios_write = 0;
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ali6117_log("M6117: Shadowing for a0000-bffff (reg 12) = %s\n", (dev->regs[0x12] & 0x02) ? "on" : "off");
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mem_set_mem_state(0xa0000, 0x20000, (dev->regs[0x12] & 0x02) ? (MEM_WRITE_INTERNAL | MEM_READ_INTERNAL) : (MEM_WRITE_EXTANY | MEM_READ_EXTANY));
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for (reg = 0; reg <= 1; reg++) {
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for (bitpair = 0; bitpair <= 3; bitpair++) {
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size = 0x8000;
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base = 0xc0000 + (size * ((reg * 4) + bitpair));
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ali6117_log("M6117: Shadowing for %05x-%05x (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x14 + reg, bitpair, 1 << ((bitpair * 2) + 1), 1 << (bitpair * 2));
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state = 0;
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if (dev->regs[0x14 + reg] & (1 << ((bitpair * 2) + 1))) {
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ali6117_log(" w on");
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state |= MEM_WRITE_INTERNAL;
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if (base >= 0xe0000)
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shadowbios_write |= 1;
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} else {
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ali6117_log(" w off");
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state |= MEM_WRITE_EXTANY;
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}
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if (dev->regs[0x14 + reg] & (1 << (bitpair * 2))) {
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ali6117_log("; r on\n");
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state |= MEM_READ_INTERNAL;
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if (base >= 0xe0000)
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shadowbios |= 1;
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} else {
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ali6117_log("; r off\n");
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state |= MEM_READ_EXTANY;
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}
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mem_set_mem_state(base, size, state);
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}
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}
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flushmmucache();
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}
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static void
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ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
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{
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ali6117_t *dev = (ali6117_t *) priv;
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ali6117_log("ALI6117: reg_write(%04X, %02X)\n", addr, val);
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if (addr == 0x22)
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dev->reg_offset = val;
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else if (dev->reg_offset == 0x13)
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dev->unlocked = (val == 0xc5);
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else if (dev->unlocked) {
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ali6117_log("ALI6117: regs[%02X] = %02X\n", dev->reg_offset, val);
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switch (dev->reg_offset) {
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case 0x30: case 0x34: case 0x35: case 0x3e:
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case 0x3f: case 0x46: case 0x4c: case 0x6a:
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case 0x73:
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return; /* read-only registers */
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case 0x12:
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val &= 0xf7;
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/* FALL-THROUGH */
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case 0x14: case 0x15:
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dev->regs[dev->reg_offset] = val;
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ali6117_recalcmapping(dev);
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break;
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case 0x1e:
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val &= 0x07;
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break;
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case 0x20:
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val &= 0xbf;
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refresh_at_enable = (val & 0x02);
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break;
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case 0x31:
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/* TODO: fast gate A20 (bit 0) */
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val &= 0x21;
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break;
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case 0x32:
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val &= 0xc1;
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break;
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case 0x33:
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val &= 0xfd;
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break;
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case 0x36:
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val &= 0xf0;
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val |= dev->regs[dev->reg_offset];
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break;
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case 0x37:
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val &= 0xf5;
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break;
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case 0x3c:
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/* TODO: IDE channel selection (bit 0, secondary if set) */
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val &= 0x8f;
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break;
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case 0x44: case 0x45:
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val &= 0x3f;
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break;
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case 0x4a:
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val &= 0xfe;
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break;
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case 0x55:
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val &= 0x03;
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break;
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case 0x56:
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val &= 0xc7;
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break;
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case 0x58:
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val &= 0xc3;
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break;
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case 0x59:
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val &= 0x60;
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break;
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case 0x5b:
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val &= 0x1f;
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break;
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case 0x64:
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val &= 0xf7;
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break;
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case 0x66:
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val &= 0xe3;
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break;
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case 0x67:
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val &= 0xdf;
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break;
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case 0x69:
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val &= 0x50;
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break;
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case 0x6b:
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val &= 0x7f;
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break;
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case 0x6e: case 0x6f:
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val &= 0x03;
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break;
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case 0x71:
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val &= 0x1f;
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break;
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}
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dev->regs[dev->reg_offset] = val;
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}
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}
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static uint8_t
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ali6117_reg_read(uint16_t addr, void *priv)
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{
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ali6117_t *dev = (ali6117_t *) priv;
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uint8_t ret;
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if (addr == 0x22)
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ret = dev->reg_offset;
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else
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ret = dev->regs[dev->reg_offset];
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ali6117_log("ALI6117: reg_read(%04X) = %02X\n", dev->reg_offset, ret);
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return ret;
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}
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static void
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ali6117_reset(void *priv)
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{
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ali6117_t *dev = (ali6117_t *) priv;
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ali6117_log("ALI6117: reset()\n");
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memset(dev->regs, 0, sizeof(dev->regs));
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dev->regs[0x11] = 0xf8;
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dev->regs[0x12] = 0x20;
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dev->regs[0x17] = 0xff;
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dev->regs[0x18] = 0xf0;
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dev->regs[0x1a] = 0xff;
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dev->regs[0x1b] = 0xf0;
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dev->regs[0x1d] = 0xff;
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dev->regs[0x20] = 0x80;
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dev->regs[0x30] = 0x08;
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dev->regs[0x31] = 0x01;
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dev->regs[0x34] = 0x04; /* enable internal RTC */
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dev->regs[0x35] = 0x20; /* enable internal KBC */
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dev->regs[0x36] = (dev->local & 0x4); /* M6117D ID */
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}
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static void
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ali6117_setup(ali6117_t *dev)
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{
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ali6117_log("ALI6117: setup()\n");
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/* Main register interface */
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io_sethandler(0x22, 2,
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ali6117_reg_read, NULL, NULL, ali6117_reg_write, NULL, NULL, dev);
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}
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static void
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ali6117_close(void *priv)
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{
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ali6117_t *dev = (ali6117_t *) priv;
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ali6117_log("ALI6117: close()\n");
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io_removehandler(0x22, 2,
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ali6117_reg_read, NULL, NULL, ali6117_reg_write, NULL, NULL, dev);
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free(dev);
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}
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static void *
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ali6117_init(const device_t *info)
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{
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ali6117_log("ALI6117: init()\n");
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ali6117_t *dev = (ali6117_t *) malloc(sizeof(ali6117_t));
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memset(dev, 0, sizeof(ali6117_t));
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dev->local = info->local;
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device_add(&ide_isa_device);
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ali6117_setup(dev);
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ali6117_reset(dev);
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pci_elcr_io_disable();
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refresh_at_enable = 0;
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return dev;
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}
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const device_t ali6117d_device =
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{
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"ALi M6117D",
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DEVICE_AT,
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0x2,
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ali6117_init,
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ali6117_close,
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ali6117_reset,
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NULL,
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NULL,
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NULL,
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NULL
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};
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@@ -125,7 +125,7 @@ stpc_recalcmapping(stpc_t *dev)
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size = 0x4000;
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base = 0xc0000 + (size * ((reg * 4) + bitpair));
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}
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stpc_log("STPC: Shadowing for %05x-%05x (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1));
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stpc_log("STPC: Shadowing for %05X-%05X (reg %02X bp %d wmask %02X rmask %02X) =", base, base + size - 1, 0x25 + reg, bitpair, 1 << (bitpair * 2), 1 << ((bitpair * 2) + 1));
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state = 0;
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if (dev->regs[0x25 + reg] & (1 << (bitpair * 2))) {
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@@ -446,9 +446,9 @@ stpc_ide_read(int func, int addr, void *priv)
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uint8_t ret;
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if (func > 0)
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ret = 0xff;
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ret = 0xff;
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else {
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ret = dev->pci_conf[2][addr];
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ret = dev->pci_conf[2][addr];
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if (addr == 0x48) {
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ret &= 0xfc;
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ret |= (!!(dev->bm[0]->status & 0x04));
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@@ -467,8 +467,8 @@ stpc_isab_write(int func, int addr, uint8_t val, void *priv)
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stpc_t *dev = (stpc_t *) priv;
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if (func == 1 && !(dev->local & STPC_IDE_ATLAS)) {
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stpc_ide_write(0, addr, val, priv);
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return;
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stpc_ide_write(0, addr, val, priv);
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return;
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}
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stpc_log("STPC: isab_write(%d, %02X, %02X)\n", func, addr, val);
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@@ -498,11 +498,11 @@ stpc_isab_read(int func, int addr, void *priv)
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uint8_t ret;
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if ((func == 1) && !(dev->local & STPC_IDE_ATLAS))
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ret = stpc_ide_read(0, addr, priv);
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ret = stpc_ide_read(0, addr, priv);
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else if (func > 0)
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ret = 0xff;
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ret = 0xff;
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else
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ret = dev->pci_conf[1][addr];
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ret = dev->pci_conf[1][addr];
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stpc_log("STPC: isab_read(%d, %02X) = %02X\n", func, addr, ret);
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return ret;
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@@ -552,9 +552,9 @@ stpc_usb_read(int func, int addr, void *priv)
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uint8_t ret;
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if (func > 0)
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ret = 0xff;
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ret = 0xff;
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else
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||||
ret = dev->pci_conf[3][addr];
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ret = dev->pci_conf[3][addr];
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||||
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||||
stpc_log("STPC: usb_read(%d, %02X) = %02X\n", func, addr, ret);
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return ret;
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@@ -596,32 +596,32 @@ stpc_serial_handlers(uint8_t val)
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{
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stpc_serial_t *dev;
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if (!(dev = device_get_priv(&stpc_serial_device))) {
|
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stpc_log("STPC: Not remapping UARTs, disabled by strap (raw %02X)\n", val);
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return 0;
|
||||
stpc_log("STPC: Not remapping UARTs, disabled by strap (raw %02X)\n", val);
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint16_t uart0_io = 0x3f8, uart0_irq = 4, uart1_io = 0x3f8, uart1_irq = 3;
|
||||
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if (val & 0x10)
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||||
uart1_io -= 0x100;
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||||
uart1_io -= 0x100;
|
||||
if (val & 0x20)
|
||||
uart1_io -= 0x10;
|
||||
uart1_io -= 0x10;
|
||||
if (val & 0x40)
|
||||
uart0_io -= 0x100;
|
||||
uart0_io -= 0x100;
|
||||
if (val & 0x80)
|
||||
uart0_io -= 0x10;
|
||||
uart0_io -= 0x10;
|
||||
|
||||
if (uart0_io == uart1_io) {
|
||||
/* Apply defaults if both UARTs are set to the same address. */
|
||||
stpc_log("STPC: Both UARTs set to %02X, resetting to defaults\n", uart0_io);
|
||||
uart0_io = 0x3f8;
|
||||
uart1_io = 0x2f8;
|
||||
/* Apply defaults if both UARTs are set to the same address. */
|
||||
stpc_log("STPC: Both UARTs set to %02X, resetting to defaults\n", uart0_io);
|
||||
uart0_io = 0x3f8;
|
||||
uart1_io = 0x2f8;
|
||||
}
|
||||
|
||||
if (uart0_io < 0x300) {
|
||||
/* The address for UART0 defines the IRQs for both ports. */
|
||||
uart0_irq = 3;
|
||||
uart1_irq = 4;
|
||||
/* The address for UART0 defines the IRQs for both ports. */
|
||||
uart0_irq = 3;
|
||||
uart1_irq = 4;
|
||||
}
|
||||
|
||||
stpc_log("STPC: Remapping UART0 to %04X %d and UART1 to %04X %d (raw %02X)\n", uart0_io, uart0_irq, uart1_io, uart1_irq, val);
|
||||
@@ -696,7 +696,7 @@ stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
|
||||
case 0x56: case 0x57:
|
||||
elcr_write(dev->reg_offset, val, NULL);
|
||||
if (dev->reg_offset == 0x57)
|
||||
refresh_at_enable = val & 0x01;
|
||||
refresh_at_enable = (val & 0x01);
|
||||
break;
|
||||
|
||||
case 0x59:
|
||||
@@ -719,16 +719,16 @@ stpc_reg_read(uint16_t addr, void *priv)
|
||||
if (addr == 0x22)
|
||||
ret = dev->reg_offset;
|
||||
else if (dev->reg_offset >= 0xc0)
|
||||
return 0xff; /* Cyrix CPU registers: let the CPU code handle these */
|
||||
return 0xff; /* Cyrix CPU registers: let the CPU code handle these */
|
||||
else if ((dev->reg_offset == 0x56) || (dev->reg_offset == 0x57)) {
|
||||
/* ELCR is in here, not in port 4D0h. */
|
||||
/* ELCR is in here, not in port 4D0h. */
|
||||
ret = elcr_read(dev->reg_offset, NULL);
|
||||
if (dev->reg_offset == 0x57)
|
||||
ret |= (dev->regs[dev->reg_offset] & 0x01);
|
||||
} else
|
||||
ret = dev->regs[dev->reg_offset];
|
||||
|
||||
stpc_log("STPC: reg_read(%04X) = %02X\n", addr, ret);
|
||||
stpc_log("STPC: reg_read(%04X) = %02X\n", dev->reg_offset, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -743,9 +743,9 @@ stpc_reset(void *priv)
|
||||
memset(dev->regs, 0, sizeof(dev->regs));
|
||||
dev->regs[0x7b] = 0xff;
|
||||
if (device_get_priv(&stpc_lpt_device))
|
||||
dev->regs[0x4c] |= 0x80; /* LPT strap */
|
||||
dev->regs[0x4c] |= 0x80; /* LPT strap */
|
||||
if (stpc_serial_handlers(0x00))
|
||||
dev->regs[0x4c] |= 0x03; /* UART straps */
|
||||
dev->regs[0x4c] |= 0x03; /* UART straps */
|
||||
}
|
||||
|
||||
|
||||
@@ -763,14 +763,14 @@ stpc_setup(stpc_t *dev)
|
||||
/* Client */
|
||||
dev->pci_conf[0][0x00] = 0x0e;
|
||||
dev->pci_conf[0][0x01] = 0x10;
|
||||
dev->pci_conf[0][0x02] = 0x64;
|
||||
dev->pci_conf[0][0x03] = 0x05;
|
||||
dev->pci_conf[0][0x02] = 0x64;
|
||||
dev->pci_conf[0][0x03] = 0x05;
|
||||
} else {
|
||||
/* Atlas, Elite, Consumer II */
|
||||
dev->pci_conf[0][0x00] = 0x4a;
|
||||
dev->pci_conf[0][0x01] = 0x10;
|
||||
dev->pci_conf[0][0x02] = 0x0a;
|
||||
dev->pci_conf[0][0x03] = 0x02;
|
||||
dev->pci_conf[0][0x02] = 0x0a;
|
||||
dev->pci_conf[0][0x03] = 0x02;
|
||||
}
|
||||
|
||||
dev->pci_conf[0][0x04] = 0x07;
|
||||
@@ -785,26 +785,26 @@ stpc_setup(stpc_t *dev)
|
||||
/* Client */
|
||||
dev->pci_conf[1][0x00] = 0x0e;
|
||||
dev->pci_conf[1][0x01] = 0x10;
|
||||
dev->pci_conf[1][0x02] = 0xcc;
|
||||
dev->pci_conf[1][0x03] = 0x55;
|
||||
dev->pci_conf[1][0x02] = 0xcc;
|
||||
dev->pci_conf[1][0x03] = 0x55;
|
||||
} else if (dev->local & STPC_ISAB_CONSUMER2) {
|
||||
/* Consumer II */
|
||||
dev->pci_conf[1][0x00] = 0x4a;
|
||||
dev->pci_conf[1][0x01] = 0x10;
|
||||
dev->pci_conf[1][0x02] = 0x0b;
|
||||
dev->pci_conf[1][0x03] = 0x02;
|
||||
dev->pci_conf[1][0x02] = 0x0b;
|
||||
dev->pci_conf[1][0x03] = 0x02;
|
||||
} else if (dev->local & STPC_IDE_ATLAS) {
|
||||
/* Atlas */
|
||||
dev->pci_conf[1][0x00] = 0x4a;
|
||||
dev->pci_conf[1][0x01] = 0x10;
|
||||
dev->pci_conf[1][0x02] = 0x10;
|
||||
dev->pci_conf[1][0x03] = 0x02;
|
||||
dev->pci_conf[1][0x02] = 0x10;
|
||||
dev->pci_conf[1][0x03] = 0x02;
|
||||
} else {
|
||||
/* Elite */
|
||||
dev->pci_conf[1][0x00] = 0x4a;
|
||||
dev->pci_conf[1][0x01] = 0x10;
|
||||
dev->pci_conf[1][0x02] = 0x1a;
|
||||
dev->pci_conf[1][0x03] = 0x02;
|
||||
dev->pci_conf[1][0x02] = 0x1a;
|
||||
dev->pci_conf[1][0x03] = 0x02;
|
||||
}
|
||||
|
||||
dev->pci_conf[1][0x04] = 0x0f;
|
||||
@@ -830,11 +830,11 @@ stpc_setup(stpc_t *dev)
|
||||
}
|
||||
|
||||
if (dev->local & STPC_IDE_ATLAS) {
|
||||
dev->pci_conf[2][0x02] = 0x28;
|
||||
dev->pci_conf[2][0x03] = 0x02;
|
||||
dev->pci_conf[2][0x02] = 0x28;
|
||||
dev->pci_conf[2][0x03] = 0x02;
|
||||
} else {
|
||||
dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02];
|
||||
dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03];
|
||||
dev->pci_conf[2][0x02] = dev->pci_conf[1][0x02];
|
||||
dev->pci_conf[2][0x03] = dev->pci_conf[1][0x03];
|
||||
}
|
||||
|
||||
dev->pci_conf[2][0x06] = 0x80;
|
||||
@@ -866,22 +866,22 @@ stpc_setup(stpc_t *dev)
|
||||
|
||||
/* USB */
|
||||
if (dev->usb) {
|
||||
dev->pci_conf[3][0x00] = 0x4a;
|
||||
dev->pci_conf[3][0x01] = 0x10;
|
||||
dev->pci_conf[3][0x02] = 0x30;
|
||||
dev->pci_conf[3][0x03] = 0x02;
|
||||
dev->pci_conf[3][0x00] = 0x4a;
|
||||
dev->pci_conf[3][0x01] = 0x10;
|
||||
dev->pci_conf[3][0x02] = 0x30;
|
||||
dev->pci_conf[3][0x03] = 0x02;
|
||||
|
||||
dev->pci_conf[3][0x06] = 0x80;
|
||||
dev->pci_conf[3][0x07] = 0x02;
|
||||
dev->pci_conf[3][0x06] = 0x80;
|
||||
dev->pci_conf[3][0x07] = 0x02;
|
||||
|
||||
dev->pci_conf[3][0x09] = 0x10;
|
||||
dev->pci_conf[3][0x0a] = 0x03;
|
||||
dev->pci_conf[3][0x0b] = 0x0c;
|
||||
dev->pci_conf[3][0x09] = 0x10;
|
||||
dev->pci_conf[3][0x0a] = 0x03;
|
||||
dev->pci_conf[3][0x0b] = 0x0c;
|
||||
|
||||
/* NOTE: This is an erratum in the STPC Atlas programming manual, the programming manuals for the other
|
||||
STPC chipsets say 0x80, which is indeed multi-function (as the STPC Atlas programming manual
|
||||
indicates as well, and Windows 2000 also issues a 0x7B STOP error if it is 0x40. */
|
||||
dev->pci_conf[3][0x0e] = /*0x40*/ 0x80;
|
||||
dev->pci_conf[3][0x0e] = /*0x40*/ 0x80;
|
||||
}
|
||||
|
||||
/* PCI setup */
|
||||
@@ -919,10 +919,10 @@ stpc_init(const device_t *info)
|
||||
pci_add_card(0x0B, stpc_nb_read, stpc_nb_write, dev);
|
||||
dev->ide_slot = pci_add_card(0x0C, stpc_isab_read, stpc_isab_write, dev);
|
||||
if (dev->local & STPC_IDE_ATLAS)
|
||||
dev->ide_slot = pci_add_card(0x0D, stpc_ide_read, stpc_ide_write, dev);
|
||||
dev->ide_slot = pci_add_card(0x0D, stpc_ide_read, stpc_ide_write, dev);
|
||||
if (dev->local & STPC_USB) {
|
||||
dev->usb = device_add(&usb_device);
|
||||
pci_add_card(0x0E, stpc_usb_read, stpc_usb_write, dev);
|
||||
dev->usb = device_add(&usb_device);
|
||||
pci_add_card(0x0E, stpc_usb_read, stpc_usb_write, dev);
|
||||
}
|
||||
|
||||
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
|
||||
@@ -990,38 +990,38 @@ stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val)
|
||||
uint8_t old_addr = (dev->reg1 & 0x03), new_addr = (val & 0x03);
|
||||
|
||||
switch (old_addr) {
|
||||
case 0x1:
|
||||
lpt3_remove();
|
||||
break;
|
||||
case 0x1:
|
||||
lpt3_remove();
|
||||
break;
|
||||
|
||||
case 0x2:
|
||||
lpt1_remove();
|
||||
break;
|
||||
case 0x2:
|
||||
lpt1_remove();
|
||||
break;
|
||||
|
||||
case 0x3:
|
||||
lpt2_remove();
|
||||
break;
|
||||
case 0x3:
|
||||
lpt2_remove();
|
||||
break;
|
||||
}
|
||||
|
||||
switch (new_addr) {
|
||||
case 0x1:
|
||||
stpc_log("STPC: Remapping parallel port to LPT3\n");
|
||||
lpt3_init(0x3bc);
|
||||
break;
|
||||
case 0x1:
|
||||
stpc_log("STPC: Remapping parallel port to LPT3\n");
|
||||
lpt3_init(0x3bc);
|
||||
break;
|
||||
|
||||
case 0x2:
|
||||
stpc_log("STPC: Remapping parallel port to LPT1\n");
|
||||
lpt1_init(0x378);
|
||||
break;
|
||||
case 0x2:
|
||||
stpc_log("STPC: Remapping parallel port to LPT1\n");
|
||||
lpt1_init(0x378);
|
||||
break;
|
||||
|
||||
case 0x3:
|
||||
stpc_log("STPC: Remapping parallel port to LPT2\n");
|
||||
lpt2_init(0x278);
|
||||
break;
|
||||
case 0x3:
|
||||
stpc_log("STPC: Remapping parallel port to LPT2\n");
|
||||
lpt2_init(0x278);
|
||||
break;
|
||||
|
||||
default:
|
||||
stpc_log("STPC: Disabling parallel port\n");
|
||||
break;
|
||||
default:
|
||||
stpc_log("STPC: Disabling parallel port\n");
|
||||
break;
|
||||
}
|
||||
|
||||
dev->reg1 = (val & 0x08);
|
||||
@@ -1036,22 +1036,22 @@ stpc_lpt_write(uint16_t addr, uint8_t val, void *priv)
|
||||
stpc_lpt_t *dev = (stpc_lpt_t *) priv;
|
||||
|
||||
if (dev->unlocked < 2) {
|
||||
/* Cheat a little bit: in reality, any write to any
|
||||
I/O port is supposed to reset the unlock counter. */
|
||||
if ((addr == 0x3f0) && (val == 0x55))
|
||||
dev->unlocked++;
|
||||
else
|
||||
dev->unlocked = 0;
|
||||
/* Cheat a little bit: in reality, any write to any
|
||||
I/O port is supposed to reset the unlock counter. */
|
||||
if ((addr == 0x3f0) && (val == 0x55))
|
||||
dev->unlocked++;
|
||||
else
|
||||
dev->unlocked = 0;
|
||||
} else if (addr == 0x3f0) {
|
||||
if (val == 0xaa)
|
||||
dev->unlocked = 0;
|
||||
else
|
||||
dev->offset = val;
|
||||
if (val == 0xaa)
|
||||
dev->unlocked = 0;
|
||||
else
|
||||
dev->offset = val;
|
||||
} else if (dev->offset == 1) {
|
||||
/* dev->reg1 is set by stpc_lpt_handlers */
|
||||
stpc_lpt_handlers(dev, val);
|
||||
/* dev->reg1 is set by stpc_lpt_handlers */
|
||||
stpc_lpt_handlers(dev, val);
|
||||
} else if (dev->offset == 4) {
|
||||
dev->reg4 = (val & 0x03);
|
||||
dev->reg4 = (val & 0x03);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user