Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there.

src/cpu/386_common.c

@@ -61,7 +61,8 @@ extern int optype;
 extern uint32_t pccache;
 
 
-int in_sys = 0;
+int in_sys = 0, unmask_a20_in_smm = 0;
+uint32_t old_rammask = 0xffffffff;
 
 smram_t temp_smram[2];
 
@@ -1100,6 +1101,13 @@ enter_smm(int in_hlt)
 
     smm_in_hlt = in_hlt;
 
+    if (unmask_a20_in_smm) {
+	old_rammask = rammask;
+	rammask = cpu_16bitbus ? 0xFFFFFF : 0xFFFFFFFF;
+
+	flushmmucache();
+    }
+
     CPU_BLOCK_END();
 }
 
@@ -1151,6 +1159,12 @@ leave_smm(void)
 	x386_common_log("Reading %08X from memory at %08X to array element %i\n", saved_state[n], smram_state, n);
     }
 
+    if (unmask_a20_in_smm) {
+	rammask = old_rammask;
+
+	flushmmucache();
+    }
+
     x386_common_log("New SMBASE: %08X (%08X)\n", saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET], saved_state[66]);
     if (is_pentium)			/* Intel P5 (Pentium) */
 	smram_restore_state_p5(saved_state);

src/cpu/808x.c

@@ -977,6 +977,7 @@ reset_common(int hard)
 
     in_smm = smi_latched = 0;
     smi_line = smm_in_hlt = 0;
+    smi_block = 0;
 
     if (hard) {
 	smbase = 0x00030000;

src/cpu/cpu.c

@@ -137,6 +137,7 @@ const OpFn	*x86_opcodes_REPNE;
 const OpFn	*x86_opcodes_3DNOW;
 
 int in_smm = 0, smi_line = 0, smi_latched = 0, smm_in_hlt = 0;
+int smi_block = 0;
 uint32_t smbase = 0x30000;
 
 CPU		*cpu_s;
@@ -358,6 +359,7 @@ cpu_set(void)
         cpu_s = &machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective];
 
 	cpu_alt_reset = 0;
+	unmask_a20_in_smm = 0;
 
         CPUID        = cpu_s->cpuid_model;
         is8086       = (cpu_s->cpu_type > CPU_8088);

src/cpu/cpu.h

@@ -412,6 +412,7 @@ extern int	hasfpu;
 extern uint32_t	cpu_features;
 
 extern int	in_smm, smi_line, smi_latched, smm_in_hlt;
+extern int	smi_block;
 extern uint32_t	smbase;
 
 #ifdef USE_NEW_DYNAREC
@@ -497,7 +498,8 @@ extern int	timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
 extern int	timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
 extern int	timing_misaligned;
 
-extern int	in_sys;
+extern int	in_sys, unmask_a20_in_smm;
+extern uint32_t	old_rammask;
 
 extern uint16_t	cpu_fast_off_count, cpu_fast_off_val;
 extern uint32_t	cpu_fast_off_flags;