Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there.

src/cpu/386_common.c

@@ -61,7 +61,8 @@ extern int optype;
 extern uint32_t pccache;
 
 
-int in_sys = 0;
+int in_sys = 0, unmask_a20_in_smm = 0;
+uint32_t old_rammask = 0xffffffff;
 
 smram_t temp_smram[2];
 
@@ -1100,6 +1101,13 @@ enter_smm(int in_hlt)
 
     smm_in_hlt = in_hlt;
 
+    if (unmask_a20_in_smm) {
+	old_rammask = rammask;
+	rammask = cpu_16bitbus ? 0xFFFFFF : 0xFFFFFFFF;
+
+	flushmmucache();
+    }
+
     CPU_BLOCK_END();
 }
 
@@ -1151,6 +1159,12 @@ leave_smm(void)
 	x386_common_log("Reading %08X from memory at %08X to array element %i\n", saved_state[n], smram_state, n);
     }
 
+    if (unmask_a20_in_smm) {
+	rammask = old_rammask;
+
+	flushmmucache();
+    }
+
     x386_common_log("New SMBASE: %08X (%08X)\n", saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET], saved_state[66]);
     if (is_pentium)			/* Intel P5 (Pentium) */
 	smram_restore_state_p5(saved_state);