Fixed cycles accumulation in update_tsc() when cache is enabled (and the actual recompiler kicks in), and also fixed a warning in the 82091AA code.

src/cpu/386_dynarec.c

@@ -276,12 +276,17 @@ static void prefetch_flush()
 static int cycles_main = 0, cycles_old = 0;
 static uint64_t tsc_old = 0;
 
+int acycs = 0;
+
 void update_tsc(void)
 {
     int cycdiff;
     uint64_t delta;
 
-    cycdiff = cycles_old - cycles;
+    if (CACHE_ON())
+	cycdiff = acycs;
+    else
+	cycdiff = cycles_old - cycles;
     delta = tsc - tsc_old;
     if (delta > 0) {
 	/* TSC has changed, this means interim timer processing has happened,

src/cpu/cpu.c

@@ -362,6 +362,8 @@ cpu_set(void)
 	cpu_effective = cpu;
         cpu_s = &machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective];
 
+	acycs = 0;
+
 	cpu_alt_reset = 0;
 	unmask_a20_in_smm = 0;
 

src/cpu/cpu.h

@@ -503,6 +503,8 @@ extern int	timing_misaligned;
 extern int	in_sys, unmask_a20_in_smm;
 extern uint32_t	old_rammask;
 
+extern int	acycs;
+
 extern uint16_t	cpu_fast_off_count, cpu_fast_off_val;
 extern uint32_t	cpu_fast_off_flags;