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clang-format in src/scsi/

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This commit is contained in:
Jasmine Iwanek
2022-09-18 17:17:15 -04:00
parent 99893d1175
commit 97a7459fd4
11 changed files with 10144 additions and 10439 deletions
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33
src/scsi/scsi.c
View File

@@ -45,12 +45,10 @@
# include "scsi_wd33c93.h"
#endif
int scsi_card_current[SCSI_BUS_MAX] = { 0, 0 };
static uint8_t next_scsi_bus = 0;
static const device_t scsi_none_device = {
.name = "None",
.internal_name = "none",
@@ -65,14 +63,12 @@ static const device_t scsi_none_device = {
.config = NULL
};
typedef const struct {
const device_t *device;
} SCSI_CARD;
static SCSI_CARD scsi_cards[] = {
// clang-format off
// clang-format off
{ &scsi_none_device, },
{ &aha154xa_device, },
{ &aha154xb_device, },
@@ -107,17 +103,15 @@ static SCSI_CARD scsi_cards[] = {
{ &buslogic_445s_device, },
{ &buslogic_445c_device, },
{ NULL, },
// clang-format on
// clang-format on
};
void
scsi_reset(void)
{
next_scsi_bus = 0;
}
uint8_t
scsi_get_bus(void)
{
@@ -131,40 +125,36 @@ scsi_get_bus(void)
return ret;
}
int
scsi_card_available(int card)
{
if (scsi_cards[card].device)
return(device_available(scsi_cards[card].device));
return (device_available(scsi_cards[card].device));
return(1);
return (1);
}
const device_t *
scsi_card_getdevice(int card)
{
return(scsi_cards[card].device);
return (scsi_cards[card].device);
}
int
scsi_card_has_config(int card)
{
if (! scsi_cards[card].device) return(0);
if (!scsi_cards[card].device)
return (0);
return(device_has_config(scsi_cards[card].device) ? 1 : 0);
return (device_has_config(scsi_cards[card].device) ? 1 : 0);
}
char *
scsi_card_get_internal_name(int card)
{
return device_get_internal_name(scsi_cards[card].device);
}
int
scsi_card_get_from_internal_name(char *s)
{
@@ -172,14 +162,13 @@ scsi_card_get_from_internal_name(char *s)
while (scsi_cards[c].device != NULL) {
if (!strcmp((char *) scsi_cards[c].device->internal_name, s))
return(c);
return (c);
c++;
}
return(0);
return (0);
}
void
scsi_card_init(void)
{
@@ -190,7 +179,7 @@ scsi_card_init(void)
if (machine_has_flags(machine, MACHINE_SCSI))
max--;
/* Do not initialize any controllers if we have do not have any SCSI
/* Do not initialize any controllers if we have do not have any SCSI
bus left. */
if (max > 0) {
for (i = 0; i < max; i++) {

175
src/scsi/scsi_aha154x.c
View File

@@ -44,7 +44,6 @@
#include <86box/scsi_aha154x.h>
#include <86box/scsi_x54x.h>
enum {
AHA_154xA,
AHA_154xB,
@@ -54,8 +53,6 @@ enum {
AHA_1640
};
#define CMD_WRITE_EEPROM 0x22 /* UNDOC: Write EEPROM */
#define CMD_READ_EEPROM 0x23 /* UNDOC: Read EEPROM */
#define CMD_SHADOW_RAM 0x24 /* UNDOC: BIOS shadow ram */
@@ -66,7 +63,6 @@ enum {
#define CMD_MBENABLE 0x29 /* set mailbox interface enable */
#define CMD_BIOS_SCSI 0x82 /* start ROM BIOS SCSI command */
uint16_t aha_ports[] = {
0x0330, 0x0334, 0x0230, 0x0234,
0x0130, 0x0134, 0x0000, 0x0000
@@ -74,8 +70,7 @@ uint16_t aha_ports[] = {
static uint8_t *aha1542cp_pnp_rom = NULL;
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct {
uint8_t CustomerSignature[20];
uint8_t uAutoRetry;
@@ -86,11 +81,9 @@ typedef struct {
} aha_setup_t;
#pragma pack(pop)
#ifdef ENABLE_AHA154X_LOG
int aha_do_log = ENABLE_AHA154X_LOG;
static void
aha_log(const char *fmt, ...)
{
@@ -103,10 +96,9 @@ aha_log(const char *fmt, ...)
}
}
#else
#define aha_log(fmt, ...)
# define aha_log(fmt, ...)
#endif
/*
* Write data to the BIOS space.
*
@@ -120,7 +112,7 @@ aha_log(const char *fmt, ...)
static void
aha_mem_write(uint32_t addr, uint8_t val, void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
addr &= 0x3fff;
@@ -128,11 +120,10 @@ aha_mem_write(uint32_t addr, uint8_t val, void *priv)
dev->shadow_ram[addr & (dev->rom_shramsz - 1)] = val;
}
static uint8_t
aha_mem_read(uint32_t addr, void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
rom_t *rom = &dev->bios;
addr &= 0x3fff;
@@ -140,42 +131,39 @@ aha_mem_read(uint32_t addr, void *priv)
if ((addr >= dev->rom_shram) && (dev->shram_mode & 2))
return dev->shadow_ram[addr & (dev->rom_shramsz - 1)];
return(rom->rom[addr]);
return (rom->rom[addr]);
}
static uint8_t
aha154x_shram(x54x_t *dev, uint8_t cmd)
{
/* If not supported, give up. */
if (dev->rom_shram == 0x0000) return(0x04);
if (dev->rom_shram == 0x0000)
return (0x04);
/* Bit 0 = Shadow RAM write enable;
Bit 1 = Shadow RAM read enable. */
dev->shram_mode = cmd;
/* Firmware expects 04 status. */
return(0x04);
return (0x04);
}
static void
aha_eeprom_save(x54x_t *dev)
{
FILE *f;
f = nvr_fopen(dev->nvr_path, "wb");
if (f)
{
if (f) {
fwrite(dev->nvr, 1, NVR_SIZE, f);
fclose(f);
f = NULL;
}
}
static uint8_t
aha154x_eeprom(x54x_t *dev, uint8_t cmd,uint8_t arg,uint8_t len,uint8_t off,uint8_t *bufp)
aha154x_eeprom(x54x_t *dev, uint8_t cmd, uint8_t arg, uint8_t len, uint8_t off, uint8_t *bufp)
{
uint8_t r = 0xff;
int c;
@@ -184,7 +172,8 @@ aha154x_eeprom(x54x_t *dev, uint8_t cmd,uint8_t arg,uint8_t len,uint8_t off,uint
dev->name, cmd, arg, len, off);
/* Only if we can handle it.. */
if (dev->nvr == NULL) return(r);
if (dev->nvr == NULL)
return (r);
if (cmd == 0x22) {
/* Write data to the EEPROM. */
@@ -209,17 +198,16 @@ aha154x_eeprom(x54x_t *dev, uint8_t cmd,uint8_t arg,uint8_t len,uint8_t off,uint
r = len;
}
return(r);
return (r);
}
/* Map either the main or utility (Select) ROM into the memory space. */
static uint8_t
aha154x_mmap(x54x_t *dev, uint8_t cmd)
{
aha_log("%s: MEMORY cmd=%02x\n", dev->name, cmd);
switch(cmd) {
switch (cmd) {
case 0x26:
/* Disable the mapper, so, set ROM1 active. */
dev->bios.rom = dev->rom1;
@@ -231,41 +219,37 @@ aha154x_mmap(x54x_t *dev, uint8_t cmd)
break;
}
return(0);
return (0);
}
static uint8_t
aha_get_host_id(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
return dev->nvr[0] & 0x07;
}
static uint8_t
aha_get_irq(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
return (dev->nvr[1] & 0x07) + 9;
}
static uint8_t
aha_get_dma(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
return (dev->nvr[1] >> 4) & 0x07;
}
static uint8_t
aha_cmd_is_fast(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
if (dev->Command == CMD_BIOS_SCSI)
return 1;
@@ -273,11 +257,10 @@ aha_cmd_is_fast(void *p)
return 0;
}
static uint8_t
aha_fast_cmds(void *p, uint8_t cmd)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
if (cmd == CMD_BIOS_SCSI) {
dev->BIOSMailboxReq++;
@@ -287,11 +270,10 @@ aha_fast_cmds(void *p, uint8_t cmd)
return 0;
}
static uint8_t
aha_param_len(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
switch (dev->Command) {
case CMD_BIOS_MBINIT:
@@ -324,20 +306,18 @@ aha_param_len(void *p)
}
}
static uint8_t
aha_cmds(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
MailboxInit_t *mbi;
if (! dev->CmdParamLeft) {
if (!dev->CmdParamLeft) {
aha_log("Running Operation Code 0x%02X\n", dev->Command);
switch (dev->Command) {
case CMD_WRITE_EEPROM: /* write EEPROM */
/* Sent by CF BIOS. */
dev->DataReplyLeft =
aha154x_eeprom(dev,
dev->DataReplyLeft = aha154x_eeprom(dev,
dev->Command,
dev->CmdBuf[0],
dev->CmdBuf[1],
@@ -351,8 +331,7 @@ aha_cmds(void *p)
case CMD_READ_EEPROM: /* read EEPROM */
/* Sent by CF BIOS. */
dev->DataReplyLeft =
aha154x_eeprom(dev,
dev->DataReplyLeft = aha154x_eeprom(dev,
dev->Command,
dev->CmdBuf[0],
dev->CmdBuf[1],
@@ -380,7 +359,7 @@ aha_cmds(void *p)
/* Sent by CF BIOS. */
dev->flags |= X54X_MBX_24BIT;
mbi = (MailboxInit_t *)dev->CmdBuf;
mbi = (MailboxInit_t *) dev->CmdBuf;
dev->BIOSMailboxInit = 1;
dev->BIOSMailboxCount = mbi->Count;
@@ -398,8 +377,7 @@ aha_cmds(void *p)
case CMD_MEMORY_MAP_1: /* AHA memory mapper */
case CMD_MEMORY_MAP_2: /* AHA memory mapper */
/* Sent by CF BIOS. */
dev->DataReplyLeft =
aha154x_mmap(dev, dev->Command);
dev->DataReplyLeft = aha154x_mmap(dev, dev->Command);
break;
case CMD_EXTBIOS: /* Return extended BIOS information */
@@ -472,16 +450,15 @@ aha_cmds(void *p)
return 0;
}
static void
aha_setup_data(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
ReplyInquireSetupInformation *ReplyISI;
aha_setup_t *aha_setup;
ReplyISI = (ReplyInquireSetupInformation *)dev->DataBuf;
aha_setup = (aha_setup_t *)ReplyISI->VendorSpecificData;
ReplyISI = (ReplyInquireSetupInformation *) dev->DataBuf;
aha_setup = (aha_setup_t *) ReplyISI->VendorSpecificData;
ReplyISI->fSynchronousInitiationEnabled = dev->sync & 1;
ReplyISI->fParityCheckingEnabled = dev->parity & 1;
@@ -491,7 +468,6 @@ aha_setup_data(void *p)
aha_setup->uUnknown = 0xC2;
}
static void
aha_do_bios_mail(x54x_t *dev)
{
@@ -509,33 +485,31 @@ aha_do_bios_mail(x54x_t *dev)
}
}
static void
aha_callback(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
if (dev->BIOSMailboxInit && dev->BIOSMailboxReq)
aha_do_bios_mail(dev);
}
static uint8_t
aha_mca_read(int port, void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
return(dev->pos_regs[port & 7]);
return (dev->pos_regs[port & 7]);
}
static void
aha_mca_write(int port, uint8_t val, void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102) return;
if (port < 0x0102)
return;
/* Save the MCA register value. */
dev->pos_regs[port & 7] = val;
@@ -552,7 +526,8 @@ aha_mca_write(int port, uint8_t val, void *priv)
dev->DmaChannel = dev->pos_regs[5] & 0x0f;
/* Extract the BIOS ROM address info. */
if (! (dev->pos_regs[2] & 0x80)) switch(dev->pos_regs[3] & 0x38) {
if (!(dev->pos_regs[2] & 0x80))
switch (dev->pos_regs[3] & 0x38) {
case 0x38: /* [1]=xx11 1xxx */
dev->rom_addr = 0xDC000;
break;
@@ -576,7 +551,8 @@ aha_mca_write(int port, uint8_t val, void *priv)
case 0x10: /* [1]=xx01 0xxx */
dev->rom_addr = 0xC8000;
break;
} else {
}
else {
/* Disabled. */
dev->rom_addr = 0x000000;
}
@@ -627,16 +603,14 @@ aha_mca_write(int port, uint8_t val, void *priv)
}
}
static uint8_t
aha_mca_feedb(void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
return (dev->pos_regs[2] & 0x01);
}
static void
aha_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
@@ -672,16 +646,17 @@ aha_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
*/
if (dev->rom_ioaddr != 0x0000) {
/* Look up the I/O address in the table. */
for (i=0; i<8; i++)
if (aha_ports[i] == dev->Base) break;
for (i = 0; i < 8; i++)
if (aha_ports[i] == dev->Base)
break;
if (i == 8) {
aha_log("%s: invalid I/O address %04x selected!\n",
dev->name, dev->Base);
return;
}
dev->bios.rom[dev->rom_ioaddr] = (uint8_t)i;
dev->bios.rom[dev->rom_ioaddr] = (uint8_t) i;
/* Negation of the DIP switches to satify the checksum. */
dev->bios.rom[dev->rom_ioaddr + 1] = (uint8_t)((i ^ 0xff) + 1);
dev->bios.rom[dev->rom_ioaddr + 1] = (uint8_t) ((i ^ 0xff) + 1);
}
dev->Irq = config->irq[0].irq;
@@ -724,7 +699,6 @@ aha_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
}
}
/* Initialize the board's ROM BIOS. */
static void
aha_setbios(x54x_t *dev)
@@ -736,7 +710,8 @@ aha_setbios(x54x_t *dev)
int i;
/* Only if this device has a BIOS ROM. */
if (dev->bios_path == NULL) return;
if (dev->bios_path == NULL)
return;
/* Open the BIOS image file and make sure it exists. */
aha_log("%s: loading BIOS from '%s'\n", dev->name, dev->bios_path);
@@ -752,9 +727,9 @@ aha_setbios(x54x_t *dev)
* this special case, we can't: we may need WRITE access to the
* memory later on.
*/
(void)fseek(f, 0L, SEEK_END);
(void) fseek(f, 0L, SEEK_END);
temp = ftell(f);
(void)fseek(f, 0L, SEEK_SET);
(void) fseek(f, 0L, SEEK_SET);
/* Load first chunk of BIOS (which is the main BIOS, aka ROM1.) */
dev->rom1 = malloc(ROM_SIZE);
@@ -772,13 +747,13 @@ aha_setbios(x54x_t *dev)
free(dev->rom1);
if (dev->rom2 != NULL)
free(dev->rom2);
(void)fclose(f);
(void) fclose(f);
return;
}
temp = ftell(f);
if (temp > ROM_SIZE)
temp = ROM_SIZE;
(void)fclose(f);
(void) fclose(f);
/* Adjust BIOS size in chunks of 2K, as per BIOS spec. */
size = 0x10000;
@@ -819,20 +794,20 @@ aha_setbios(x54x_t *dev)
*/
if (dev->rom_ioaddr != 0x0000) {
/* Look up the I/O address in the table. */
for (i=0; i<8; i++)
if (aha_ports[i] == dev->Base) break;
for (i = 0; i < 8; i++)
if (aha_ports[i] == dev->Base)
break;
if (i == 8) {
aha_log("%s: invalid I/O address %04x selected!\n",
dev->name, dev->Base);
return;
}
dev->bios.rom[dev->rom_ioaddr] = (uint8_t)i;
dev->bios.rom[dev->rom_ioaddr] = (uint8_t) i;
/* Negation of the DIP switches to satify the checksum. */
dev->bios.rom[dev->rom_ioaddr + 1] = (uint8_t)((i ^ 0xff) + 1);
dev->bios.rom[dev->rom_ioaddr + 1] = (uint8_t) ((i ^ 0xff) + 1);
}
}
/* Get the SCSISelect code decompressor program from the microcode rom for the
AHA-1542CP. */
static void
@@ -842,7 +817,8 @@ aha_setmcode(x54x_t *dev)
FILE *f;
/* Only if this device has a BIOS ROM. */
if (dev->mcode_path == NULL) return;
if (dev->mcode_path == NULL)
return;
/* Open the microcode image file and make sure it exists. */
aha_log("%s: loading microcode from '%ls'\n", dev->name, dev->bios_path);
@@ -858,13 +834,13 @@ aha_setmcode(x54x_t *dev)
* this special case, we can't: we may need WRITE access to the
* memory later on.
*/
(void)fseek(f, 0L, SEEK_END);
(void) fseek(f, 0L, SEEK_END);
temp = ftell(f);
(void)fseek(f, 0L, SEEK_SET);
(void) fseek(f, 0L, SEEK_SET);
if (temp < (dev->cmd_33_offset + dev->cmd_33_len - 1)) {
aha_log("%s: microcode ROM size invalid!\n", dev->name);
(void)fclose(f);
(void) fclose(f);
return;
}
@@ -891,10 +867,9 @@ aha_setmcode(x54x_t *dev)
fseek(f, dev->cmd_33_offset, SEEK_SET);
(void) !fread(dev->cmd_33_buf, dev->cmd_33_len, 1, f);
(void)fclose(f);
(void) fclose(f);
}
static void
aha_initnvr(x54x_t *dev)
{
@@ -903,8 +878,8 @@ aha_initnvr(x54x_t *dev)
dev->nvr[0] |= (0x10 | 0x20 | 0x40);
if (dev->fdc_address == FDC_SECONDARY_ADDR)
dev->nvr[0] |= EE0_ALTFLOP;
dev->nvr[1] = dev->Irq-9; /* IRQ15 */
dev->nvr[1] |= (dev->DmaChannel<<4); /* DMA6 */
dev->nvr[1] = dev->Irq - 9; /* IRQ15 */
dev->nvr[1] |= (dev->DmaChannel << 4); /* DMA6 */
dev->nvr[2] = (EE2_HABIOS | /* BIOS enabled */
EE2_DYNSCAN | /* scan bus */
EE2_EXT1G | EE2_RMVOK); /* Imm return on seek */
@@ -913,7 +888,6 @@ aha_initnvr(x54x_t *dev)
EE6_RSTBUS); /* reset SCSI bus on boot*/
}
/* Initialize the board's EEPROM (NVR.) */
static void
aha_setnvr(x54x_t *dev)
@@ -921,10 +895,11 @@ aha_setnvr(x54x_t *dev)
FILE *f;
/* Only if this device has an EEPROM. */
if (dev->nvr_path == NULL) return;
if (dev->nvr_path == NULL)
return;
/* Allocate and initialize the EEPROM. */
dev->nvr = (uint8_t *)malloc(NVR_SIZE);
dev->nvr = (uint8_t *) malloc(NVR_SIZE);
memset(dev->nvr, 0x00, NVR_SIZE);
f = nvr_fopen(dev->nvr_path, "rb");
@@ -944,7 +919,6 @@ aha_setnvr(x54x_t *dev)
}
}
void
aha1542cp_close(void *priv)
{
@@ -956,7 +930,6 @@ aha1542cp_close(void *priv)
x54x_close(priv);
}
/* General initialization routine for all boards. */
static void *
aha_init(const device_t *info)
@@ -1002,7 +975,7 @@ aha_init(const device_t *info)
strcpy(dev->vendor, "Adaptec");
/* Perform per-board initialization. */
switch(dev->type) {
switch (dev->type) {
case AHA_154xA:
strcpy(dev->name, "AHA-154xA");
dev->fw_rev = "A003"; /* The 3.07 microcode says A006. */
@@ -1016,15 +989,13 @@ aha_init(const device_t *info)
case AHA_154xB:
strcpy(dev->name, "AHA-154xB");
switch(dev->Base) {
switch (dev->Base) {
case 0x0330:
dev->bios_path =
"roms/scsi/adaptec/aha1540b320_330.bin";
dev->bios_path = "roms/scsi/adaptec/aha1540b320_330.bin";
break;
case 0x0334:
dev->bios_path =
"roms/scsi/adaptec/aha1540b320_334.bin";
dev->bios_path = "roms/scsi/adaptec/aha1540b320_334.bin";
break;
}
dev->fw_rev = "A005"; /* The 3.2 microcode says A012. */
@@ -1135,7 +1106,7 @@ aha_init(const device_t *info)
}
}
return(dev);
return (dev);
}
// clang-format off

242
src/scsi/scsi_buslogic.c
View File

@@ -47,27 +47,26 @@
#include <86box/scsi_device.h>
#include <86box/scsi_x54x.h>
/*
* Auto SCSI structure which is located
* in host adapter RAM and contains several
* configuration parameters.
*/
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct {
uint8_t aInternalSignature[2];
uint8_t cbInformation;
uint8_t aHostAdaptertype[6];
uint8_t uReserved1;
uint8_t fFloppyEnabled :1,
fFloppySecondary :1,
fLevelSensitiveInterrupt:1,
uReserved2 :2,
uSystemRAMAreForBIOS :3;
uint8_t uDMAChannel :7,
fDMAAutoConfiguration :1,
uIrqChannel :7,
fIrqAutoConfiguration :1;
uint8_t fFloppyEnabled : 1,
fFloppySecondary : 1,
fLevelSensitiveInterrupt : 1,
uReserved2 : 2,
uSystemRAMAreForBIOS : 3;
uint8_t uDMAChannel : 7,
fDMAAutoConfiguration : 1,
uIrqChannel : 7,
fIrqAutoConfiguration : 1;
uint8_t uDMATransferRate;
uint8_t uSCSIId;
uint8_t uSCSIConfiguration;
@@ -115,7 +114,7 @@ typedef struct {
#pragma pack(pop)
/* The local RAM. */
#pragma pack(push,1)
#pragma pack(push, 1)
typedef union {
uint8_t u8View[256]; /* byte view */
struct { /* structured view */
@@ -126,7 +125,7 @@ typedef union {
#pragma pack(pop)
/** Structure for the INQUIRE_SETUP_INFORMATION reply. */
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct {
uint8_t uSignature;
uint8_t uCharacterD;
@@ -142,45 +141,45 @@ typedef struct {
#pragma pack(pop)
/* Structure for the INQUIRE_EXTENDED_SETUP_INFORMATION. */
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct {
uint8_t uBusType;
uint8_t uBiosAddress;
uint16_t u16ScatterGatherLimit;
uint8_t cMailbox;
uint32_t uMailboxAddressBase;
uint8_t uReserved1 :2,
fFastEISA :1,
uReserved2 :3,
fLevelSensitiveInterrupt:1,
uReserved3 :1;
uint8_t uReserved1 : 2,
fFastEISA : 1,
uReserved2 : 3,
fLevelSensitiveInterrupt : 1,
uReserved3 : 1;
uint8_t aFirmwareRevision[3];
uint8_t fHostWideSCSI :1,
fHostDifferentialSCSI :1,
fHostSupportsSCAM :1,
fHostUltraSCSI :1,
fHostSmartTermination :1,
uReserved4 :3;
uint8_t fHostWideSCSI : 1,
fHostDifferentialSCSI : 1,
fHostSupportsSCAM : 1,
fHostUltraSCSI : 1,
fHostSmartTermination : 1,
uReserved4 : 3;
} ReplyInquireExtendedSetupInformation;
#pragma pack(pop)
/* Structure for the INQUIRE_PCI_HOST_ADAPTER_INFORMATION reply. */
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct {
uint8_t IsaIOPort;
uint8_t IRQ;
uint8_t LowByteTerminated :1,
HighByteTerminated :1,
uReserved :2, /* Reserved. */
JP1 :1, /* Whatever that means. */
JP2 :1, /* Whatever that means. */
JP3 :1, /* Whatever that means. */
InformationIsValid :1;
uint8_t LowByteTerminated : 1,
HighByteTerminated : 1,
uReserved : 2, /* Reserved. */
JP1 : 1, /* Whatever that means. */
JP2 : 1, /* Whatever that means. */
JP3 : 1, /* Whatever that means. */
InformationIsValid : 1;
uint8_t uReserved2; /* Reserved. */
} BuslogicPCIInformation_t;
#pragma pack(pop)
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct
{
/** Data length. */
@@ -204,14 +203,14 @@ typedef struct
} ESCMD;
#pragma pack(pop)
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct {
uint8_t Count;
uint32_t Address;
} MailboxInitExtended_t;
#pragma pack(pop)
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct {
rom_t bios;
int ExtendedLUNCCBFormat;
@@ -229,7 +228,6 @@ typedef struct {
} buslogic_data_t;
#pragma pack(pop)
enum {
CHIP_BUSLOGIC_ISA_542B_1991_12_14,
CHIP_BUSLOGIC_ISA_545S_1992_10_05,
@@ -241,11 +239,9 @@ enum {
CHIP_BUSLOGIC_PCI_958D_1995_12_30
};
#ifdef ENABLE_BUSLOGIC_LOG
int buslogic_do_log = ENABLE_BUSLOGIC_LOG;
static void
buslogic_log(const char *fmt, ...)
{
@@ -258,15 +254,13 @@ buslogic_log(const char *fmt, ...)
}
}
#else
#define buslogic_log(fmt, ...)
# define buslogic_log(fmt, ...)
#endif
static char *
BuslogicGetNVRFileName(buslogic_data_t *bl)
{
switch(bl->chip)
{
switch (bl->chip) {
case CHIP_BUSLOGIC_ISA_542B_1991_12_14:
return "bt542b.nvr";
case CHIP_BUSLOGIC_ISA_545S_1992_10_05:
@@ -289,7 +283,6 @@ BuslogicGetNVRFileName(buslogic_data_t *bl)
}
}
static void
BuslogicAutoSCSIRamSetDefaults(x54x_t *dev, uint8_t safe)
{
@@ -338,7 +331,7 @@ BuslogicAutoSCSIRamSetDefaults(x54x_t *dev, uint8_t safe)
HALR->structured.autoSCSIData.uSystemRAMAreForBIOS = 6;
if (bl->chip != CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
switch(dev->DmaChannel) {
switch (dev->DmaChannel) {
case 5:
HALR->structured.autoSCSIData.uDMAChannel = 1;
break;
@@ -356,7 +349,7 @@ BuslogicAutoSCSIRamSetDefaults(x54x_t *dev, uint8_t safe)
HALR->structured.autoSCSIData.fDMAAutoConfiguration = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 0 : 1;
if (bl->chip != CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
switch(dev->Irq) {
switch (dev->Irq) {
case 9:
HALR->structured.autoSCSIData.uIrqChannel = 1;
break;
@@ -411,7 +404,6 @@ BuslogicAutoSCSIRamSetDefaults(x54x_t *dev, uint8_t safe)
HALR->structured.autoSCSIData.uHostAdapterIoPortAddress = 2; /* 0 = primary (330h), 1 = secondary (334h), 2 = disable, 3 = reserved */
}
static void
BuslogicInitializeAutoSCSIRam(x54x_t *dev)
{
@@ -421,15 +413,14 @@ BuslogicInitializeAutoSCSIRam(x54x_t *dev)
FILE *f;
f = nvr_fopen(BuslogicGetNVRFileName(bl), "rb");
if (f)
{
if (f) {
if (fread(&(bl->LocalRAM.structured.autoSCSIData), 1, 64, f) != 64)
fatal("BuslogicInitializeAutoSCSIRam(): Error reading data\n");
fclose(f);
f = NULL;
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
x54x_io_remove(dev, dev->Base, 4);
switch(HALR->structured.autoSCSIData.uHostAdapterIoPortAddress) {
switch (HALR->structured.autoSCSIData.uHostAdapterIoPortAddress) {
case 0:
dev->Base = 0x330;
break;
@@ -442,18 +433,15 @@ BuslogicInitializeAutoSCSIRam(x54x_t *dev)
}
x54x_io_set(dev, dev->Base, 4);
}
}
else
{
} else {
BuslogicAutoSCSIRamSetDefaults(dev, 0);
}
}
static void
buslogic_cmd_phase1(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
if ((dev->CmdParam == 2) && (dev->Command == 0x90)) {
dev->CmdParamLeft = dev->CmdBuf[1];
@@ -474,50 +462,40 @@ buslogic_cmd_phase1(void *p)
}
}
static uint8_t
buslogic_get_host_id(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
HALocalRAM *HALR = &bl->LocalRAM;
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16))
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) || (bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16))
return dev->HostID;
else
return HALR->structured.autoSCSIData.uSCSIId;
}
static uint8_t
buslogic_get_irq(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
uint8_t bl_irq[7] = { 0, 9, 10, 11, 12, 14, 15 };
HALocalRAM *HALR = &bl->LocalRAM;
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16) ||
(bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30))
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) || (bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16) || (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30))
return dev->Irq;
else
return bl_irq[HALR->structured.autoSCSIData.uIrqChannel];
}
static uint8_t
buslogic_get_dma(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
uint8_t bl_dma[4] = { 0, 5, 6, 7 };
@@ -526,20 +504,16 @@ buslogic_get_dma(void *p)
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30)
return (dev->Base ? 7 : 0);
else if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16))
else if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) || (bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16))
return dev->DmaChannel;
else
return bl_dma[HALR->structured.autoSCSIData.uDMAChannel];
}
static uint8_t
buslogic_param_len(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
switch (dev->Command) {
@@ -578,7 +552,6 @@ buslogic_param_len(void *p)
}
}
static void
BuslogicSCSIBIOSDMATransfer(x54x_t *dev, ESCMD *ESCSICmd, uint8_t TargetID, int dir, int transfer_size)
{
@@ -604,19 +577,18 @@ BuslogicSCSIBIOSDMATransfer(x54x_t *dev, ESCMD *ESCSICmd, uint8_t TargetID, int
if (dir && ((ESCSICmd->DataDirection == CCB_DATA_XFER_OUT) || (ESCSICmd->DataDirection == 0x00))) {
buslogic_log("BusLogic BIOS DMA: Reading %i bytes from %08X\n", TransferLength, Address);
dma_bm_read(Address, (uint8_t *)sd->sc->temp_buffer, TransferLength, transfer_size);
dma_bm_read(Address, (uint8_t *) sd->sc->temp_buffer, TransferLength, transfer_size);
} else if (!dir && ((ESCSICmd->DataDirection == CCB_DATA_XFER_IN) || (ESCSICmd->DataDirection == 0x00))) {
buslogic_log("BusLogic BIOS DMA: Writing %i bytes at %08X\n", TransferLength, Address);
dma_bm_write(Address, (uint8_t *)sd->sc->temp_buffer, TransferLength, transfer_size);
dma_bm_write(Address, (uint8_t *) sd->sc->temp_buffer, TransferLength, transfer_size);
}
}
}
static void
BuslogicSCSIBIOSRequestSetup(x54x_t *dev, uint8_t *CmdBuf, uint8_t *DataInBuf, uint8_t DataReply)
{
ESCMD *ESCSICmd = (ESCMD *)CmdBuf;
ESCMD *ESCSICmd = (ESCMD *) CmdBuf;
uint32_t i;
uint8_t temp_cdb[12];
int target_cdb_len = 12;
@@ -653,7 +625,8 @@ BuslogicSCSIBIOSRequestSetup(x54x_t *dev, uint8_t *CmdBuf, uint8_t *DataInBuf, u
target_cdb_len = 12;
if (!scsi_device_valid(sd)) fatal("SCSI target on ID %02i has disappeared\n", ESCSICmd->TargetId);
if (!scsi_device_valid(sd))
fatal("SCSI target on ID %02i has disappeared\n", ESCSICmd->TargetId);
buslogic_log("SCSI target command being executed on: SCSI ID %i, SCSI LUN %i, Target %i\n", ESCSICmd->TargetId, ESCSICmd->LogicalUnit, target_id);
@@ -693,11 +666,10 @@ BuslogicSCSIBIOSRequestSetup(x54x_t *dev, uint8_t *CmdBuf, uint8_t *DataInBuf, u
dev->DataReplyLeft = DataReply;
}
static uint8_t
buslogic_cmds(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
HALocalRAM *HALR = &bl->LocalRAM;
@@ -750,7 +722,7 @@ buslogic_cmds(void *p)
case 0x81:
dev->flags &= ~X54X_MBX_24BIT;
MailboxInitE = (MailboxInitExtended_t *)dev->CmdBuf;
MailboxInitE = (MailboxInitExtended_t *) dev->CmdBuf;
dev->MailboxInit = 1;
dev->MailboxCount = MailboxInitE->Count;
@@ -790,7 +762,7 @@ buslogic_cmds(void *p)
ReplyPI = (BuslogicPCIInformation_t *) dev->DataBuf;
memset(ReplyPI, 0, sizeof(BuslogicPCIInformation_t));
ReplyPI->InformationIsValid = 0;
switch(dev->Base) {
switch (dev->Base) {
case 0x330:
ReplyPI->IsaIOPort = 0;
break;
@@ -838,7 +810,7 @@ buslogic_cmds(void *p)
break;
case 0x8D:
dev->DataReplyLeft = dev->CmdBuf[0];
ReplyIESI = (ReplyInquireExtendedSetupInformation *)dev->DataBuf;
ReplyIESI = (ReplyInquireExtendedSetupInformation *) dev->DataBuf;
memset(ReplyIESI, 0, sizeof(ReplyInquireExtendedSetupInformation));
switch (bl->chip) {
@@ -862,9 +834,7 @@ buslogic_cmds(void *p)
ReplyIESI->cMailbox = dev->MailboxCount;
ReplyIESI->uMailboxAddressBase = dev->MailboxOutAddr;
ReplyIESI->fHostWideSCSI = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 1 : 0;
if ((bl->chip != CHIP_BUSLOGIC_ISA_542B_1991_12_14) && (bl->chip != CHIP_BUSLOGIC_ISA_545S_1992_10_05) &&
(bl->chip != CHIP_BUSLOGIC_ISA_542BH_1993_05_23) && (bl->chip != CHIP_BUSLOGIC_MCA_640A_1993_05_23) &&
(bl->chip != CHIP_BUSLOGIC_VLB_445S_1993_11_16))
if ((bl->chip != CHIP_BUSLOGIC_ISA_542B_1991_12_14) && (bl->chip != CHIP_BUSLOGIC_ISA_545S_1992_10_05) && (bl->chip != CHIP_BUSLOGIC_ISA_542BH_1993_05_23) && (bl->chip != CHIP_BUSLOGIC_MCA_640A_1993_05_23) && (bl->chip != CHIP_BUSLOGIC_VLB_445S_1993_11_16))
ReplyIESI->fLevelSensitiveInterrupt = bl->LocalRAM.structured.autoSCSIData.fLevelSensitiveInterrupt;
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30)
ReplyIESI->fHostUltraSCSI = 1;
@@ -899,10 +869,7 @@ buslogic_cmds(void *p)
break;
}
case 0x92:
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) ||
(bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23)) {
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) || (bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23)) {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
break;
@@ -933,7 +900,7 @@ buslogic_cmds(void *p)
if ((bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) && !(dev->Status & STAT_INVCMD)) {
x54x_io_remove(dev, dev->Base, 4);
switch(HALR->structured.autoSCSIData.uHostAdapterIoPortAddress) {
switch (HALR->structured.autoSCSIData.uHostAdapterIoPortAddress) {
case 0:
dev->Base = 0x330;
break;
@@ -948,8 +915,7 @@ buslogic_cmds(void *p)
}
break;
case 0x94:
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23)) {
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23) || (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23)) {
dev->DataReplyLeft = 0;
dev->Status |= STAT_INVCMD;
break;
@@ -1046,18 +1012,17 @@ buslogic_cmds(void *p)
return 0;
}
static void
buslogic_setup_data(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
ReplyInquireSetupInformation *ReplyISI;
buslogic_setup_t *bl_setup;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
HALocalRAM *HALR = &bl->LocalRAM;
ReplyISI = (ReplyInquireSetupInformation *)dev->DataBuf;
bl_setup = (buslogic_setup_t *)ReplyISI->VendorSpecificData;
ReplyISI = (ReplyInquireSetupInformation *) dev->DataBuf;
bl_setup = (buslogic_setup_t *) ReplyISI->VendorSpecificData;
ReplyISI->fSynchronousInitiationEnabled = HALR->structured.autoSCSIData.u16SynchronousPermittedMask ? 1 : 0;
ReplyISI->fParityCheckingEnabled = (HALR->structured.autoSCSIData.uSCSIConfiguration & 2) ? 1 : 0;
@@ -1067,8 +1032,7 @@ buslogic_setup_data(void *p)
* friendly with Adaptec hardware and upsetting the HBA state.
*/
bl_setup->uCharacterD = 'D'; /* BusLogic model. */
switch(bl->chip)
{
switch (bl->chip) {
case CHIP_BUSLOGIC_ISA_542B_1991_12_14:
case CHIP_BUSLOGIC_ISA_545S_1992_10_05:
case CHIP_BUSLOGIC_ISA_542BH_1993_05_23:
@@ -1088,11 +1052,10 @@ buslogic_setup_data(void *p)
}
}
static uint8_t
buslogic_is_aggressive_mode(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
buslogic_log("Buslogic: Aggressive mode = %d\n", bl->fAggressiveRoundRobinMode);
@@ -1100,35 +1063,30 @@ buslogic_is_aggressive_mode(void *p)
return bl->fAggressiveRoundRobinMode;
}
static uint8_t
buslogic_interrupt_type(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) ||
(bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16) || (bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23))
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) || (bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16) || (bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23))
return 0;
else
return !!bl->LocalRAM.structured.autoSCSIData.fLevelSensitiveInterrupt;
}
static void
buslogic_reset(void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
bl->ExtendedLUNCCBFormat = 0;
}
uint8_t buslogic_pci_regs[256];
bar_t buslogic_pci_bar[3];
static void
BuslogicBIOSUpdate(buslogic_data_t *bl)
{
@@ -1153,7 +1111,7 @@ BuslogicBIOSUpdate(buslogic_data_t *bl)
static uint8_t
BuslogicPCIRead(int func, int addr, void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
#ifdef ENABLE_BUSLOGIC_LOG
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
#endif
@@ -1231,14 +1189,13 @@ BuslogicPCIRead(int func, int addr, void *p)
return PCI_INTA;
}
return(0);
return (0);
}
static void
BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
{
x54x_t *dev = (x54x_t *)p;
x54x_t *dev = (x54x_t *) p;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
uint8_t valxor;
@@ -1268,7 +1225,9 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
val |= 1;
/*FALLTHROUGH*/
case 0x11: case 0x12: case 0x13:
case 0x11:
case 0x12:
case 0x13:
/* I/O Base set. */
/* First, remove the old I/O. */
x54x_io_remove(dev, bl->PCIBase, 32);
@@ -1277,7 +1236,7 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
/* Then let's calculate the new I/O base. */
bl->PCIBase = buslogic_pci_bar[0].addr & 0xffe0;
/* Log the new base. */
buslogic_log("BusLogic PCI: New I/O base is %04X\n" , bl->PCIBase);
buslogic_log("BusLogic PCI: New I/O base is %04X\n", bl->PCIBase);
/* We're done, so get out of the here. */
if (buslogic_pci_regs[4] & PCI_COMMAND_IO) {
if (bl->PCIBase != 0) {
@@ -1290,7 +1249,9 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
val &= 0xe0;
/*FALLTHROUGH*/
case 0x15: case 0x16: case 0x17:
case 0x15:
case 0x16:
case 0x17:
/* MMIO Base set. */
/* First, remove the old I/O. */
x54x_mem_disable(dev);
@@ -1302,7 +1263,7 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
buslogic_pci_bar[1].addr &= 0xffffc000;
bl->MMIOBase = buslogic_pci_bar[1].addr & 0xffffc000;
/* Log the new base. */
buslogic_log("BusLogic PCI: New MMIO base is %04X\n" , bl->MMIOBase);
buslogic_log("BusLogic PCI: New MMIO base is %04X\n", bl->MMIOBase);
/* We're done, so get out of the here. */
if (buslogic_pci_regs[4] & PCI_COMMAND_MEM) {
if (bl->MMIOBase != 0) {
@@ -1333,7 +1294,6 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
}
}
static void
BuslogicInitializeLocalRAM(buslogic_data_t *bl)
{
@@ -1353,16 +1313,14 @@ BuslogicInitializeLocalRAM(buslogic_data_t *bl)
bl->LocalRAM.structured.autoSCSIData.u16UltraPermittedMask = ~0;
}
static uint8_t
buslogic_mca_read(int port, void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
return(dev->pos_regs[port & 7]);
return (dev->pos_regs[port & 7]);
}
static void
buslogic_mca_write(int port, uint8_t val, void *priv)
{
@@ -1372,7 +1330,8 @@ buslogic_mca_write(int port, uint8_t val, void *priv)
HALocalRAM *HALR = &bl->LocalRAM;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102) return;
if (port < 0x0102)
return;
/* Save the MCA register value. */
dev->pos_regs[port & 7] = val;
@@ -1393,7 +1352,8 @@ buslogic_mca_write(int port, uint8_t val, void *priv)
dev->DmaChannel = dev->pos_regs[5] & 0x0f;
/* Extract the BIOS ROM address info. */
if (dev->pos_regs[2] & 0xe0) switch(dev->pos_regs[2] & 0xe0) {
if (dev->pos_regs[2] & 0xe0)
switch (dev->pos_regs[2] & 0xe0) {
case 0xe0: /* [0]=111x xxxx */
bl->bios_addr = 0xDC000;
break;
@@ -1425,7 +1385,8 @@ buslogic_mca_write(int port, uint8_t val, void *priv)
case 0x20: /* [0]=001x xxxx */
bl->bios_addr = 0xC4000;
break;
} else {
}
else {
/* Disabled. */
bl->bios_addr = 0x000000;
}
@@ -1458,7 +1419,7 @@ buslogic_mca_write(int port, uint8_t val, void *priv)
HALR->structured.autoSCSIData.uBIOSConfiguration &= ~4;
HALR->structured.autoSCSIData.uBIOSConfiguration |= (dev->pos_regs[4] & 8) ? 4 : 0;
switch(dev->DmaChannel) {
switch (dev->DmaChannel) {
case 5:
HALR->structured.autoSCSIData.uDMAChannel = 1;
break;
@@ -1473,7 +1434,7 @@ buslogic_mca_write(int port, uint8_t val, void *priv)
break;
}
switch(dev->Irq) {
switch (dev->Irq) {
case 9:
HALR->structured.autoSCSIData.uIrqChannel = 1;
break;
@@ -1526,16 +1487,14 @@ buslogic_mca_write(int port, uint8_t val, void *priv)
}
}
static uint8_t
buslogic_mca_feedb(void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
return (dev->pos_regs[2] & 0x01);
}
void
BuslogicDeviceReset(void *p)
{
@@ -1548,7 +1507,6 @@ BuslogicDeviceReset(void *p)
BuslogicInitializeAutoSCSIRam(dev);
}
static void *
buslogic_init(const device_t *info)
{
@@ -1580,8 +1538,7 @@ buslogic_init(const device_t *info)
dev->Base = device_get_config_hex16("base");
dev->Irq = device_get_config_int("irq");
dev->DmaChannel = device_get_config_int("dma");
}
else if (info->flags & DEVICE_PCI) {
} else if (info->flags & DEVICE_PCI) {
dev->Base = 0;
}
dev->HostID = 7; /* default HA ID */
@@ -1736,8 +1693,7 @@ buslogic_init(const device_t *info)
memset(bl->SCAMData, 0x00, 65536);
if (bl->has_bios)
{
if (bl->has_bios) {
bl->bios_size = bios_rom_size;
bl->bios_mask = 0xffffc000;
@@ -1761,8 +1717,7 @@ buslogic_init(const device_t *info)
f = NULL;
}
}
}
else {
} else {
bl->bios_size = 0;
bl->bios_mask = 0;
@@ -1793,13 +1748,12 @@ buslogic_init(const device_t *info)
x54x_device_reset(dev);
if ((bl->chip != CHIP_BUSLOGIC_ISA_542B_1991_12_14) && (bl->chip != CHIP_BUSLOGIC_ISA_545S_1992_10_05) && (bl->chip != CHIP_BUSLOGIC_ISA_542BH_1993_05_23) &&
(bl->chip != CHIP_BUSLOGIC_VLB_445S_1993_11_16) && (bl->chip != CHIP_BUSLOGIC_MCA_640A_1993_05_23)) {
if ((bl->chip != CHIP_BUSLOGIC_ISA_542B_1991_12_14) && (bl->chip != CHIP_BUSLOGIC_ISA_545S_1992_10_05) && (bl->chip != CHIP_BUSLOGIC_ISA_542BH_1993_05_23) && (bl->chip != CHIP_BUSLOGIC_VLB_445S_1993_11_16) && (bl->chip != CHIP_BUSLOGIC_MCA_640A_1993_05_23)) {
BuslogicInitializeLocalRAM(bl);
BuslogicInitializeAutoSCSIRam(dev);
}
return(dev);
return (dev);
}
// clang-format off

171
src/scsi/scsi_cdrom.c
View File

@@ -39,8 +39,7 @@
#include <86box/scsi_cdrom.h>
#include <86box/version.h>
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct
{
uint8_t opcode;
@@ -60,10 +59,8 @@ typedef struct
} gesn_event_header_t;
#pragma pack(pop)
/* Table of all SCSI commands and their flags, needed for the new disc change / not ready handler. */
const uint8_t scsi_cdrom_command_flags[0x100] =
{
const uint8_t scsi_cdrom_command_flags[0x100] = {
IMPLEMENTED | CHECK_READY | NONDATA, /* 0x00 */
IMPLEMENTED | ALLOW_UA | NONDATA | SCSI_ONLY, /* 0x01 */
0, /* 0x02 */
@@ -157,17 +154,10 @@ const uint8_t scsi_cdrom_command_flags[0x100] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 /* 0xF0-0xFF */
};
static uint64_t scsi_cdrom_mode_sense_page_flags = (GPMODEP_R_W_ERROR_PAGE |
GPMODEP_DISCONNECT_PAGE |
GPMODEP_CDROM_PAGE |
GPMODEP_CDROM_AUDIO_PAGE |
(1ULL << 0x0fULL) |
GPMODEP_CAPABILITIES_PAGE |
GPMODEP_ALL_PAGES);
static uint64_t scsi_cdrom_mode_sense_page_flags = (GPMODEP_R_W_ERROR_PAGE | GPMODEP_DISCONNECT_PAGE | GPMODEP_CDROM_PAGE | GPMODEP_CDROM_AUDIO_PAGE | (1ULL << 0x0fULL) | GPMODEP_CAPABILITIES_PAGE | GPMODEP_ALL_PAGES);
static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_default =
{ {
{ 0, 0 },
static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_default = {
{{ 0, 0 },
{ GPMODE_R_W_ERROR_PAGE, 6, 0, 5, 0, 0, 0, 0 },
{ 0, 0 },
{ 0, 0 },
@@ -209,12 +199,11 @@ static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_default =
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_CAPABILITIES_PAGE, 0x12, 0, 0, 1, 0, 0, 0, 2, 0xC2, 1, 0, 0, 0, 2, 0xC2, 0, 0, 0, 0 }
} };
{ GPMODE_CAPABILITIES_PAGE, 0x12, 0, 0, 1, 0, 0, 0, 2, 0xC2, 1, 0, 0, 0, 2, 0xC2, 0, 0, 0, 0 }}
};
static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_default_scsi =
{ {
{ 0, 0 },
static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_default_scsi = {
{{ 0, 0 },
{ GPMODE_R_W_ERROR_PAGE, 6, 0, 5, 0, 0, 0, 0 },
{ GPMODE_DISCONNECT_PAGE, 0x0e, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0 },
@@ -228,7 +217,7 @@ static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_default_scsi =
{ 0, 0 },
{ 0, 0 },
{ GPMODE_CDROM_PAGE, 6, 0, 1, 0, 60, 0, 75 },
{ 0x8E, 0xE, 5, 4, 0,128, 0, 75, 1, 255, 2, 255, 0, 0, 0, 0 },
{ 0x8E, 0xE, 5, 4, 0, 128, 0, 75, 1, 255, 2, 255, 0, 0, 0, 0 },
{ 0x0F, 0x14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0 },
{ 0, 0 },
@@ -256,12 +245,11 @@ static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_default_scsi =
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_CAPABILITIES_PAGE, 0x12, 0, 0, 1, 0, 0, 0, 2, 0xC2, 1, 0, 0, 0, 2, 0xC2, 0, 0, 0, 0 }
} };
{ GPMODE_CAPABILITIES_PAGE, 0x12, 0, 0, 1, 0, 0, 0, 2, 0xC2, 1, 0, 0, 0, 2, 0xC2, 0, 0, 0, 0 }}
};
static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_changeable =
{ {
{ 0, 0 },
static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_changeable = {
{{ 0, 0 },
{ GPMODE_R_W_ERROR_PAGE, 6, 0xFF, 0xFF, 0, 0, 0, 0 },
{ GPMODE_DISCONNECT_PAGE, 0x0E, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0xFF, 0xFF, 0, 0, 0, 0 },
{ 0, 0 },
@@ -303,24 +291,21 @@ static const mode_sense_pages_t scsi_cdrom_mode_sense_pages_changeable =
{ 0, 0 },
{ 0, 0 },
{ 0, 0 },
{ GPMODE_CAPABILITIES_PAGE, 0x12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
} };
{ GPMODE_CAPABILITIES_PAGE, 0x12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
};
static gesn_cdb_t *gesn_cdb;
static gesn_event_header_t *gesn_event_header;
static void scsi_cdrom_command_complete(scsi_cdrom_t *dev);
static void scsi_cdrom_mode_sense_load(scsi_cdrom_t *dev);
static void scsi_cdrom_init(scsi_cdrom_t *dev);
#ifdef ENABLE_SCSI_CDROM_LOG
int scsi_cdrom_do_log = ENABLE_SCSI_CDROM_LOG;
static void
scsi_cdrom_log(const char *format, ...)
{
@@ -333,10 +318,9 @@ scsi_cdrom_log(const char *format, ...)
}
}
#else
#define scsi_cdrom_log(format, ...)
# define scsi_cdrom_log(format, ...)
#endif
static void
scsi_cdrom_set_callback(scsi_cdrom_t *dev)
{
@@ -344,7 +328,6 @@ scsi_cdrom_set_callback(scsi_cdrom_t *dev)
ide_set_callback(ide_drives[dev->drv->ide_channel], dev->callback);
}
static void
scsi_cdrom_init(scsi_cdrom_t *dev)
{
@@ -374,7 +357,6 @@ scsi_cdrom_init(scsi_cdrom_t *dev)
scsi_cdrom_mode_sense_load(dev);
}
/* Returns: 0 for none, 1 for PIO, 2 for DMA. */
static int
scsi_cdrom_current_mode(scsi_cdrom_t *dev)
@@ -391,7 +373,6 @@ scsi_cdrom_current_mode(scsi_cdrom_t *dev)
return 0;
}
/* Translates ATAPI phase (DRQ, I/O, C/D) to SCSI phase (MSG, C/D, I/O). */
int
scsi_cdrom_atapi_phase_to_scsi(scsi_cdrom_t *dev)
@@ -417,7 +398,6 @@ scsi_cdrom_atapi_phase_to_scsi(scsi_cdrom_t *dev)
return 0;
}
static uint32_t
scsi_cdrom_get_channel(void *p, int channel)
{
@@ -428,7 +408,6 @@ scsi_cdrom_get_channel(void *p, int channel)
return dev->ms_pages_saved.pages[GPMODE_CDROM_AUDIO_PAGE][channel ? 10 : 8];
}
static uint32_t
scsi_cdrom_get_volume(void *p, int channel)
{
@@ -439,7 +418,6 @@ scsi_cdrom_get_volume(void *p, int channel)
return dev->ms_pages_saved.pages[GPMODE_CDROM_AUDIO_PAGE][channel ? 11 : 9];
}
static void
scsi_cdrom_mode_sense_load(scsi_cdrom_t *dev)
{
@@ -465,7 +443,6 @@ scsi_cdrom_mode_sense_load(scsi_cdrom_t *dev)
}
}
static void
scsi_cdrom_mode_sense_save(scsi_cdrom_t *dev)
{
@@ -484,7 +461,6 @@ scsi_cdrom_mode_sense_save(scsi_cdrom_t *dev)
}
}
/*SCSI Mode Sense 6/10*/
static uint8_t
scsi_cdrom_mode_sense_read(scsi_cdrom_t *dev, uint8_t page_control, uint8_t page, uint8_t pos)
@@ -508,7 +484,6 @@ scsi_cdrom_mode_sense_read(scsi_cdrom_t *dev, uint8_t page_control, uint8_t page
return 0;
}
static uint32_t
scsi_cdrom_mode_sense(scsi_cdrom_t *dev, uint8_t *buf, uint32_t pos, uint8_t page, uint8_t block_descriptor_len)
{
@@ -558,7 +533,6 @@ scsi_cdrom_mode_sense(scsi_cdrom_t *dev, uint8_t *buf, uint32_t pos, uint8_t pag
return pos;
}
static void
scsi_cdrom_update_request_length(scsi_cdrom_t *dev, int len, int block_len)
{
@@ -614,7 +588,6 @@ scsi_cdrom_update_request_length(scsi_cdrom_t *dev, int len, int block_len)
return;
}
static double
scsi_cdrom_bus_speed(scsi_cdrom_t *dev)
{
@@ -635,7 +608,6 @@ scsi_cdrom_bus_speed(scsi_cdrom_t *dev)
}
}
static void
scsi_cdrom_command_common(scsi_cdrom_t *dev)
{
@@ -651,7 +623,7 @@ scsi_cdrom_command_common(scsi_cdrom_t *dev)
if (dev->packet_status == PHASE_COMPLETE)
dev->callback = 0;
else {
switch(dev->current_cdb[0]) {
switch (dev->current_cdb[0]) {
case GPCMD_REZERO_UNIT:
case 0x0b:
case 0x2b:
@@ -707,7 +679,6 @@ scsi_cdrom_command_common(scsi_cdrom_t *dev)
scsi_cdrom_set_callback(dev);
}
static void
scsi_cdrom_command_complete(scsi_cdrom_t *dev)
{
@@ -716,7 +687,6 @@ scsi_cdrom_command_complete(scsi_cdrom_t *dev)
scsi_cdrom_command_common(dev);
}
static void
scsi_cdrom_command_read(scsi_cdrom_t *dev)
{
@@ -724,7 +694,6 @@ scsi_cdrom_command_read(scsi_cdrom_t *dev)
scsi_cdrom_command_common(dev);
}
static void
scsi_cdrom_command_read_dma(scsi_cdrom_t *dev)
{
@@ -732,7 +701,6 @@ scsi_cdrom_command_read_dma(scsi_cdrom_t *dev)
scsi_cdrom_command_common(dev);
}
static void
scsi_cdrom_command_write(scsi_cdrom_t *dev)
{
@@ -740,20 +708,20 @@ scsi_cdrom_command_write(scsi_cdrom_t *dev)
scsi_cdrom_command_common(dev);
}
static void scsi_cdrom_command_write_dma(scsi_cdrom_t *dev)
static void
scsi_cdrom_command_write_dma(scsi_cdrom_t *dev)
{
dev->packet_status = PHASE_DATA_OUT_DMA;
scsi_cdrom_command_common(dev);
}
/* id = Current CD-ROM device ID;
len = Total transfer length;
block_len = Length of a single block (it matters because media access commands on ATAPI);
alloc_len = Allocated transfer length;
direction = Transfer direction (0 = read from host, 1 = write to host). */
static void scsi_cdrom_data_command_finish(scsi_cdrom_t *dev, int len, int block_len, int alloc_len, int direction)
static void
scsi_cdrom_data_command_finish(scsi_cdrom_t *dev, int len, int block_len, int alloc_len, int direction)
{
scsi_cdrom_log("CD-ROM %i: Finishing command (%02X): %i, %i, %i, %i, %i\n",
dev->id, dev->current_cdb[0], len, block_len, alloc_len, direction, dev->request_length);
@@ -789,14 +757,12 @@ static void scsi_cdrom_data_command_finish(scsi_cdrom_t *dev, int len, int block
dev->id, dev->packet_status, dev->request_length, dev->packet_len, dev->pos, dev->phase);
}
static void
scsi_cdrom_sense_clear(scsi_cdrom_t *dev, int command)
{
scsi_cdrom_sense_key = scsi_cdrom_asc = scsi_cdrom_ascq = 0;
}
static void
scsi_cdrom_set_phase(scsi_cdrom_t *dev, uint8_t phase)
{
@@ -809,7 +775,6 @@ scsi_cdrom_set_phase(scsi_cdrom_t *dev, uint8_t phase)
scsi_devices[scsi_bus][scsi_id].phase = phase;
}
static void
scsi_cdrom_cmd_error(scsi_cdrom_t *dev)
{
@@ -827,7 +792,6 @@ scsi_cdrom_cmd_error(scsi_cdrom_t *dev)
scsi_cdrom_log("CD-ROM %i: ERROR: %02X/%02X/%02X\n", dev->id, scsi_cdrom_sense_key, scsi_cdrom_asc, scsi_cdrom_ascq);
}
static void
scsi_cdrom_unit_attention(scsi_cdrom_t *dev)
{
@@ -845,7 +809,6 @@ scsi_cdrom_unit_attention(scsi_cdrom_t *dev)
scsi_cdrom_log("CD-ROM %i: UNIT ATTENTION\n", dev->id);
}
static void
scsi_cdrom_buf_alloc(scsi_cdrom_t *dev, uint32_t len)
{
@@ -854,7 +817,6 @@ scsi_cdrom_buf_alloc(scsi_cdrom_t *dev, uint32_t len)
dev->buffer = (uint8_t *) malloc(len);
}
static void
scsi_cdrom_buf_free(scsi_cdrom_t *dev)
{
@@ -865,7 +827,6 @@ scsi_cdrom_buf_free(scsi_cdrom_t *dev)
}
}
static void
scsi_cdrom_bus_master_error(scsi_common_t *sc)
{
@@ -876,7 +837,6 @@ scsi_cdrom_bus_master_error(scsi_common_t *sc)
scsi_cdrom_cmd_error(dev);
}
static void
scsi_cdrom_not_ready(scsi_cdrom_t *dev)
{
@@ -886,7 +846,6 @@ scsi_cdrom_not_ready(scsi_cdrom_t *dev)
scsi_cdrom_cmd_error(dev);
}
static void
scsi_cdrom_invalid_lun(scsi_cdrom_t *dev)
{
@@ -896,7 +855,6 @@ scsi_cdrom_invalid_lun(scsi_cdrom_t *dev)
scsi_cdrom_cmd_error(dev);
}
static void
scsi_cdrom_illegal_opcode(scsi_cdrom_t *dev)
{
@@ -906,7 +864,6 @@ scsi_cdrom_illegal_opcode(scsi_cdrom_t *dev)
scsi_cdrom_cmd_error(dev);
}
static void
scsi_cdrom_lba_out_of_range(scsi_cdrom_t *dev)
{
@@ -916,7 +873,6 @@ scsi_cdrom_lba_out_of_range(scsi_cdrom_t *dev)
scsi_cdrom_cmd_error(dev);
}
static void
scsi_cdrom_invalid_field(scsi_cdrom_t *dev)
{
@@ -927,7 +883,6 @@ scsi_cdrom_invalid_field(scsi_cdrom_t *dev)
dev->status = 0x53;
}
static void
scsi_cdrom_invalid_field_pl(scsi_cdrom_t *dev)
{
@@ -938,7 +893,6 @@ scsi_cdrom_invalid_field_pl(scsi_cdrom_t *dev)
dev->status = 0x53;
}
static void
scsi_cdrom_illegal_mode(scsi_cdrom_t *dev)
{
@@ -948,7 +902,6 @@ scsi_cdrom_illegal_mode(scsi_cdrom_t *dev)
scsi_cdrom_cmd_error(dev);
}
static void
scsi_cdrom_incompatible_format(scsi_cdrom_t *dev)
{
@@ -958,7 +911,6 @@ scsi_cdrom_incompatible_format(scsi_cdrom_t *dev)
scsi_cdrom_cmd_error(dev);
}
static void
scsi_cdrom_data_phase_error(scsi_cdrom_t *dev)
{
@@ -968,7 +920,6 @@ scsi_cdrom_data_phase_error(scsi_cdrom_t *dev)
scsi_cdrom_cmd_error(dev);
}
static int
scsi_cdrom_read_data(scsi_cdrom_t *dev, int msf, int type, int flags, int32_t *len)
{
@@ -1023,7 +974,6 @@ scsi_cdrom_read_data(scsi_cdrom_t *dev, int msf, int type, int flags, int32_t *l
return 1;
}
static int
scsi_cdrom_read_blocks(scsi_cdrom_t *dev, int32_t *len, int first_batch)
{
@@ -1067,7 +1017,6 @@ scsi_cdrom_read_blocks(scsi_cdrom_t *dev, int32_t *len, int first_batch)
return 1;
}
/*SCSI Read DVD Structure*/
static int
scsi_cdrom_read_dvd_structure(scsi_cdrom_t *dev, int format, const uint8_t *packet, uint8_t *buf)
@@ -1184,7 +1133,6 @@ scsi_cdrom_read_dvd_structure(scsi_cdrom_t *dev, int format, const uint8_t *pack
}
}
static void
scsi_cdrom_insert(void *p)
{
@@ -1199,7 +1147,6 @@ scsi_cdrom_insert(void *p)
scsi_cdrom_log("CD-ROM %i: Media insert\n", dev->id);
}
static int
scsi_cdrom_pre_execution_check(scsi_cdrom_t *dev, uint8_t *cdb)
{
@@ -1292,7 +1239,6 @@ skip_ready_check:
return 1;
}
static void
scsi_cdrom_rezero(scsi_cdrom_t *dev)
{
@@ -1300,7 +1246,6 @@ scsi_cdrom_rezero(scsi_cdrom_t *dev)
cdrom_seek(dev->drv, 0);
}
void
scsi_cdrom_reset(scsi_common_t *sc)
{
@@ -1320,7 +1265,6 @@ scsi_cdrom_reset(scsi_common_t *sc)
dev->cur_lun = SCSI_LUN_USE_CDB;
}
static void
scsi_cdrom_request_sense(scsi_cdrom_t *dev, uint8_t *buffer, uint8_t alloc_length)
{
@@ -1333,18 +1277,17 @@ scsi_cdrom_request_sense(scsi_cdrom_t *dev, uint8_t *buffer, uint8_t alloc_lengt
buffer[0] = 0x70;
if ((scsi_cdrom_sense_key > 0) && (dev->drv->cd_status == CD_STATUS_PLAYING_COMPLETED)) {
buffer[2]=SENSE_ILLEGAL_REQUEST;
buffer[12]=ASC_AUDIO_PLAY_OPERATION;
buffer[13]=ASCQ_AUDIO_PLAY_OPERATION_COMPLETED;
} else if ((scsi_cdrom_sense_key == 0) && ((dev->drv->cd_status == CD_STATUS_PAUSED) ||
((dev->drv->cd_status >= CD_STATUS_PLAYING) && (dev->drv->cd_status != CD_STATUS_STOPPED)))) {
buffer[2]=SENSE_ILLEGAL_REQUEST;
buffer[12]=ASC_AUDIO_PLAY_OPERATION;
buffer[13]=(dev->drv->cd_status == CD_STATUS_PLAYING) ? ASCQ_AUDIO_PLAY_OPERATION_IN_PROGRESS : ASCQ_AUDIO_PLAY_OPERATION_PAUSED;
buffer[2] = SENSE_ILLEGAL_REQUEST;
buffer[12] = ASC_AUDIO_PLAY_OPERATION;
buffer[13] = ASCQ_AUDIO_PLAY_OPERATION_COMPLETED;
} else if ((scsi_cdrom_sense_key == 0) && ((dev->drv->cd_status == CD_STATUS_PAUSED) || ((dev->drv->cd_status >= CD_STATUS_PLAYING) && (dev->drv->cd_status != CD_STATUS_STOPPED)))) {
buffer[2] = SENSE_ILLEGAL_REQUEST;
buffer[12] = ASC_AUDIO_PLAY_OPERATION;
buffer[13] = (dev->drv->cd_status == CD_STATUS_PLAYING) ? ASCQ_AUDIO_PLAY_OPERATION_IN_PROGRESS : ASCQ_AUDIO_PLAY_OPERATION_PAUSED;
} else if (dev->unit_attention && (scsi_cdrom_sense_key == 0)) {
buffer[2]=SENSE_UNIT_ATTENTION;
buffer[12]=ASC_MEDIUM_MAY_HAVE_CHANGED;
buffer[13]=0;
buffer[2] = SENSE_UNIT_ATTENTION;
buffer[12] = ASC_MEDIUM_MAY_HAVE_CHANGED;
buffer[13] = 0;
}
scsi_cdrom_log("CD-ROM %i: Reporting sense: %02X %02X %02X\n", dev->id, buffer[2], buffer[12], buffer[13]);
@@ -1359,7 +1302,6 @@ scsi_cdrom_request_sense(scsi_cdrom_t *dev, uint8_t *buffer, uint8_t alloc_lengt
scsi_cdrom_sense_clear(dev, GPCMD_REQUEST_SENSE);
}
void
scsi_cdrom_request_sense_for_scsi(scsi_common_t *sc, uint8_t *buffer, uint8_t alloc_length)
{
@@ -1379,7 +1321,6 @@ scsi_cdrom_request_sense_for_scsi(scsi_common_t *sc, uint8_t *buffer, uint8_t al
scsi_cdrom_request_sense(dev, buffer, alloc_length);
}
static void
scsi_cdrom_set_buf_len(scsi_cdrom_t *dev, int32_t *BufLen, int32_t *src_len)
{
@@ -1394,7 +1335,6 @@ scsi_cdrom_set_buf_len(scsi_cdrom_t *dev, int32_t *BufLen, int32_t *src_len)
}
}
static void
scsi_cdrom_stop(scsi_common_t *sc)
{
@@ -1403,13 +1343,12 @@ scsi_cdrom_stop(scsi_common_t *sc)
cdrom_stop(dev->drv);
}
void
scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
{
scsi_cdrom_t *dev = (scsi_cdrom_t *) sc;
int len, max_len, used_len, alloc_length, msf;
int pos = 0, i= 0, size_idx, idx = 0;
int pos = 0, i = 0, size_idx, idx = 0;
uint32_t feature;
unsigned preamble_len;
int toc_format, block_desc = 0;
@@ -1595,7 +1534,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
scsi_cdrom_set_phase(dev, SCSI_PHASE_DATA_IN);
alloc_length = 2048;
switch(cdb[0]) {
switch (cdb[0]) {
case GPCMD_READ_6:
dev->sector_len = cdb[4];
if (dev->sector_len == 0)
@@ -1715,7 +1654,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
scsi_cdrom_buf_alloc(dev, 8);
dev->sector_len = 1;
dev->sector_pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4]<<8) | cdb[5];
dev->sector_pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
if (msf)
real_pos = cdrom_lba_to_msf_accurate(dev->sector_pos);
else
@@ -1995,7 +1934,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
dev->buffer[7] = 0x20; /* unrestricted use */
dev->buffer[8] = 0x00; /* CD-ROM */
len=34;
len = 34;
len = MIN(len, max_len);
scsi_cdrom_set_buf_len(dev, BufLen, &len);
@@ -2090,7 +2029,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
scsi_cdrom_set_phase(dev, SCSI_PHASE_STATUS);
switch(cdb[0]) {
switch (cdb[0]) {
case GPCMD_PLAY_AUDIO_10:
msf = 0;
pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
@@ -2164,7 +2103,8 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
if (!(cdb[2] & 0x40))
alloc_length = 4;
else switch(cdb[3]) {
else
switch (cdb[3]) {
case 0:
/* SCSI-2: Q-type subchannel, ATAPI: reserved */
alloc_length = (dev->drv->bus_type == CDROM_BUS_SCSI) ? 48 : 4;
@@ -2183,7 +2123,8 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
pos = 0;
dev->buffer[pos++] = 0;
dev->buffer[pos++] = 0; /*Audio status*/
dev->buffer[pos++] = 0; dev->buffer[pos++] = 0; /*Subchannel length*/
dev->buffer[pos++] = 0;
dev->buffer[pos++] = 0; /*Subchannel length*/
/* Mode 0 = Q subchannel mode, first 16 bytes are indentical to mode 1 (current position),
the rest are stuff like ISRC etc., which can be all zeroes. */
if (cdb[3] <= 3) {
@@ -2194,7 +2135,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
dev->buffer[2] = alloc_length - 4;
}
switch(dev->drv->cd_status) {
switch (dev->drv->cd_status) {
case CD_STATUS_PLAYING:
dev->buffer[1] = 0x11;
break;
@@ -2288,7 +2229,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
case GPCMD_START_STOP_UNIT:
scsi_cdrom_set_phase(dev, SCSI_PHASE_STATUS);
switch(cdb[4] & 3) {
switch (cdb[4] & 3) {
case 0: /* Stop the disc. */
scsi_cdrom_stop(sc);
break;
@@ -2389,8 +2330,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
if (dev->drv->bus_type == CDROM_BUS_SCSI) {
dev->buffer[2] = 0x02;
dev->buffer[3] = 0x02;
}
else {
} else {
dev->buffer[2] = 0x00;
dev->buffer[3] = 0x21;
}
@@ -2421,7 +2361,7 @@ scsi_cdrom_command(scsi_common_t *sc, uint8_t *cdb)
atapi_out:
dev->buffer[size_idx] = idx - preamble_len;
len=idx;
len = idx;
len = MIN(len, max_len);
scsi_cdrom_set_buf_len(dev, BufLen, &len);
@@ -2453,12 +2393,12 @@ atapi_out:
case GPCMD_SEEK_10:
scsi_cdrom_set_phase(dev, SCSI_PHASE_STATUS);
switch(cdb[0]) {
switch (cdb[0]) {
case GPCMD_SEEK_6:
pos = (cdb[2] << 8) | cdb[3];
break;
case GPCMD_SEEK_10:
pos = (cdb[2] << 24) | (cdb[3]<<16) | (cdb[4]<<8) | cdb[5];
pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
break;
}
dev->drv->seek_diff = ABS((int) (pos - dev->drv->seek_pos));
@@ -2508,7 +2448,6 @@ atapi_out:
scsi_cdrom_buf_free(dev);
}
static void
scsi_cdrom_command_stop(scsi_common_t *sc)
{
@@ -2518,7 +2457,6 @@ scsi_cdrom_command_stop(scsi_common_t *sc)
scsi_cdrom_buf_free(dev);
}
/* The command second phase function, needed for Mode Select. */
static uint8_t
scsi_cdrom_phase_data_out(scsi_common_t *sc)
@@ -2531,7 +2469,7 @@ scsi_cdrom_phase_data_out(scsi_common_t *sc)
uint8_t error = 0;
uint8_t page, page_len, hdr_len, val, old_val, ch;
switch(dev->current_cdb[0]) {
switch (dev->current_cdb[0]) {
case GPCMD_MODE_SELECT_6:
case GPCMD_MODE_SELECT_10:
if (dev->current_cdb[0] == GPCMD_MODE_SELECT_10) {
@@ -2559,7 +2497,7 @@ scsi_cdrom_phase_data_out(scsi_common_t *sc)
pos = hdr_len + block_desc_len;
while(1) {
while (1) {
if (pos >= param_list_len) {
scsi_cdrom_log("CD-ROM %i: Buffer has only block descriptor\n", dev->id);
break;
@@ -2615,7 +2553,6 @@ scsi_cdrom_phase_data_out(scsi_common_t *sc)
return 1;
}
static void
scsi_cdrom_close(void *p)
{
@@ -2625,13 +2562,12 @@ scsi_cdrom_close(void *p)
free(dev);
}
static int
scsi_cdrom_get_max(int ide_has_dma, int type)
{
int ret;
switch(type) {
switch (type) {
case TYPE_PIO:
ret = ide_has_dma ? 4 : 0;
break;
@@ -2652,13 +2588,12 @@ scsi_cdrom_get_max(int ide_has_dma, int type)
return ret;
}
static int
scsi_cdrom_get_timings(int ide_has_dma, int type)
{
int ret;
switch(type) {
switch (type) {
case TIMINGS_DMA:
ret = ide_has_dma ? 120 : 0;
break;
@@ -2676,7 +2611,6 @@ scsi_cdrom_get_timings(int ide_has_dma, int type)
return ret;
}
/**
* Fill in ide->buffer with the output of the "IDENTIFY PACKET DEVICE" command
*/
@@ -2693,7 +2627,7 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma)
scsi_cdrom_log("ATAPI Identify: %s\n", device_identify);
#endif
ide->buffer[0] = 0x8000 | (5<<8) | 0x80 | (2<<5); /* ATAPI device, CD-ROM drive, removable media, accelerated DRQ */
ide->buffer[0] = 0x8000 | (5 << 8) | 0x80 | (2 << 5); /* ATAPI device, CD-ROM drive, removable media, accelerated DRQ */
ide_padstr((char *) (ide->buffer + 10), "", 20); /* Serial Number */
#if 0
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION_EX, 8); /* Firmware */
@@ -2713,7 +2647,6 @@ scsi_cdrom_identify(ide_t *ide, int ide_has_dma)
}
}
void
scsi_cdrom_drive_reset(int c)
{

17
src/scsi/scsi_device.c
View File

@@ -26,11 +26,9 @@
#include <86box/scsi.h>
#include <86box/scsi_device.h>
scsi_device_t scsi_devices[SCSI_BUS_MAX][SCSI_ID_MAX];
uint8_t scsi_null_device_sense[18] = { 0x70,0,SENSE_ILLEGAL_REQUEST,0,0,0,0,0,0,0,0,0,ASC_INV_LUN,0,0,0,0,0 };
uint8_t scsi_null_device_sense[18] = { 0x70, 0, SENSE_ILLEGAL_REQUEST, 0, 0, 0, 0, 0, 0, 0, 0, 0, ASC_INV_LUN, 0, 0, 0, 0, 0 };
static uint8_t
scsi_device_target_command(scsi_device_t *dev, uint8_t *cdb)
@@ -46,7 +44,6 @@ scsi_device_target_command(scsi_device_t *dev, uint8_t *cdb)
return SCSI_STATUS_CHECK_CONDITION;
}
double
scsi_device_get_callback(scsi_device_t *dev)
{
@@ -56,7 +53,6 @@ scsi_device_get_callback(scsi_device_t *dev)
return -1.0;
}
uint8_t *
scsi_device_sense(scsi_device_t *dev)
{
@@ -66,7 +62,6 @@ scsi_device_sense(scsi_device_t *dev)
return scsi_null_device_sense;
}
void
scsi_device_request_sense(scsi_device_t *dev, uint8_t *buffer, uint8_t alloc_length)
{
@@ -76,7 +71,6 @@ scsi_device_request_sense(scsi_device_t *dev, uint8_t *buffer, uint8_t alloc_len
memcpy(buffer, scsi_null_device_sense, alloc_length);
}
void
scsi_device_reset(scsi_device_t *dev)
{
@@ -84,7 +78,6 @@ scsi_device_reset(scsi_device_t *dev)
dev->reset(dev->sc);
}
int
scsi_device_present(scsi_device_t *dev)
{
@@ -94,7 +87,6 @@ scsi_device_present(scsi_device_t *dev)
return 1;
}
int
scsi_device_valid(scsi_device_t *dev)
{
@@ -104,7 +96,6 @@ scsi_device_valid(scsi_device_t *dev)
return 0;
}
int
scsi_device_cdb_length(scsi_device_t *dev)
{
@@ -112,7 +103,6 @@ scsi_device_cdb_length(scsi_device_t *dev)
return 12;
}
void
scsi_device_command_phase0(scsi_device_t *dev, uint8_t *cdb)
{
@@ -127,7 +117,6 @@ scsi_device_command_phase0(scsi_device_t *dev, uint8_t *cdb)
dev->status = scsi_device_target_command(dev, cdb);
}
void
scsi_device_command_stop(scsi_device_t *dev)
{
@@ -137,7 +126,6 @@ scsi_device_command_stop(scsi_device_t *dev)
}
}
void
scsi_device_command_phase1(scsi_device_t *dev)
{
@@ -157,7 +145,6 @@ scsi_device_command_phase1(scsi_device_t *dev)
dev->status = SCSI_STATUS_OK;
}
/* When LUN is FF, there has been no IDENTIFY message, otherwise
there has been one. */
void
@@ -172,7 +159,6 @@ scsi_device_identify(scsi_device_t *dev, uint8_t lun)
a LUN not supported by the target. */
}
void
scsi_device_close_all(void)
{
@@ -188,7 +174,6 @@ scsi_device_close_all(void)
}
}
void
scsi_device_init(void)
{

106
src/scsi/scsi_disk.c
View File

@@ -33,13 +33,11 @@
#include <86box/scsi_disk.h>
#include <86box/version.h>
#define scsi_disk_sense_error dev->sense[0]
#define scsi_disk_sense_key dev->sense[2]
#define scsi_disk_asc dev->sense[12]
#define scsi_disk_ascq dev->sense[13]
/* Table of all SCSI commands and their flags, needed for the new disc change / not ready handler. */
const uint8_t scsi_disk_command_flags[0x100] = {
IMPLEMENTED | CHECK_READY | NONDATA, /* 0x00 */
@@ -103,30 +101,24 @@ const uint8_t scsi_disk_command_flags[0x100] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
uint64_t scsi_disk_mode_sense_page_flags = (GPMODEP_FORMAT_DEVICE_PAGE |
GPMODEP_RIGID_DISK_PAGE |
GPMODEP_UNK_VENDOR_PAGE |
GPMODEP_ALL_PAGES);
uint64_t scsi_disk_mode_sense_page_flags = (GPMODEP_FORMAT_DEVICE_PAGE | GPMODEP_RIGID_DISK_PAGE | GPMODEP_UNK_VENDOR_PAGE | GPMODEP_ALL_PAGES);
/* This should be done in a better way but for time being, it's been done this way so it's not as huge and more readable. */
static const mode_sense_pages_t scsi_disk_mode_sense_pages_default =
{ { [GPMODE_FORMAT_DEVICE_PAGE] = { GPMODE_FORMAT_DEVICE_PAGE, 0x16, 0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
[GPMODE_RIGID_DISK_PAGE ] = { GPMODE_RIGID_DISK_PAGE, 0x16, 0, 0x10, 0, 64, 0, 0, 0, 0, 0, 0, 0, 200, 0xff, 0xff, 0xff, 0, 0, 0, 0x15, 0x18, 0, 0 },
[GPMODE_UNK_VENDOR_PAGE ] = { 0xB0, 0x16, '8', '6', 'B', 'o', 'x', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ' }
} };
static const mode_sense_pages_t scsi_disk_mode_sense_pages_changeable =
{ { [GPMODE_FORMAT_DEVICE_PAGE] = { GPMODE_FORMAT_DEVICE_PAGE, 0x16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
[GPMODE_RIGID_DISK_PAGE ] = { GPMODE_RIGID_DISK_PAGE, 0x16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
[GPMODE_UNK_VENDOR_PAGE ] = { 0xB0, 0x16, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
} };
static const mode_sense_pages_t scsi_disk_mode_sense_pages_default = {
{[GPMODE_FORMAT_DEVICE_PAGE] = { GPMODE_FORMAT_DEVICE_PAGE, 0x16, 0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
[GPMODE_RIGID_DISK_PAGE] = { GPMODE_RIGID_DISK_PAGE, 0x16, 0, 0x10, 0, 64, 0, 0, 0, 0, 0, 0, 0, 200, 0xff, 0xff, 0xff, 0, 0, 0, 0x15, 0x18, 0, 0 },
[GPMODE_UNK_VENDOR_PAGE] = { 0xB0, 0x16, '8', '6', 'B', 'o', 'x', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ' }}
};
static const mode_sense_pages_t scsi_disk_mode_sense_pages_changeable = {
{[GPMODE_FORMAT_DEVICE_PAGE] = { GPMODE_FORMAT_DEVICE_PAGE, 0x16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
[GPMODE_RIGID_DISK_PAGE] = { GPMODE_RIGID_DISK_PAGE, 0x16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
[GPMODE_UNK_VENDOR_PAGE] = { 0xB0, 0x16, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}
};
#ifdef ENABLE_SCSI_DISK_LOG
int scsi_disk_do_log = ENABLE_SCSI_DISK_LOG;
static void
scsi_disk_log(const char *fmt, ...)
{
@@ -139,10 +131,9 @@ scsi_disk_log(const char *fmt, ...)
}
}
#else
#define scsi_disk_log(fmt, ...)
# define scsi_disk_log(fmt, ...)
#endif
void
scsi_disk_mode_sense_load(scsi_disk_t *dev)
{
@@ -162,7 +153,6 @@ scsi_disk_mode_sense_load(scsi_disk_t *dev)
}
}
void
scsi_disk_mode_sense_save(scsi_disk_t *dev)
{
@@ -178,7 +168,6 @@ scsi_disk_mode_sense_save(scsi_disk_t *dev)
}
}
/*SCSI Mode Sense 6/10*/
uint8_t
scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page, uint8_t pos)
@@ -186,12 +175,13 @@ scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page,
if (page_control == 1)
return scsi_disk_mode_sense_pages_changeable.pages[page][pos];
if (page == GPMODE_RIGID_DISK_PAGE) switch (page_control) {
if (page == GPMODE_RIGID_DISK_PAGE)
switch (page_control) {
/* Rigid disk geometry page. */
case 0:
case 2:
case 3:
switch(pos) {
switch (pos) {
case 0:
case 1:
default:
@@ -212,12 +202,14 @@ scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page,
return dev->drv->hpc & 0xff;
}
break;
} else if (page == GPMODE_FORMAT_DEVICE_PAGE) switch (page_control) {
}
else if (page == GPMODE_FORMAT_DEVICE_PAGE)
switch (page_control) {
/* Format device page. */
case 0:
case 2:
case 3:
switch(pos) {
switch (pos) {
case 0:
case 1:
default:
@@ -229,7 +221,9 @@ scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page,
return (dev->drv->spt + 1) & 0xff;
}
break;
} else switch (page_control) {
}
else
switch (page_control) {
case 0:
case 3:
return dev->ms_pages_saved.pages[page][pos];
@@ -240,7 +234,6 @@ scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page,
return 0;
}
uint32_t
scsi_disk_mode_sense(scsi_disk_t *dev, uint8_t *buf, uint32_t pos, uint8_t page, uint8_t block_descriptor_len)
{
@@ -280,7 +273,6 @@ scsi_disk_mode_sense(scsi_disk_t *dev, uint8_t *buf, uint32_t pos, uint8_t page,
return pos;
}
static void
scsi_disk_command_common(scsi_disk_t *dev)
{
@@ -292,7 +284,6 @@ scsi_disk_command_common(scsi_disk_t *dev)
dev->callback = -1.0; /* Speed depends on SCSI controller */
}
static void
scsi_disk_command_complete(scsi_disk_t *dev)
{
@@ -301,7 +292,6 @@ scsi_disk_command_complete(scsi_disk_t *dev)
scsi_disk_command_common(dev);
}
static void
scsi_disk_command_read_dma(scsi_disk_t *dev)
{
@@ -309,7 +299,6 @@ scsi_disk_command_read_dma(scsi_disk_t *dev)
scsi_disk_command_common(dev);
}
static void
scsi_disk_command_write_dma(scsi_disk_t *dev)
{
@@ -317,7 +306,6 @@ scsi_disk_command_write_dma(scsi_disk_t *dev)
scsi_disk_command_common(dev);
}
static void
scsi_disk_data_command_finish(scsi_disk_t *dev, int len, int block_len, int alloc_len, int direction)
{
@@ -337,14 +325,12 @@ scsi_disk_data_command_finish(scsi_disk_t *dev, int len, int block_len, int allo
}
}
static void
scsi_disk_sense_clear(scsi_disk_t *dev, int command)
{
scsi_disk_sense_key = scsi_disk_asc = scsi_disk_ascq = 0;
}
static void
scsi_disk_set_phase(scsi_disk_t *dev, uint8_t phase)
{
@@ -357,7 +343,6 @@ scsi_disk_set_phase(scsi_disk_t *dev, uint8_t phase)
scsi_devices[scsi_bus][scsi_id].phase = phase;
}
static void
scsi_disk_cmd_error(scsi_disk_t *dev)
{
@@ -371,7 +356,6 @@ scsi_disk_cmd_error(scsi_disk_t *dev)
scsi_disk_log("SCSI HD %i: ERROR: %02X/%02X/%02X\n", dev->id, scsi_disk_sense_key, scsi_disk_asc, scsi_disk_ascq);
}
static void
scsi_disk_invalid_lun(scsi_disk_t *dev)
{
@@ -382,7 +366,6 @@ scsi_disk_invalid_lun(scsi_disk_t *dev)
scsi_disk_cmd_error(dev);
}
static void
scsi_disk_illegal_opcode(scsi_disk_t *dev)
{
@@ -392,7 +375,6 @@ scsi_disk_illegal_opcode(scsi_disk_t *dev)
scsi_disk_cmd_error(dev);
}
static void
scsi_disk_lba_out_of_range(scsi_disk_t *dev)
{
@@ -402,7 +384,6 @@ scsi_disk_lba_out_of_range(scsi_disk_t *dev)
scsi_disk_cmd_error(dev);
}
static void
scsi_disk_invalid_field(scsi_disk_t *dev)
{
@@ -413,7 +394,6 @@ scsi_disk_invalid_field(scsi_disk_t *dev)
dev->status = 0x53;
}
static void
scsi_disk_invalid_field_pl(scsi_disk_t *dev)
{
@@ -424,7 +404,6 @@ scsi_disk_invalid_field_pl(scsi_disk_t *dev)
dev->status = 0x53;
}
static void
scsi_disk_data_phase_error(scsi_disk_t *dev)
{
@@ -434,7 +413,6 @@ scsi_disk_data_phase_error(scsi_disk_t *dev)
scsi_disk_cmd_error(dev);
}
static int
scsi_disk_pre_execution_check(scsi_disk_t *dev, uint8_t *cdb)
{
@@ -461,7 +439,6 @@ scsi_disk_pre_execution_check(scsi_disk_t *dev, uint8_t *cdb)
return 1;
}
static void
scsi_disk_seek(scsi_disk_t *dev, uint32_t pos)
{
@@ -469,7 +446,6 @@ scsi_disk_seek(scsi_disk_t *dev, uint32_t pos)
hdd_image_seek(dev->id, pos);
}
static void
scsi_disk_rezero(scsi_disk_t *dev)
{
@@ -480,7 +456,6 @@ scsi_disk_rezero(scsi_disk_t *dev)
scsi_disk_seek(dev, 0);
}
static void
scsi_disk_reset(scsi_common_t *sc)
{
@@ -493,7 +468,6 @@ scsi_disk_reset(scsi_common_t *sc)
dev->cur_lun = SCSI_LUN_USE_CDB;
}
void
scsi_disk_request_sense(scsi_disk_t *dev, uint8_t *buffer, uint8_t alloc_length, int desc)
{
@@ -518,7 +492,6 @@ scsi_disk_request_sense(scsi_disk_t *dev, uint8_t *buffer, uint8_t alloc_length,
scsi_disk_sense_clear(dev, GPCMD_REQUEST_SENSE);
}
static void
scsi_disk_request_sense_for_scsi(scsi_common_t *sc, uint8_t *buffer, uint8_t alloc_length)
{
@@ -527,7 +500,6 @@ scsi_disk_request_sense_for_scsi(scsi_common_t *sc, uint8_t *buffer, uint8_t all
scsi_disk_request_sense(dev, buffer, alloc_length, 0);
}
static void
scsi_disk_set_buf_len(scsi_disk_t *dev, int32_t *BufLen, int32_t *src_len)
{
@@ -540,7 +512,6 @@ scsi_disk_set_buf_len(scsi_disk_t *dev, int32_t *BufLen, int32_t *src_len)
scsi_disk_log("SCSI HD %i: Actual transfer length: %i\n", dev->id, *BufLen);
}
static void
scsi_disk_buf_alloc(scsi_disk_t *dev, uint32_t len)
{
@@ -549,7 +520,6 @@ scsi_disk_buf_alloc(scsi_disk_t *dev, uint32_t len)
dev->temp_buffer = (uint8_t *) malloc(len);
}
static void
scsi_disk_buf_free(scsi_disk_t *dev)
{
@@ -560,7 +530,6 @@ scsi_disk_buf_free(scsi_disk_t *dev)
}
}
static void
scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
{
@@ -675,7 +644,7 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
case GPCMD_READ_6:
case GPCMD_READ_10:
case GPCMD_READ_12:
switch(cdb[0]) {
switch (cdb[0]) {
case GPCMD_READ_6:
dev->sector_len = cdb[4];
if (dev->sector_len == 0)
@@ -692,7 +661,7 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
break;
}
if ((dev->sector_pos > last_sector)/* || ((dev->sector_pos + dev->sector_len - 1) > last_sector)*/) {
if ((dev->sector_pos > last_sector) /* || ((dev->sector_pos + dev->sector_len - 1) > last_sector)*/) {
scsi_disk_lba_out_of_range(dev);
return;
}
@@ -744,8 +713,7 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
case GPCMD_WRITE_AND_VERIFY_10:
case GPCMD_WRITE_12:
case GPCMD_WRITE_AND_VERIFY_12:
switch(cdb[0])
{
switch (cdb[0]) {
case GPCMD_VERIFY_6:
case GPCMD_WRITE_6:
dev->sector_len = cdb[4];
@@ -769,8 +737,9 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
break;
}
if ((dev->sector_pos > last_sector)/* ||
((dev->sector_pos + dev->sector_len - 1) > last_sector)*/) {
if ((dev->sector_pos > last_sector) /* ||
((dev->sector_pos + dev->sector_len - 1) > last_sector)*/
) {
scsi_disk_lba_out_of_range(dev);
return;
}
@@ -815,8 +784,9 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
dev->sector_len = (cdb[7] << 8) | cdb[8];
dev->sector_pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
if ((dev->sector_pos > last_sector)/* ||
((dev->sector_pos + dev->sector_len - 1) > last_sector)*/) {
if ((dev->sector_pos > last_sector) /* ||
((dev->sector_pos + dev->sector_len - 1) > last_sector)*/
) {
scsi_disk_lba_out_of_range(dev);
return;
}
@@ -1001,7 +971,7 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
atapi_out:
dev->temp_buffer[size_idx] = idx - preamble_len;
len=idx;
len = idx;
if (len > max_len)
len = max_len;
@@ -1022,12 +992,12 @@ atapi_out:
case GPCMD_SEEK_6:
case GPCMD_SEEK_10:
switch(cdb[0]) {
switch (cdb[0]) {
case GPCMD_SEEK_6:
pos = (cdb[2] << 8) | cdb[3];
break;
case GPCMD_SEEK_10:
pos = (cdb[2] << 24) | (cdb[3]<<16) | (cdb[4]<<8) | cdb[5];
pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
break;
}
scsi_disk_seek(dev, pos);
@@ -1062,7 +1032,6 @@ atapi_out:
/* scsi_disk_log("SCSI HD %i: Phase: %02X, request length: %i\n", dev->id, dev->phase, dev->request_length); */
}
static void
scsi_disk_command_stop(scsi_common_t *sc)
{
@@ -1072,7 +1041,6 @@ scsi_disk_command_stop(scsi_common_t *sc)
scsi_disk_buf_free(dev);
}
static uint8_t
scsi_disk_phase_data_out(scsi_common_t *sc)
{
@@ -1163,7 +1131,7 @@ scsi_disk_phase_data_out(scsi_common_t *sc)
pos = hdr_len + block_desc_len;
while(1) {
while (1) {
if (pos >= param_list_len) {
scsi_disk_log("SCSI HD %i: Buffer has only block descriptor\n", dev->id);
break;
@@ -1214,7 +1182,6 @@ scsi_disk_phase_data_out(scsi_common_t *sc)
return 1;
}
void
scsi_disk_hard_reset(void)
{
@@ -1243,7 +1210,7 @@ scsi_disk_hard_reset(void)
continue;
/* Make sure to ignore any SCSI disk whose image fails to load. */
if (! hdd_image_load(c))
if (!hdd_image_load(c))
continue;
if (!hdd[c].priv) {
@@ -1276,7 +1243,6 @@ scsi_disk_hard_reset(void)
}
}
void
scsi_disk_close(void)
{

153
src/scsi/scsi_ncr5380.c
View File

@@ -42,7 +42,6 @@
#include <86box/scsi_device.h>
#include <86box/scsi_ncr5380.h>
#define LCS6821N_ROM "roms/scsi/ncr5380/Longshine LCS-6821N - BIOS version 1.04.bin"
#define RT1000B_810R_ROM "roms/scsi/ncr5380/Rancho_RT1000_RTBios_version_8.10R.bin"
#define RT1000B_820R_ROM "roms/scsi/ncr5380/RTBIOS82.ROM"
@@ -50,7 +49,6 @@
#define T128_ROM "roms/scsi/ncr5380/trantor_t128_bios_v1.12.bin"
#define COREL_LS2000_ROM "roms/scsi/ncr5380/Corel LS2000 - BIOS ROM - Ver 1.65.bin"
#define NCR_CURDATA 0 /* current SCSI data (read only) */
#define NCR_OUTDATA 0 /* output data (write only) */
#define NCR_INITCOMMAND 1 /* initiator command (read/write) */
@@ -173,13 +171,11 @@ typedef struct {
#define DMA_SEND 1
#define DMA_INITIATOR_RECEIVE 2
static int cmd_len[8] = {6, 10, 10, 6, 16, 12, 6, 6};
static int cmd_len[8] = { 6, 10, 10, 6, 16, 12, 6, 6 };
#ifdef ENABLE_NCR5380_LOG
int ncr5380_do_log = ENABLE_NCR5380_LOG;
static void
ncr_log(const char *fmt, ...)
{
@@ -192,10 +188,9 @@ ncr_log(const char *fmt, ...)
}
}
#else
#define ncr_log(fmt, ...)
# define ncr_log(fmt, ...)
#endif
#define SET_BUS_STATE(ncr, state) ncr->cur_bus = (ncr->cur_bus & ~(SCSI_PHASE_MESSAGE_IN)) | (state & (SCSI_PHASE_MESSAGE_IN))
static void
@@ -225,17 +220,18 @@ get_dev_id(uint8_t data)
int c;
for (c = 0; c < SCSI_ID_MAX; c++) {
if (data & (1 << c)) return(c);
if (data & (1 << c))
return (c);
}
return(-1);
return (-1);
}
static int
getmsglen(uint8_t *msgp, int len)
{
uint8_t msg = msgp[0];
if (msg == 0 || (msg >= 0x02 && msg <= 0x1f) ||msg >= 0x80)
if (msg == 0 || (msg >= 0x02 && msg <= 0x1f) || msg >= 0x80)
return 1;
if (msg >= 0x20 && msg <= 0x2f)
return 2;
@@ -279,7 +275,6 @@ ncr_timer_on(ncr5380_t *ncr_dev, ncr_t *ncr, int callback)
timer_on_auto(&ncr_dev->timer, p);
}
static uint32_t
get_bus_host(ncr_t *ncr)
{
@@ -315,10 +310,9 @@ get_bus_host(ncr_t *ncr)
if (ncr->mode & MODE_ARBITRATE)
bus_host |= BUS_ARB;
return(bus_host | BUS_SETDATA(ncr->output_data));
return (bus_host | BUS_SETDATA(ncr->output_data));
}
static void
ncr_bus_read(ncr5380_t *ncr_dev)
{
@@ -375,11 +369,10 @@ ncr_bus_read(ncr5380_t *ncr_dev)
}
}
static void
ncr_bus_update(void *priv, int bus)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
double p;
@@ -404,7 +397,7 @@ ncr_bus_update(void *priv, int bus)
ncr_log("Select - target ID = %i\n", ncr->target_id);
/*Once the device has been found and selected, mark it as busy*/
if ((ncr->target_id != (uint8_t)-1) && scsi_device_present(&scsi_devices[ncr_dev->bus][ncr->target_id])) {
if ((ncr->target_id != (uint8_t) -1) && scsi_device_present(&scsi_devices[ncr_dev->bus][ncr->target_id])) {
ncr->cur_bus |= BUS_BSY;
ncr->state = STATE_SELECT;
} else {
@@ -416,7 +409,7 @@ ncr_bus_update(void *priv, int bus)
case STATE_SELECT:
if (!(bus & BUS_SEL)) {
if (!(bus & BUS_ATN)) {
if ((ncr->target_id != (uint8_t)-1) && scsi_device_present(&scsi_devices[ncr_dev->bus][ncr->target_id])) {
if ((ncr->target_id != (uint8_t) -1) && scsi_device_present(&scsi_devices[ncr_dev->bus][ncr->target_id])) {
ncr_log("Device found at ID %i, Current Bus BSY=%02x\n", ncr->target_id, ncr->cur_bus);
ncr->state = STATE_COMMAND;
ncr->cur_bus = BUS_BSY | BUS_REQ;
@@ -564,7 +557,7 @@ ncr_bus_update(void *priv, int bus)
}
break;
case STATE_MESSAGE_ID:
if ((ncr->target_id != (uint8_t)-1) && scsi_device_present(&scsi_devices[ncr_dev->bus][ncr->target_id])) {
if ((ncr->target_id != (uint8_t) -1) && scsi_device_present(&scsi_devices[ncr_dev->bus][ncr->target_id])) {
ncr_log("Device found at ID %i on MSGOUT, Current Bus BSY=%02x\n", ncr->target_id, ncr->cur_bus);
scsi_device_identify(&scsi_devices[ncr_dev->bus][ncr->target_id], ncr->msglun);
ncr->state = STATE_COMMAND;
@@ -579,16 +572,15 @@ ncr_bus_update(void *priv, int bus)
ncr->bus_in = bus;
}
static void
ncr_write(uint16_t port, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
int bus_host = 0;
ncr_log("NCR5380 write(%04x,%02x)\n",port & 7,val);
ncr_log("NCR5380 write(%04x,%02x)\n", port & 7, val);
switch (port & 7) {
case 0: /* Output data register */
@@ -720,11 +712,10 @@ ncr_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
ncr_read(uint16_t port, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
ncr_t *ncr = &ncr_dev->ncr;
uint8_t ret = 0xff;
int bus, bus_state;
@@ -838,15 +829,14 @@ ncr_read(uint16_t port, void *priv)
ncr_log("NCR5380 read(%04x)=%02x\n", port & 7, ret);
return(ret);
return (ret);
}
/* Memory-mapped I/O READ handler. */
static uint8_t
memio_read(uint32_t addr, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
uint8_t ret = 0xff;
@@ -859,7 +849,8 @@ memio_read(uint32_t addr, void *priv)
ret = 0xff;
else if (addr >= 0x3a00)
ret = ncr_dev->ext_ram[addr - 0x3a00];
else switch (addr & 0x3f80) {
else
switch (addr & 0x3f80) {
case 0x3800:
#if ENABLE_NCR5380_LOG
ncr_log("Read intRAM %02x %02x\n", addr & 0x3f, ncr_dev->int_ram[addr & 0x3f]);
@@ -916,15 +907,14 @@ memio_read(uint32_t addr, void *priv)
ncr_log("memio_read(%08x)=%02x\n", addr, ret);
#endif
return(ret);
return (ret);
}
/* Memory-mapped I/O WRITE handler. */
static void
memio_write(uint32_t addr, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
@@ -932,7 +922,8 @@ memio_write(uint32_t addr, uint8_t val, void *priv)
if (addr >= 0x3a00)
ncr_dev->ext_ram[addr - 0x3a00] = val;
else switch (addr & 0x3f80) {
else
switch (addr & 0x3f80) {
case 0x3800:
ncr_dev->int_ram[addr & 0x3f] = val;
break;
@@ -960,8 +951,7 @@ memio_write(uint32_t addr, uint8_t val, void *priv)
if ((val & CTRL_DATA_DIR) && !(ncr_dev->status_ctrl & CTRL_DATA_DIR)) {
ncr_dev->buffer_host_pos = MIN(128, dev->buffer_length);
ncr_dev->status_ctrl |= STATUS_BUFFER_NOT_READY;
}
else if (!(val & CTRL_DATA_DIR) && (ncr_dev->status_ctrl & CTRL_DATA_DIR)) {
} else if (!(val & CTRL_DATA_DIR) && (ncr_dev->status_ctrl & CTRL_DATA_DIR)) {
ncr_dev->buffer_host_pos = 0;
ncr_dev->status_ctrl &= ~STATUS_BUFFER_NOT_READY;
}
@@ -989,12 +979,11 @@ memio_write(uint32_t addr, uint8_t val, void *priv)
}
}
/* Memory-mapped I/O READ handler for the Trantor T130B. */
static uint8_t
t130b_read(uint32_t addr, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
uint8_t ret = 0xff;
addr &= 0x3fff;
@@ -1004,15 +993,14 @@ t130b_read(uint32_t addr, void *priv)
ret = ncr_dev->ext_ram[addr & 0x7f];
ncr_log("MEM: Reading %02X from %08X\n", ret, addr);
return(ret);
return (ret);
}
/* Memory-mapped I/O WRITE handler for the Trantor T130B. */
static void
t130b_write(uint32_t addr, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
addr &= 0x3fff;
ncr_log("MEM: Writing %02X to %08X\n", val, addr);
@@ -1020,51 +1008,69 @@ t130b_write(uint32_t addr, uint8_t val, void *priv)
ncr_dev->ext_ram[addr & 0x7f] = val;
}
static uint8_t
t130b_in(uint16_t port, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
uint8_t ret = 0xff;
switch (port & 0x0f) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x00:
case 0x01:
case 0x02:
case 0x03:
ret = memio_read((port & 7) | 0x3980, ncr_dev);
break;
case 0x04: case 0x05:
case 0x04:
case 0x05:
ret = memio_read(0x3900, ncr_dev);
break;
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
ret = ncr_read(port, ncr_dev);
break;
}
ncr_log("I/O: Reading %02X from %04X\n", ret, port);
return(ret);
return (ret);
}
static void
t130b_out(uint16_t port, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
ncr_log("I/O: Writing %02X to %04X\n", val, port);
switch (port & 0x0f) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x00:
case 0x01:
case 0x02:
case 0x03:
memio_write((port & 7) | 0x3980, val, ncr_dev);
break;
case 0x04: case 0x05:
case 0x04:
case 0x05:
memio_write(0x3900, val, ncr_dev);
break;
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
ncr_write(port, val, ncr_dev);
break;
}
@@ -1227,7 +1233,7 @@ ncr_dma_initiator_receive(ncr5380_t *ncr_dev, ncr_t *ncr, scsi_device_t *dev)
static void
ncr_callback(void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
@@ -1255,7 +1261,7 @@ ncr_callback(void *priv)
}
}
switch(ncr->dma_mode) {
switch (ncr->dma_mode) {
case DMA_SEND:
if (ncr_dev->type != 3) {
if (ncr_dev->status_ctrl & CTRL_DATA_DIR) {
@@ -1332,7 +1338,7 @@ ncr_callback(void *priv)
static uint8_t
t128_read(uint32_t addr, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
uint8_t ret = 0xff;
@@ -1382,13 +1388,13 @@ t128_read(uint32_t addr, void *priv)
}
}
return(ret);
return (ret);
}
static void
t128_write(uint32_t addr, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
ncr_t *ncr = &ncr_dev->ncr;
scsi_device_t *dev = &scsi_devices[ncr_dev->bus][ncr->target_id];
@@ -1439,19 +1445,19 @@ t128_write(uint32_t addr, uint8_t val, void *priv)
static uint8_t
rt1000b_mc_read(int port, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
return(ncr_dev->pos_regs[port & 7]);
return (ncr_dev->pos_regs[port & 7]);
}
static void
rt1000b_mc_write(int port, uint8_t val, void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102) return;
if (port < 0x0102)
return;
mem_mapping_disable(&ncr_dev->bios_rom.mapping);
mem_mapping_disable(&ncr_dev->mapping);
@@ -1489,7 +1495,7 @@ rt1000b_mc_write(int port, uint8_t val, void *priv)
static uint8_t
rt1000b_mc_feedb(void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
return ncr_dev->pos_regs[2] & 1;
}
@@ -1508,7 +1514,7 @@ ncr_init(const device_t *info)
ncr_dev->bus = scsi_get_bus();
switch(ncr_dev->type) {
switch (ncr_dev->type) {
case 0: /* Longshine LCS6821N */
ncr_dev->rom_addr = device_get_config_hex20("bios_addr");
ncr_dev->irq = device_get_config_int("irq");
@@ -1570,7 +1576,7 @@ ncr_init(const device_t *info)
}
io_sethandler(ncr_dev->base, 16,
t130b_in,NULL,NULL, t130b_out,NULL,NULL, ncr_dev);
t130b_in, NULL, NULL, t130b_out, NULL, NULL, ncr_dev);
break;
case 3: /* Trantor T128 */
@@ -1621,14 +1627,13 @@ ncr_init(const device_t *info)
}
timer_add(&ncr_dev->timer, ncr_callback, ncr_dev, 0);
return(ncr_dev);
return (ncr_dev);
}
static void
ncr_close(void *priv)
{
ncr5380_t *ncr_dev = (ncr5380_t *)priv;
ncr5380_t *ncr_dev = (ncr5380_t *) priv;
if (ncr_dev) {
/* Tell the timer to terminate. */
@@ -1639,42 +1644,40 @@ ncr_close(void *priv)
}
}
static int
lcs6821n_available(void)
{
return(rom_present(LCS6821N_ROM));
return (rom_present(LCS6821N_ROM));
}
static int
rt1000b_available(void)
{
return(rom_present(RT1000B_820R_ROM) && rom_present(RT1000B_810R_ROM));
return (rom_present(RT1000B_820R_ROM) && rom_present(RT1000B_810R_ROM));
}
static int
rt1000b_820_available(void)
{
return(rom_present(RT1000B_820R_ROM));
return (rom_present(RT1000B_820R_ROM));
}
static int
t130b_available(void)
{
return(rom_present(T130B_ROM));
return (rom_present(T130B_ROM));
}
static int
t128_available(void)
{
return(rom_present(T128_ROM));
return (rom_present(T128_ROM));
}
static int
corel_ls2000_available(void)
{
return(rom_present(COREL_LS2000_ROM));
return (rom_present(COREL_LS2000_ROM));
}
// clang-format off

242
src/scsi/scsi_ncr53c8xx.c
View File

@@ -45,7 +45,6 @@
#include <86box/scsi_device.h>
#include <86box/scsi_ncr53c8xx.h>
#define NCR53C8XX_SDMS3_ROM "roms/scsi/ncr53c8xx/NCR307.BIN"
#define SYM53C8XX_SDMS4_ROM "roms/scsi/ncr53c8xx/8xx_64.rom"
@@ -196,8 +195,7 @@ typedef struct ncr53c8xx_request {
int out;
} ncr53c8xx_request;
typedef enum
{
typedef enum {
SCSI_STATE_SEND_COMMAND,
SCSI_STATE_READ_DATA,
SCSI_STATE_WRITE_DATA,
@@ -317,11 +315,9 @@ typedef struct {
#endif
} ncr53c8xx_t;
#ifdef ENABLE_NCR53C8XX_LOG
int ncr53c8xx_do_log = ENABLE_NCR53C8XX_LOG;
static void
ncr53c8xx_log(const char *fmt, ...)
{
@@ -334,31 +330,27 @@ ncr53c8xx_log(const char *fmt, ...)
}
}
#else
#define ncr53c8xx_log(fmt, ...)
# define ncr53c8xx_log(fmt, ...)
#endif
static uint8_t ncr53c8xx_reg_readb(ncr53c8xx_t *dev, uint32_t offset);
static void ncr53c8xx_reg_writeb(ncr53c8xx_t *dev, uint32_t offset, uint8_t val);
static __inline int32_t
sextract32(uint32_t value, int start, int length)
{
/* Note that this implementation relies on right shift of signed
* integers being an arithmetic shift.
*/
return ((int32_t)(value << (32 - length - start))) >> (32 - length);
return ((int32_t) (value << (32 - length - start))) >> (32 - length);
}
static __inline int
ncr53c8xx_irq_on_rsl(ncr53c8xx_t *dev)
{
return (dev->sien0 & NCR_SIST0_RSL) && (dev->scid & NCR_SCID_RRE);
}
static void
ncr53c8xx_soft_reset(ncr53c8xx_t *dev)
{
@@ -456,7 +448,6 @@ ncr53c8xx_soft_reset(ncr53c8xx_t *dev)
}
}
static void
ncr53c8xx_read(ncr53c8xx_t *dev, uint32_t addr, uint8_t *buf, uint32_t len)
{
@@ -474,7 +465,6 @@ ncr53c8xx_read(ncr53c8xx_t *dev, uint32_t addr, uint8_t *buf, uint32_t len)
}
}
static void
ncr53c8xx_write(ncr53c8xx_t *dev, uint32_t addr, uint8_t *buf, uint32_t len)
{
@@ -492,19 +482,17 @@ ncr53c8xx_write(ncr53c8xx_t *dev, uint32_t addr, uint8_t *buf, uint32_t len)
}
}
static __inline uint32_t
read_dword(ncr53c8xx_t *dev, uint32_t addr)
{
uint32_t buf;
ncr53c8xx_log("Reading the next DWORD from memory (%08X)...\n", addr);
dma_bm_read(addr, (uint8_t *)&buf, 4, 4);
dma_bm_read(addr, (uint8_t *) &buf, 4, 4);
return buf;
}
static
void do_irq(ncr53c8xx_t *dev, int level)
static void
do_irq(ncr53c8xx_t *dev, int level)
{
if (level) {
pci_set_irq(dev->pci_slot, PCI_INTA);
@@ -515,7 +503,6 @@ void do_irq(ncr53c8xx_t *dev, int level)
}
}
static void
ncr53c8xx_update_irq(ncr53c8xx_t *dev)
{
@@ -552,7 +539,6 @@ ncr53c8xx_update_irq(ncr53c8xx_t *dev)
}
}
/* Stop SCRIPTS execution and raise a SCSI interrupt. */
static void
ncr53c8xx_script_scsi_interrupt(ncr53c8xx_t *dev, int stat0, int stat1)
@@ -578,7 +564,6 @@ ncr53c8xx_script_scsi_interrupt(ncr53c8xx_t *dev, int stat0, int stat1)
ncr53c8xx_update_irq(dev);
}
/* Stop SCRIPTS execution and raise a DMA interrupt. */
static void
ncr53c8xx_script_dma_interrupt(ncr53c8xx_t *dev, int stat)
@@ -590,14 +575,12 @@ ncr53c8xx_script_dma_interrupt(ncr53c8xx_t *dev, int stat)
timer_stop(&dev->timer);
}
static __inline void
ncr53c8xx_set_phase(ncr53c8xx_t *dev, int phase)
{
dev->sstat1 = (dev->sstat1 & ~PHASE_MASK) | phase;
}
static void
ncr53c8xx_bad_phase(ncr53c8xx_t *dev, int out, int new_phase)
{
@@ -609,7 +592,6 @@ ncr53c8xx_bad_phase(ncr53c8xx_t *dev, int out, int new_phase)
ncr53c8xx_set_phase(dev, new_phase);
}
static void
ncr53c8xx_disconnect(ncr53c8xx_t *dev)
{
@@ -624,7 +606,6 @@ ncr53c8xx_disconnect(ncr53c8xx_t *dev)
scsi_device_identify(sd, SCSI_LUN_USE_CDB);
}
static void
ncr53c8xx_bad_selection(ncr53c8xx_t *dev, uint32_t id)
{
@@ -633,16 +614,15 @@ ncr53c8xx_bad_selection(ncr53c8xx_t *dev, uint32_t id)
ncr53c8xx_disconnect(dev);
}
/* Callback to indicate that the SCSI layer has completed a command. */
static void
ncr53c8xx_command_complete(void *priv, uint32_t status)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)priv;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
int out;
out = (dev->sstat1 & PHASE_MASK) == PHASE_DO;
ncr53c8xx_log("(ID=%02i LUN=%02i) SCSI Command 0x%02x: Command complete status=%d\n", dev->current->tag, dev->current_lun, dev->last_command, (int)status);
ncr53c8xx_log("(ID=%02i LUN=%02i) SCSI Command 0x%02x: Command complete status=%d\n", dev->current->tag, dev->current_lun, dev->last_command, (int) status);
dev->status = status;
dev->command_complete = 2;
if (dev->waiting && dev->dbc != 0) {
@@ -654,7 +634,6 @@ ncr53c8xx_command_complete(void *priv, uint32_t status)
dev->sstop = 0;
}
static void
ncr53c8xx_do_dma(ncr53c8xx_t *dev, int out, uint8_t id)
{
@@ -711,7 +690,6 @@ ncr53c8xx_do_dma(ncr53c8xx_t *dev, int out, uint8_t id)
}
}
/* Queue a byte for a MSG IN phase. */
static void
ncr53c8xx_add_msg_byte(ncr53c8xx_t *dev, uint8_t data)
@@ -724,7 +702,6 @@ ncr53c8xx_add_msg_byte(ncr53c8xx_t *dev, uint8_t data)
}
}
static void
ncr53c8xx_timer_on(ncr53c8xx_t *dev, scsi_device_t *sd, double p)
{
@@ -736,7 +713,6 @@ ncr53c8xx_timer_on(ncr53c8xx_t *dev, scsi_device_t *sd, double p)
timer_on_auto(&dev->timer, period + 40.0);
}
static int
ncr53c8xx_do_command(ncr53c8xx_t *dev, uint8_t id)
{
@@ -759,7 +735,7 @@ ncr53c8xx_do_command(ncr53c8xx_t *dev, uint8_t id)
return 0;
}
dev->current = (ncr53c8xx_request*)malloc(sizeof(ncr53c8xx_request));
dev->current = (ncr53c8xx_request *) malloc(sizeof(ncr53c8xx_request));
dev->current->tag = id;
sd->buffer_length = -1;
@@ -772,7 +748,7 @@ ncr53c8xx_do_command(ncr53c8xx_t *dev, uint8_t id)
buf[1] = (buf[1] & 0x1f) | (dev->current_lun << 5);
scsi_device_command_phase0(&scsi_devices[dev->bus][dev->current->tag], buf);
dev->hba_private = (void *)dev->current;
dev->hba_private = (void *) dev->current;
dev->waiting = 0;
dev->buffer_pos = 0;
@@ -800,7 +776,6 @@ ncr53c8xx_do_command(ncr53c8xx_t *dev, uint8_t id)
}
}
static void
ncr53c8xx_do_status(ncr53c8xx_t *dev)
{
@@ -817,7 +792,6 @@ ncr53c8xx_do_status(ncr53c8xx_t *dev)
ncr53c8xx_add_msg_byte(dev, 0); /* COMMAND COMPLETE */
}
#ifdef USE_WDTR
static void
ncr53c8xx_do_wdtr(ncr53c8xx_t *dev, int exponent)
@@ -832,7 +806,6 @@ ncr53c8xx_do_wdtr(ncr53c8xx_t *dev, int exponent)
}
#endif
static void
ncr53c8xx_do_msgin(ncr53c8xx_t *dev)
{
@@ -873,7 +846,6 @@ ncr53c8xx_do_msgin(ncr53c8xx_t *dev)
}
}
/* Read the next byte during a MSGOUT phase. */
static uint8_t
ncr53c8xx_get_msgbyte(ncr53c8xx_t *dev)
@@ -885,7 +857,6 @@ ncr53c8xx_get_msgbyte(ncr53c8xx_t *dev)
return data;
}
/* Skip the next n bytes during a MSGOUT phase. */
static void
ncr53c8xx_skip_msgbytes(ncr53c8xx_t *dev, unsigned int n)
@@ -894,7 +865,6 @@ ncr53c8xx_skip_msgbytes(ncr53c8xx_t *dev, unsigned int n)
dev->dbc -= n;
}
static void
ncr53c8xx_bad_message(ncr53c8xx_t *dev, uint8_t msg)
{
@@ -904,7 +874,6 @@ ncr53c8xx_bad_message(ncr53c8xx_t *dev, uint8_t msg)
dev->msg_action = 0;
}
static void
ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
{
@@ -1018,7 +987,6 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
}
}
static void
ncr53c8xx_memcpy(ncr53c8xx_t *dev, uint32_t dest, uint32_t src, int count)
{
@@ -1036,7 +1004,6 @@ ncr53c8xx_memcpy(ncr53c8xx_t *dev, uint32_t dest, uint32_t src, int count)
}
}
static void
ncr53c8xx_process_script(ncr53c8xx_t *dev)
{
@@ -1091,7 +1058,7 @@ again:
/* 32-bit Table indirect */
offset = sextract32(addr, 0, 24);
dma_bm_read(dev->dsa + offset, (uint8_t *)buf, 8, 4);
dma_bm_read(dev->dsa + offset, (uint8_t *) buf, 8, 4);
/* byte count is stored in bits 0:23 only */
dev->dbc = buf[0] & 0xffffff;
addr = buf[1];
@@ -1225,7 +1192,7 @@ again:
reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
data8 = (insn >> 8) & 0xff;
opcode = (insn >> 27) & 7;
operator = (insn >> 24) & 7;
operator=(insn >> 24) & 7;
op0 = op1 = 0;
switch (opcode) {
case 5: /* From SFBR */
@@ -1428,7 +1395,6 @@ again:
ncr53c8xx_log("SCRIPTS execution stopped\n");
}
static void
ncr53c8xx_execute_script(ncr53c8xx_t *dev)
{
@@ -1436,7 +1402,6 @@ ncr53c8xx_execute_script(ncr53c8xx_t *dev)
timer_on_auto(&dev->timer, 40.0);
}
static void
ncr53c8xx_callback(void *p)
{
@@ -1453,13 +1418,12 @@ ncr53c8xx_callback(void *p)
timer_stop(&dev->timer);
}
static void
ncr53c8xx_eeprom(ncr53c8xx_t *dev, uint8_t save)
{
FILE *f;
f = nvr_fopen(dev->nvr_path, save ? "wb": "rb");
f = nvr_fopen(dev->nvr_path, save ? "wb" : "rb");
if (f) {
if (save)
fwrite(&dev->nvram, sizeof(dev->nvram), 1, f);
@@ -1469,22 +1433,42 @@ ncr53c8xx_eeprom(ncr53c8xx_t *dev, uint8_t save)
}
}
static void
ncr53c8xx_reg_writeb(ncr53c8xx_t *dev, uint32_t offset, uint8_t val)
{
uint8_t tmp = 0;
#define CASE_SET_REG24(name, addr) \
case addr : dev->name &= 0xffffff00; dev->name |= val; break; \
case addr + 1: dev->name &= 0xffff00ff; dev->name |= val << 8; break; \
case addr + 2: dev->name &= 0xff00ffff; dev->name |= val << 16; break;
case addr: \
dev->name &= 0xffffff00; \
dev->name |= val; \
break; \
case addr + 1: \
dev->name &= 0xffff00ff; \
dev->name |= val << 8; \
break; \
case addr + 2: \
dev->name &= 0xff00ffff; \
dev->name |= val << 16; \
break;
#define CASE_SET_REG32(name, addr) \
case addr : dev->name &= 0xffffff00; dev->name |= val; break; \
case addr + 1: dev->name &= 0xffff00ff; dev->name |= val << 8; break; \
case addr + 2: dev->name &= 0xff00ffff; dev->name |= val << 16; break; \
case addr + 3: dev->name &= 0x00ffffff; dev->name |= val << 24; break;
case addr: \
dev->name &= 0xffffff00; \
dev->name |= val; \
break; \
case addr + 1: \
dev->name &= 0xffff00ff; \
dev->name |= val << 8; \
break; \
case addr + 2: \
dev->name &= 0xff00ffff; \
dev->name |= val << 16; \
break; \
case addr + 3: \
dev->name &= 0x00ffffff; \
dev->name |= val << 24; \
break;
#ifdef DEBUG_NCR_REG
ncr53c8xx_log("Write reg %02x = %02x\n", offset, val);
@@ -1549,10 +1533,14 @@ ncr53c8xx_reg_writeb(ncr53c8xx_t *dev, uint32_t offset, uint8_t val)
ncr53c8xx_log("NCR 810: SOCL write %02X\n", val);
dev->socl = val;
break;
case 0x0a: case 0x0b:
case 0x0a:
case 0x0b:
/* Openserver writes to these readonly registers on startup */
return;
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
/* Linux writes to these readonly registers on startup. */
return;
CASE_SET_REG32(dsa, 0x10)
@@ -1708,36 +1696,46 @@ ncr53c8xx_reg_writeb(ncr53c8xx_t *dev, uint32_t offset, uint8_t val)
#undef CASE_SET_REG32
}
static uint8_t
ncr53c8xx_reg_readb(ncr53c8xx_t *dev, uint32_t offset)
{
uint8_t tmp;
#define CASE_GET_REG24(name, addr) \
case addr: return dev->name & 0xff; \
case addr + 1: return (dev->name >> 8) & 0xff; \
case addr + 2: return (dev->name >> 16) & 0xff;
case addr: \
return dev->name & 0xff; \
case addr + 1: \
return (dev->name >> 8) & 0xff; \
case addr + 2: \
return (dev->name >> 16) & 0xff;
#define CASE_GET_REG32(name, addr) \
case addr: return dev->name & 0xff; \
case addr + 1: return (dev->name >> 8) & 0xff; \
case addr + 2: return (dev->name >> 16) & 0xff; \
case addr + 3: return (dev->name >> 24) & 0xff;
case addr: \
return dev->name & 0xff; \
case addr + 1: \
return (dev->name >> 8) & 0xff; \
case addr + 2: \
return (dev->name >> 16) & 0xff; \
case addr + 3: \
return (dev->name >> 24) & 0xff;
#define CASE_GET_REG32_COND(name, addr) \
case addr: if (dev->wide) \
case addr: \
if (dev->wide) \
return dev->name & 0xff; \
else \
return 0x00; \
case addr + 1: if (dev->wide) \
case addr + 1: \
if (dev->wide) \
return (dev->name >> 8) & 0xff; \
else \
return 0x00; \
case addr + 2: if (dev->wide) \
case addr + 2: \
if (dev->wide) \
return (dev->name >> 16) & 0xff; \
else \
return 0x00; \
case addr + 3: if (dev->wide) \
case addr + 3: \
if (dev->wide) \
return (dev->name >> 24) & 0xff; \
else \
return 0x00;
@@ -1988,19 +1986,17 @@ ncr53c8xx_reg_readb(ncr53c8xx_t *dev, uint32_t offset)
#undef CASE_GET_REG32
}
static uint8_t
ncr53c8xx_io_readb(uint16_t addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
return ncr53c8xx_reg_readb(dev, addr & 0xff);
}
static uint16_t
ncr53c8xx_io_readw(uint16_t addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
uint16_t val;
addr &= 0xff;
@@ -2009,11 +2005,10 @@ ncr53c8xx_io_readw(uint16_t addr, void *p)
return val;
}
static uint32_t
ncr53c8xx_io_readl(uint16_t addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
uint32_t val;
addr &= 0xff;
@@ -2024,29 +2019,26 @@ ncr53c8xx_io_readl(uint16_t addr, void *p)
return val;
}
static void
ncr53c8xx_io_writeb(uint16_t addr, uint8_t val, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_reg_writeb(dev, addr & 0xff, val);
}
static void
ncr53c8xx_io_writew(uint16_t addr, uint16_t val, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
addr &= 0xff;
ncr53c8xx_reg_writeb(dev, addr, val & 0xff);
ncr53c8xx_reg_writeb(dev, addr + 1, (val >> 8) & 0xff);
}
static void
ncr53c8xx_io_writel(uint16_t addr, uint32_t val, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
addr &= 0xff;
ncr53c8xx_reg_writeb(dev, addr, val & 0xff);
ncr53c8xx_reg_writeb(dev, addr + 1, (val >> 8) & 0xff);
@@ -2054,31 +2046,28 @@ ncr53c8xx_io_writel(uint16_t addr, uint32_t val, void *p)
ncr53c8xx_reg_writeb(dev, addr + 3, (val >> 24) & 0xff);
}
static void
ncr53c8xx_mmio_writeb(uint32_t addr, uint8_t val, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_reg_writeb(dev, addr & 0xff, val);
}
static void
ncr53c8xx_mmio_writew(uint32_t addr, uint16_t val, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
addr &= 0xff;
ncr53c8xx_reg_writeb(dev, addr, val & 0xff);
ncr53c8xx_reg_writeb(dev, addr + 1, (val >> 8) & 0xff);
}
static void
ncr53c8xx_mmio_writel(uint32_t addr, uint32_t val, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
addr &= 0xff;
ncr53c8xx_reg_writeb(dev, addr, val & 0xff);
@@ -2087,20 +2076,18 @@ ncr53c8xx_mmio_writel(uint32_t addr, uint32_t val, void *p)
ncr53c8xx_reg_writeb(dev, addr + 3, (val >> 24) & 0xff);
}
static uint8_t
ncr53c8xx_mmio_readb(uint32_t addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
return ncr53c8xx_reg_readb(dev, addr & 0xff);
}
static uint16_t
ncr53c8xx_mmio_readw(uint32_t addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
uint16_t val;
addr &= 0xff;
@@ -2109,11 +2096,10 @@ ncr53c8xx_mmio_readw(uint32_t addr, void *p)
return val;
}
static uint32_t
ncr53c8xx_mmio_readl(uint32_t addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
uint32_t val;
addr &= 0xff;
@@ -2125,16 +2111,14 @@ ncr53c8xx_mmio_readl(uint32_t addr, void *p)
return val;
}
static void
ncr53c8xx_ram_writeb(uint32_t addr, uint8_t val, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
dev->ram[addr & 0x0fff] = val;
}
static void
ncr53c8xx_ram_writew(uint32_t addr, uint16_t val, void *p)
{
@@ -2142,7 +2126,6 @@ ncr53c8xx_ram_writew(uint32_t addr, uint16_t val, void *p)
ncr53c8xx_ram_writeb(addr + 1, (val >> 8) & 0xff, p);
}
static void
ncr53c8xx_ram_writel(uint32_t addr, uint32_t val, void *p)
{
@@ -2152,16 +2135,14 @@ ncr53c8xx_ram_writel(uint32_t addr, uint32_t val, void *p)
ncr53c8xx_ram_writeb(addr + 3, (val >> 24) & 0xff, p);
}
static uint8_t
ncr53c8xx_ram_readb(uint32_t addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
return dev->ram[addr & 0x0fff];
}
static uint16_t
ncr53c8xx_ram_readw(uint32_t addr, void *p)
{
@@ -2173,7 +2154,6 @@ ncr53c8xx_ram_readw(uint32_t addr, void *p)
return val;
}
static uint32_t
ncr53c8xx_ram_readl(uint32_t addr, void *p)
{
@@ -2187,7 +2167,6 @@ ncr53c8xx_ram_readl(uint32_t addr, void *p)
return val;
}
static void
ncr53c8xx_io_set(ncr53c8xx_t *dev, uint32_t base, uint16_t len)
{
@@ -2197,7 +2176,6 @@ ncr53c8xx_io_set(ncr53c8xx_t *dev, uint32_t base, uint16_t len)
ncr53c8xx_io_writeb, ncr53c8xx_io_writew, ncr53c8xx_io_writel, dev);
}
static void
ncr53c8xx_io_remove(ncr53c8xx_t *dev, uint32_t base, uint16_t len)
{
@@ -2207,7 +2185,6 @@ ncr53c8xx_io_remove(ncr53c8xx_t *dev, uint32_t base, uint16_t len)
ncr53c8xx_io_writeb, ncr53c8xx_io_writew, ncr53c8xx_io_writel, dev);
}
static void
ncr53c8xx_mem_init(ncr53c8xx_t *dev, uint32_t addr)
{
@@ -2217,7 +2194,6 @@ ncr53c8xx_mem_init(ncr53c8xx_t *dev, uint32_t addr)
NULL, MEM_MAPPING_EXTERNAL, dev);
}
static void
ncr53c8xx_ram_init(ncr53c8xx_t *dev, uint32_t addr)
{
@@ -2227,21 +2203,18 @@ ncr53c8xx_ram_init(ncr53c8xx_t *dev, uint32_t addr)
NULL, MEM_MAPPING_EXTERNAL, dev);
}
static void
ncr53c8xx_mem_set_addr(ncr53c8xx_t *dev, uint32_t base)
{
mem_mapping_set_addr(&dev->mmio_mapping, base, 0x100);
}
static void
ncr53c8xx_ram_set_addr(ncr53c8xx_t *dev, uint32_t base)
{
mem_mapping_set_addr(&dev->ram_mapping, base, 0x1000);
}
static void
ncr53c8xx_bios_set_addr(ncr53c8xx_t *dev, uint32_t base)
{
@@ -2251,36 +2224,31 @@ ncr53c8xx_bios_set_addr(ncr53c8xx_t *dev, uint32_t base)
mem_mapping_set_addr(&dev->bios.mapping, base, 0x04000);
}
static void
ncr53c8xx_mem_disable(ncr53c8xx_t *dev)
{
mem_mapping_disable(&dev->mmio_mapping);
}
static void
ncr53c8xx_ram_disable(ncr53c8xx_t *dev)
{
mem_mapping_disable(&dev->ram_mapping);
}
static void
ncr53c8xx_bios_disable(ncr53c8xx_t *dev)
{
mem_mapping_disable(&dev->bios.mapping);
}
uint8_t ncr53c8xx_pci_regs[256];
bar_t ncr53c8xx_pci_bar[4];
static uint8_t
ncr53c8xx_pci_read(int func, int addr, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_log("NCR53c8xx: Reading register %02X\n", addr & 0xff);
@@ -2375,14 +2343,13 @@ ncr53c8xx_pci_read(int func, int addr, void *p)
return 0x40;
}
return(0);
return (0);
}
static void
ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
uint8_t valxor;
ncr53c8xx_log("NCR53c8xx: Write value %02X to register %02X\n", val, addr & 0xff);
@@ -2392,8 +2359,7 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
return;
}
switch (addr)
{
switch (addr) {
case 0x04:
valxor = (val & 0x57) ^ ncr53c8xx_pci_regs[addr];
if (valxor & PCI_COMMAND_IO) {
@@ -2423,7 +2389,10 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
ncr53c8xx_pci_regs[addr] = val;
break;
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x10:
case 0x11:
case 0x12:
case 0x13:
/* I/O Base set. */
/* First, remove the old I/O. */
ncr53c8xx_io_remove(dev, dev->PCIBase, 0x0100);
@@ -2433,7 +2402,7 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
ncr53c8xx_pci_bar[0].addr &= 0xff00;
dev->PCIBase = ncr53c8xx_pci_bar[0].addr;
/* Log the new base. */
ncr53c8xx_log("NCR53c8xx: New I/O base is %04X\n" , dev->PCIBase);
ncr53c8xx_log("NCR53c8xx: New I/O base is %04X\n", dev->PCIBase);
/* We're done, so get out of the here. */
if (ncr53c8xx_pci_regs[4] & PCI_COMMAND_IO) {
if (dev->PCIBase != 0) {
@@ -2442,7 +2411,9 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
}
return;
case 0x15: case 0x16: case 0x17:
case 0x15:
case 0x16:
case 0x17:
/* MMIO Base set. */
/* First, remove the old I/O. */
ncr53c8xx_mem_disable(dev);
@@ -2452,7 +2423,7 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
ncr53c8xx_pci_bar[1].addr &= 0xffffc000;
dev->MMIOBase = ncr53c8xx_pci_bar[1].addr & 0xffffc000;
/* Log the new base. */
ncr53c8xx_log("NCR53c8xx: New MMIO base is %08X\n" , dev->MMIOBase);
ncr53c8xx_log("NCR53c8xx: New MMIO base is %08X\n", dev->MMIOBase);
/* We're done, so get out of the here. */
if (ncr53c8xx_pci_regs[4] & PCI_COMMAND_MEM) {
if (dev->MMIOBase != 0)
@@ -2460,7 +2431,9 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
}
return;
case 0x19: case 0x1A: case 0x1B:
case 0x19:
case 0x1A:
case 0x1B:
if (!dev->wide)
return;
/* RAM Base set. */
@@ -2472,7 +2445,7 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
ncr53c8xx_pci_bar[2].addr &= 0xfffff000;
dev->RAMBase = ncr53c8xx_pci_bar[2].addr & 0xfffff000;
/* Log the new base. */
ncr53c8xx_log("NCR53c8xx: New RAM base is %08X\n" , dev->RAMBase);
ncr53c8xx_log("NCR53c8xx: New RAM base is %08X\n", dev->RAMBase);
/* We're done, so get out of the here. */
if (ncr53c8xx_pci_regs[4] & PCI_COMMAND_MEM) {
if (dev->RAMBase != 0)
@@ -2480,7 +2453,10 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
}
return;
case 0x30: case 0x31: case 0x32: case 0x33:
case 0x30:
case 0x31:
case 0x32:
case 0x33:
if (dev->has_bios == 0)
return;
/* BIOS Base set. */
@@ -2493,7 +2469,7 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
dev->BIOSBase = ncr53c8xx_pci_bar[3].addr & dev->bios_mask;
ncr53c8xx_log("BIOS BAR: %08X\n", dev->BIOSBase | ncr53c8xx_pci_bar[3].addr_regs[0]);
/* Log the new base. */
ncr53c8xx_log("NCR53c8xx: New BIOS base is %08X\n" , dev->BIOSBase);
ncr53c8xx_log("NCR53c8xx: New BIOS base is %08X\n", dev->BIOSBase);
/* We're done, so get out of the here. */
if (ncr53c8xx_pci_bar[3].addr_regs[0] & 0x01)
ncr53c8xx_bios_set_addr(dev, dev->BIOSBase);
@@ -2506,7 +2482,6 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
}
}
static void *
ncr53c8xx_init(const device_t *info)
{
@@ -2609,14 +2584,13 @@ ncr53c8xx_init(const device_t *info)
timer_add(&dev->timer, ncr53c8xx_callback, dev, 0);
return(dev);
return (dev);
}
static void
ncr53c8xx_close(void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *)priv;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
if (dev) {
if (dev->eeprom)
@@ -2634,7 +2608,7 @@ ncr53c8xx_close(void *priv)
}
static const device_config_t ncr53c8xx_pci_config[] = {
// clang-format off
// clang-format off
{
.name = "bios",
.description = "BIOS",

117
src/scsi/scsi_pcscsi.c
View File

@@ -204,11 +204,9 @@ typedef struct {
#define READ_FROM_DEVICE 1
#define WRITE_TO_DEVICE 0
#ifdef ENABLE_ESP_LOG
int esp_do_log = ENABLE_ESP_LOG;
static void
esp_log(const char *fmt, ...)
{
@@ -221,7 +219,7 @@ esp_log(const char *fmt, ...)
}
}
#else
#define esp_log(fmt, ...)
# define esp_log(fmt, ...)
#endif
static void esp_dma_enable(esp_t *dev, int level);
@@ -569,7 +567,8 @@ esp_do_nodma(esp_t *dev, scsi_device_t *sd)
dev->do_cmd = 0;
esp_do_cmd(dev);
} else {
dev->cmdfifo_cdb_offset = fifo8_num_used(&dev->cmdfifo);;
dev->cmdfifo_cdb_offset = fifo8_num_used(&dev->cmdfifo);
;
esp_log("CDB offset = %i used\n", dev->cmdfifo_cdb_offset);
dev->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
@@ -641,7 +640,6 @@ esp_do_nodma(esp_t *dev, scsi_device_t *sd)
}
}
static void
esp_do_dma(esp_t *dev, scsi_device_t *sd)
{
@@ -797,7 +795,6 @@ partial:
}
}
static void
esp_report_command_complete(esp_t *dev, uint32_t status)
{
@@ -813,7 +810,7 @@ esp_report_command_complete(esp_t *dev, uint32_t status)
static void
esp_command_complete(void *priv, uint32_t status)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
esp_report_command_complete(dev, status);
}
@@ -821,7 +818,7 @@ esp_command_complete(void *priv, uint32_t status)
static void
esp_pci_command_complete(void *priv, uint32_t status)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
esp_command_complete(dev, status);
dev->dma_regs[DMA_WBC] = 0;
@@ -845,7 +842,7 @@ esp_timer_on(esp_t *dev, scsi_device_t *sd, double p)
static void
handle_ti(void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
scsi_device_t *sd = &scsi_devices[dev->bus][dev->id];
if (dev->dma) {
@@ -860,7 +857,7 @@ handle_ti(void *priv)
static void
handle_s_without_atn(void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
int len;
len = esp_get_cmd(dev, ESP_CMDFIFO_SZ);
@@ -880,7 +877,7 @@ handle_s_without_atn(void *priv)
static void
handle_satn(void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
int len;
len = esp_get_cmd(dev, ESP_CMDFIFO_SZ);
@@ -900,7 +897,7 @@ handle_satn(void *priv)
static void
handle_satn_stop(void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
int cmdlen;
cmdlen = esp_get_cmd(dev, 1);
@@ -1013,13 +1010,11 @@ esp_reg_read(esp_t *dev, uint32_t saddr)
default:
ret = dev->rregs[saddr];
break;
}
esp_log("Read reg %02x = %02x\n", saddr, ret);
return ret;
}
static void
esp_reg_write(esp_t *dev, uint32_t saddr, uint32_t val)
{
@@ -1066,7 +1061,7 @@ esp_reg_write(esp_t *dev, uint32_t saddr, uint32_t val)
if (dev->mca)
esp_dma_enable(dev, 0);
}
esp_log("[%04X:%08X]: ESP Command = %02x, DMA ena1 = %d, DMA ena2 = %d\n", CS, cpu_state.pc, val & (CMD_CMD|CMD_DMA), dev->dma, dev->dma_enabled);
esp_log("[%04X:%08X]: ESP Command = %02x, DMA ena1 = %d, DMA ena2 = %d\n", CS, cpu_state.pc, val & (CMD_CMD | CMD_DMA), dev->dma, dev->dma_enabled);
switch (val & CMD_CMD) {
case CMD_NOP:
break;
@@ -1153,7 +1148,6 @@ esp_reg_write(esp_t *dev, uint32_t saddr, uint32_t val)
dev->wregs[saddr] = val;
}
static void
esp_pci_dma_memory_rw(esp_t *dev, uint8_t *buf, uint32_t len, int dir)
{
@@ -1200,8 +1194,7 @@ esp_pci_dma_read(esp_t *dev, uint16_t saddr)
esp_log("ESP PCI DMA Read SCSI interrupt issued\n");
}
if (!(dev->sbac & SBAC_STATUS)) {
dev->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
DMA_STAT_DONE);
dev->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE);
esp_log("ESP PCI DMA Read done cleared\n");
}
}
@@ -1232,9 +1225,7 @@ esp_pci_dma_write(esp_t *dev, uint16_t saddr, uint32_t val)
dev->dma_regs[DMA_WBC] = dev->dma_regs[DMA_STC];
dev->dma_regs[DMA_WAC] = dev->dma_regs[DMA_SPA];
dev->dma_regs[DMA_WMAC] = dev->dma_regs[DMA_SMDLA];
dev->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT |
DMA_STAT_DONE | DMA_STAT_ABORT |
DMA_STAT_ERROR | DMA_STAT_PWDN);
dev->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT | DMA_STAT_DONE | DMA_STAT_ABORT | DMA_STAT_ERROR | DMA_STAT_PWDN);
esp_dma_enable(dev, 1);
break;
default: /* can't happen */
@@ -1302,7 +1293,7 @@ esp_io_pci_read(esp_t *dev, uint32_t addr, unsigned int size)
/* give only requested data */
ret >>= (addr & 3) * 8;
ret &= ~(~(uint64_t)0 << (8 * size));
ret &= ~(~(uint64_t) 0 << (8 * size));
esp_log("ESP PCI I/O read: addr = %02x, val = %02x\n", addr, ret);
return ret;
@@ -1329,7 +1320,7 @@ esp_io_pci_write(esp_t *dev, uint32_t addr, uint32_t val, unsigned int size)
}
shift = (4 - size) * 8;
mask = (~(uint32_t)0 << shift) >> shift;
mask = (~(uint32_t) 0 << shift) >> shift;
shift = ((4 - (addr & 3)) & 3) * 8;
val <<= shift;
@@ -1352,46 +1343,45 @@ esp_io_pci_write(esp_t *dev, uint32_t addr, uint32_t val, unsigned int size)
}
}
static void
esp_pci_io_writeb(uint16_t addr, uint8_t val, void *p)
{
esp_t *dev = (esp_t *)p;
esp_t *dev = (esp_t *) p;
esp_io_pci_write(dev, addr, val, 1);
}
static void
esp_pci_io_writew(uint16_t addr, uint16_t val, void *p)
{
esp_t *dev = (esp_t *)p;
esp_t *dev = (esp_t *) p;
esp_io_pci_write(dev, addr, val, 2);
}
static void
esp_pci_io_writel(uint16_t addr, uint32_t val, void *p)
{
esp_t *dev = (esp_t *)p;
esp_t *dev = (esp_t *) p;
esp_io_pci_write(dev, addr, val, 4);
}
static uint8_t
esp_pci_io_readb(uint16_t addr, void *p)
{
esp_t *dev = (esp_t *)p;
esp_t *dev = (esp_t *) p;
return esp_io_pci_read(dev, addr, 1);
}
static uint16_t
esp_pci_io_readw(uint16_t addr, void *p)
{
esp_t *dev = (esp_t *)p;
esp_t *dev = (esp_t *) p;
return esp_io_pci_read(dev, addr, 2);
}
static uint32_t
esp_pci_io_readl(uint16_t addr, void *p)
{
esp_t *dev = (esp_t *)p;
esp_t *dev = (esp_t *) p;
return esp_io_pci_read(dev, addr, 4);
}
@@ -1404,7 +1394,6 @@ esp_io_set(esp_t *dev, uint32_t base, uint16_t len)
esp_pci_io_writeb, esp_pci_io_writew, esp_pci_io_writel, dev);
}
static void
esp_io_remove(esp_t *dev, uint32_t base, uint16_t len)
{
@@ -1446,7 +1435,8 @@ static void
dc390_save_eeprom(esp_t *dev)
{
FILE *f = nvr_fopen(dev->nvr_path, "wb");
if (!f) return;
if (!f)
return;
fwrite(dev->eeprom.data, 1, 128, f);
fclose(f);
}
@@ -1574,7 +1564,7 @@ static void
dc390_load_eeprom(esp_t *dev)
{
ati_eeprom_t *eeprom = &dev->eeprom;
uint8_t *nvr = (uint8_t *)eeprom->data;
uint8_t *nvr = (uint8_t *) eeprom->data;
int i;
uint16_t checksum = 0;
FILE *f;
@@ -1598,9 +1588,7 @@ dc390_load_eeprom(esp_t *dev)
nvr[EE_ADAPT_SCSI_ID] = 7;
nvr[EE_MODE2] = 0x0f;
nvr[EE_TAG_CMD_NUM] = 0x04;
nvr[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT |
EE_ADAPT_OPTION_BOOT_FROM_CDROM |
EE_ADAPT_OPTION_INT13;
nvr[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT | EE_ADAPT_OPTION_BOOT_FROM_CDROM | EE_ADAPT_OPTION_INT13;
for (i = 0; i < EE_CHKSUM1; i += 2) {
checksum += ((nvr[i] & 0xff) | (nvr[i + 1] << 8));
esp_log("Checksum calc = %04x, nvr = %02x\n", checksum, nvr[i]);
@@ -1616,17 +1604,16 @@ dc390_load_eeprom(esp_t *dev)
uint8_t esp_pci_regs[256];
bar_t esp_pci_bar[2];
static uint8_t
esp_pci_read(int func, int addr, void *p)
{
esp_t *dev = (esp_t *)p;
esp_t *dev = (esp_t *) p;
//esp_log("ESP PCI: Reading register %02X\n", addr & 0xff);
// esp_log("ESP PCI: Reading register %02X\n", addr & 0xff);
switch (addr) {
case 0x00:
//esp_log("ESP PCI: Read DO line = %02x\n", dev->eeprom.out);
// esp_log("ESP PCI: Read DO line = %02x\n", dev->eeprom.out);
if (!dev->has_bios)
return 0x22;
else {
@@ -1691,19 +1678,18 @@ esp_pci_read(int func, int addr, void *p)
return esp_pci_regs[addr];
}
return(0);
return (0);
}
static void
esp_pci_write(int func, int addr, uint8_t val, void *p)
{
esp_t *dev = (esp_t *)p;
esp_t *dev = (esp_t *) p;
uint8_t valxor;
int eesk;
int eedi;
//esp_log("ESP PCI: Write value %02X to register %02X\n", val, addr);
// esp_log("ESP PCI: Write value %02X to register %02X\n", val, addr);
if ((addr >= 0x80) && (addr <= 0xFF)) {
if (addr == 0x80) {
@@ -1712,7 +1698,7 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
dc390_write_eeprom(dev, 1, eesk, eedi);
} else if (addr == 0xc0)
dc390_write_eeprom(dev, 0, 0, 0);
//esp_log("ESP PCI: Write value %02X to register %02X\n", val, addr);
// esp_log("ESP PCI: Write value %02X to register %02X\n", val, addr);
return;
}
@@ -1727,7 +1713,10 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
esp_pci_regs[addr] = val & 3;
break;
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x10:
case 0x11:
case 0x12:
case 0x13:
/* I/O Base set. */
/* First, remove the old I/O. */
esp_io_remove(dev, dev->PCIBase, 0x80);
@@ -1737,7 +1726,7 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
esp_pci_bar[0].addr &= 0xff00;
dev->PCIBase = esp_pci_bar[0].addr;
/* Log the new base. */
//esp_log("ESP PCI: New I/O base is %04X\n" , dev->PCIBase);
// esp_log("ESP PCI: New I/O base is %04X\n" , dev->PCIBase);
/* We're done, so get out of the here. */
if (esp_pci_regs[4] & PCI_COMMAND_IO) {
if (dev->PCIBase != 0) {
@@ -1746,7 +1735,10 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
}
return;
case 0x30: case 0x31: case 0x32: case 0x33:
case 0x30:
case 0x31:
case 0x32:
case 0x33:
if (!dev->has_bios)
return;
/* BIOS Base set. */
@@ -1758,7 +1750,7 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
esp_pci_bar[1].addr &= 0xfff80001;
dev->BIOSBase = esp_pci_bar[1].addr & 0xfff80000;
/* Log the new base. */
//esp_log("ESP PCI: New BIOS base is %08X\n" , dev->BIOSBase);
// esp_log("ESP PCI: New BIOS base is %08X\n" , dev->BIOSBase);
/* We're done, so get out of the here. */
if (esp_pci_bar[1].addr & 0x00000001)
esp_bios_set_addr(dev, dev->BIOSBase);
@@ -1822,13 +1814,13 @@ dc390_init(const device_t *info)
timer_add(&dev->timer, esp_callback, dev, 0);
return(dev);
return (dev);
}
static uint16_t
ncr53c90_in(uint16_t port, void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
uint16_t ret = 0;
port &= 0x1f;
@@ -1867,7 +1859,7 @@ ncr53c90_inw(uint16_t port, void *priv)
static void
ncr53c90_out(uint16_t port, uint16_t val, void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
port &= 0x1f;
@@ -1898,22 +1890,22 @@ ncr53c90_outw(uint16_t port, uint16_t val, void *priv)
static uint8_t
ncr53c90_mca_read(int port, void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
return(dev->pos_regs[port & 7]);
return (dev->pos_regs[port & 7]);
}
static void
ncr53c90_mca_write(int port, uint8_t val, void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
static const uint16_t ncrmca_iobase[] = {
0, 0x240, 0x340, 0x400, 0x420, 0x3240, 0x8240, 0xa240
};
/* MCA does not write registers below 0x0100. */
if (port < 0x0102) return;
if (port < 0x0102)
return;
/* Save the MCA register value. */
dev->pos_regs[port & 7] = val;
@@ -1958,16 +1950,14 @@ ncr53c90_mca_write(int port, uint8_t val, void *priv)
}
}
static uint8_t
ncr53c90_mca_feedb(void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
return (dev->pos_regs[2] & 0x01);
}
static void *
ncr53c90_mca_init(const device_t *info)
{
@@ -1991,13 +1981,13 @@ ncr53c90_mca_init(const device_t *info)
timer_add(&dev->timer, esp_callback, dev, 0);
return(dev);
return (dev);
}
static void
esp_close(void *priv)
{
esp_t *dev = (esp_t *)priv;
esp_t *dev = (esp_t *) priv;
if (dev) {
fifo8_destroy(&dev->fifo);
@@ -2008,9 +1998,8 @@ esp_close(void *priv)
}
}
static const device_config_t bios_enable_config[] = {
// clang-format off
// clang-format off
{
.name = "bios",
.description = "Enable BIOS",

150
src/scsi/scsi_spock.c
View File

@@ -48,15 +48,14 @@
#define SPOCK_TIME (20)
typedef enum
{
typedef enum {
SCSI_STATE_IDLE,
SCSI_STATE_SELECT,
SCSI_STATE_SEND_COMMAND,
SCSI_STATE_END_PHASE
} scsi_state_t;
#pragma pack(push,1)
#pragma pack(push, 1)
typedef struct {
uint16_t pos;
uint16_t pos1;
@@ -206,11 +205,9 @@ typedef struct {
#define IRQ_TYPE_SW_SEQ_ERROR 0xf
#define IRQ_TYPE_RESET_COMPLETE 0x10
#ifdef ENABLE_SPOCK_LOG
int spock_do_log = ENABLE_SPOCK_LOG;
static void
spock_log(const char *fmt, ...)
{
@@ -223,7 +220,7 @@ spock_log(const char *fmt, ...)
}
}
#else
#define spock_log(fmt, ...)
# define spock_log(fmt, ...)
#endif
static void
@@ -291,12 +288,15 @@ spock_add_to_period(spock_t *scsi, int TransferLength)
static void
spock_write(uint16_t port, uint8_t val, void *p)
{
spock_t *scsi = (spock_t *)p;
spock_t *scsi = (spock_t *) p;
spock_log("spock_write: port=%04x val=%02x %04x:%04x\n", port, val, CS, cpu_state.pc);
switch (port & 7) {
case 0: case 1: case 2: case 3: /*Command Interface Register*/
case 0:
case 1:
case 2:
case 3: /*Command Interface Register*/
scsi->cir_pending[port & 3] = val;
if (port & 2)
scsi->cir_status |= 2;
@@ -326,7 +326,7 @@ spock_write(uint16_t port, uint8_t val, void *p)
static void
spock_writew(uint16_t port, uint16_t val, void *p)
{
spock_t *scsi = (spock_t *)p;
spock_t *scsi = (spock_t *) p;
switch (port & 7) {
case 0: /*Command Interface Register*/
@@ -344,15 +344,17 @@ spock_writew(uint16_t port, uint16_t val, void *p)
spock_log("spock_writew: port=%04x val=%04x\n", port, val);
}
static uint8_t
spock_read(uint16_t port, void *p)
{
spock_t *scsi = (spock_t *)p;
spock_t *scsi = (spock_t *) p;
uint8_t temp = 0xff;
switch (port & 7) {
case 0: case 1: case 2: case 3: /*Command Interface Register*/
case 0:
case 1:
case 2:
case 3: /*Command Interface Register*/
temp = scsi->cir_pending[port & 3];
break;
@@ -371,8 +373,7 @@ spock_read(uint16_t port, void *p)
if (scsi->cir_status == 0) {
spock_log("Status Cmd Empty\n");
temp |= STATUS_CMD_EMPTY;
}
else if (scsi->cir_status == 3) {
} else if (scsi->cir_status == 3) {
spock_log("Status Cmd Full\n");
temp |= STATUS_CMD_FULL;
}
@@ -386,7 +387,7 @@ spock_read(uint16_t port, void *p)
static uint16_t
spock_readw(uint16_t port, void *p)
{
spock_t *scsi = (spock_t *)p;
spock_t *scsi = (spock_t *) p;
uint16_t temp = 0xffff;
switch (port & 7) {
@@ -405,7 +406,7 @@ spock_readw(uint16_t port, void *p)
static void
spock_rd_sge(spock_t *scsi, uint32_t Address, SGE *SG)
{
dma_bm_read(Address, (uint8_t *)SG, sizeof(SGE), 2);
dma_bm_read(Address, (uint8_t *) SG, sizeof(SGE), 2);
spock_add_to_period(scsi, sizeof(SGE));
}
@@ -418,7 +419,7 @@ spock_get_len(spock_t *scsi, scb_t *scb)
scsi->data_len, scsi->data_ptr);
if (!scsi->data_len)
return(0);
return (0);
if (scb->enable & ENABLE_PT) {
for (i = 0; i < scsi->data_len; i += 8) {
@@ -426,9 +427,9 @@ spock_get_len(spock_t *scsi, scb_t *scb)
DataToTransfer += scb->sge.sys_buf_byte_count;
}
return(DataToTransfer);
return (DataToTransfer);
} else {
return(scsi->data_len);
return (scsi->data_len);
}
}
@@ -527,7 +528,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
scsi->dev_id[c].phys_id = c;
scsi->dev_id[c].lun_id = 0;
}
for (; c < (SCSI_ID_MAX-1); c++)
for (; c < (SCSI_ID_MAX - 1); c++)
scsi->dev_id[c].phys_id = -1;
scsi->in_reset = 0;
@@ -543,8 +544,7 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
spock_log("SCB State = %d\n", scsi->scb_state);
do
{
do {
old_scb_state = scsi->scb_state;
switch (scsi->scb_state) {
@@ -559,20 +559,20 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
spock_log("Start failed, SCB ID = %d\n", scsi->scb_id);
spock_set_irq(scsi, scsi->scb_id, IRQ_TYPE_COMMAND_FAIL);
scsi->scb_state = 0;
dma_bm_write(scb->term_status_block_addr + 0x7*2, (uint8_t *)&term_stat_block_addr7, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0x8*2, (uint8_t *)&term_stat_block_addr8, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0x7 * 2, (uint8_t *) &term_stat_block_addr7, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0x8 * 2, (uint8_t *) &term_stat_block_addr8, 2, 2);
break;
}
dma_bm_read(scsi->scb_addr, (uint8_t *)&scb->command, 2, 2);
dma_bm_read(scsi->scb_addr + 2, (uint8_t *)&scb->enable, 2, 2);
dma_bm_read(scsi->scb_addr + 4, (uint8_t *)&scb->lba_addr, 4, 2);
dma_bm_read(scsi->scb_addr + 8, (uint8_t *)&scb->sge.sys_buf_addr, 4, 2);
dma_bm_read(scsi->scb_addr + 12, (uint8_t *)&scb->sge.sys_buf_byte_count, 4, 2);
dma_bm_read(scsi->scb_addr + 16, (uint8_t *)&scb->term_status_block_addr, 4, 2);
dma_bm_read(scsi->scb_addr + 20, (uint8_t *)&scb->scb_chain_addr, 4, 2);
dma_bm_read(scsi->scb_addr + 24, (uint8_t *)&scb->block_count, 2, 2);
dma_bm_read(scsi->scb_addr + 26, (uint8_t *)&scb->block_length, 2, 2);
dma_bm_read(scsi->scb_addr, (uint8_t *) &scb->command, 2, 2);
dma_bm_read(scsi->scb_addr + 2, (uint8_t *) &scb->enable, 2, 2);
dma_bm_read(scsi->scb_addr + 4, (uint8_t *) &scb->lba_addr, 4, 2);
dma_bm_read(scsi->scb_addr + 8, (uint8_t *) &scb->sge.sys_buf_addr, 4, 2);
dma_bm_read(scsi->scb_addr + 12, (uint8_t *) &scb->sge.sys_buf_byte_count, 4, 2);
dma_bm_read(scsi->scb_addr + 16, (uint8_t *) &scb->term_status_block_addr, 4, 2);
dma_bm_read(scsi->scb_addr + 20, (uint8_t *) &scb->scb_chain_addr, 4, 2);
dma_bm_read(scsi->scb_addr + 24, (uint8_t *) &scb->block_count, 2, 2);
dma_bm_read(scsi->scb_addr + 26, (uint8_t *) &scb->block_length, 2, 2);
spock_log("SCB : \n"
" Command = %04x\n"
@@ -607,16 +607,16 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
get_complete_stat->cache_info_status = 0;
get_complete_stat->scb_addr = scsi->scb_addr;
dma_bm_write(scb->sge.sys_buf_addr, (uint8_t *)&get_complete_stat->scb_status, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 2, (uint8_t *)&get_complete_stat->retry_count, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 4, (uint8_t *)&get_complete_stat->residual_byte_count, 4, 2);
dma_bm_write(scb->sge.sys_buf_addr + 8, (uint8_t *)&get_complete_stat->sg_list_element_addr, 4, 2);
dma_bm_write(scb->sge.sys_buf_addr + 12, (uint8_t *)&get_complete_stat->device_dep_status_len, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 14, (uint8_t *)&get_complete_stat->cmd_status, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 16, (uint8_t *)&get_complete_stat->error, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 18, (uint8_t *)&get_complete_stat->reserved, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 20, (uint8_t *)&get_complete_stat->cache_info_status, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 22, (uint8_t *)&get_complete_stat->scb_addr, 4, 2);
dma_bm_write(scb->sge.sys_buf_addr, (uint8_t *) &get_complete_stat->scb_status, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 2, (uint8_t *) &get_complete_stat->retry_count, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 4, (uint8_t *) &get_complete_stat->residual_byte_count, 4, 2);
dma_bm_write(scb->sge.sys_buf_addr + 8, (uint8_t *) &get_complete_stat->sg_list_element_addr, 4, 2);
dma_bm_write(scb->sge.sys_buf_addr + 12, (uint8_t *) &get_complete_stat->device_dep_status_len, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 14, (uint8_t *) &get_complete_stat->cmd_status, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 16, (uint8_t *) &get_complete_stat->error, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 18, (uint8_t *) &get_complete_stat->reserved, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 20, (uint8_t *) &get_complete_stat->cache_info_status, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 22, (uint8_t *) &get_complete_stat->scb_addr, 4, 2);
scsi->scb_state = 3;
}
break;
@@ -648,15 +648,15 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
get_pos_info->pos7 = 0;
get_pos_info->pos8 = 0;
dma_bm_write(scb->sge.sys_buf_addr, (uint8_t *)&get_pos_info->pos, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 2, (uint8_t *)&get_pos_info->pos1, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 4, (uint8_t *)&get_pos_info->pos2, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 6, (uint8_t *)&get_pos_info->pos3, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 8, (uint8_t *)&get_pos_info->pos4, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 10, (uint8_t *)&get_pos_info->pos5, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 12, (uint8_t *)&get_pos_info->pos6, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 14, (uint8_t *)&get_pos_info->pos7, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 16, (uint8_t *)&get_pos_info->pos8, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr, (uint8_t *) &get_pos_info->pos, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 2, (uint8_t *) &get_pos_info->pos1, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 4, (uint8_t *) &get_pos_info->pos2, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 6, (uint8_t *) &get_pos_info->pos3, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 8, (uint8_t *) &get_pos_info->pos4, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 10, (uint8_t *) &get_pos_info->pos5, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 12, (uint8_t *) &get_pos_info->pos6, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 14, (uint8_t *) &get_pos_info->pos7, 2, 2);
dma_bm_write(scb->sge.sys_buf_addr + 16, (uint8_t *) &get_pos_info->pos8, 2, 2);
scsi->scb_state = 3;
}
break;
@@ -812,10 +812,10 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
spock_set_irq(scsi, scsi->scb_id, IRQ_TYPE_COMMAND_FAIL);
scsi->scb_state = 0;
spock_log("Status Check Condition on device ID %d, reset = %d\n", scsi->scb_id, scsi->adapter_reset);
dma_bm_write(scb->term_status_block_addr + 0x7*2, (uint8_t *)&term_stat_block_addr7, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0x8*2, (uint8_t *)&term_stat_block_addr8, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0xb*2, (uint8_t *)&term_stat_block_addrb, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0xc*2, (uint8_t *)&term_stat_block_addrc, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0x7 * 2, (uint8_t *) &term_stat_block_addr7, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0x8 * 2, (uint8_t *) &term_stat_block_addr8, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0xb * 2, (uint8_t *) &term_stat_block_addrb, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0xc * 2, (uint8_t *) &term_stat_block_addrc, 2, 2);
}
} else {
uint16_t term_stat_block_addr7 = (0xc << 8) | 2;
@@ -823,8 +823,8 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
spock_set_irq(scsi, scsi->scb_id, IRQ_TYPE_COMMAND_FAIL);
scsi->scb_state = 0;
spock_log("Status Check Condition on device ID %d on no device, reset = %d\n", scsi->scb_id, scsi->adapter_reset);
dma_bm_write(scb->term_status_block_addr + 0x7*2, (uint8_t *)&term_stat_block_addr7, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0x8*2, (uint8_t *)&term_stat_block_addr8, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0x7 * 2, (uint8_t *) &term_stat_block_addr7, 2, 2);
dma_bm_write(scb->term_status_block_addr + 0x8 * 2, (uint8_t *) &term_stat_block_addr8, 2, 2);
}
}
break;
@@ -857,7 +857,7 @@ spock_process_scsi(spock_t *scsi, scb_t *scb)
case SCSI_STATE_SELECT:
spock_log("Selecting ID %d\n", scsi->cdb_id);
if ((scsi->cdb_id != (uint8_t)-1) && scsi_device_present(&scsi_devices[scsi->bus][scsi->cdb_id])) {
if ((scsi->cdb_id != (uint8_t) -1) && scsi_device_present(&scsi_devices[scsi->bus][scsi->cdb_id])) {
scsi->scsi_state = SCSI_STATE_SEND_COMMAND;
spock_log("Device selected at ID %i\n", scsi->cdb_id);
} else {
@@ -934,9 +934,9 @@ spock_process_scsi(spock_t *scsi, scb_t *scb)
} else {
spock_log("Normal Transfer\n");
if (sd->phase == SCSI_PHASE_DATA_IN) {
dma_bm_write(scsi->data_ptr, sd->sc->temp_buffer, MIN(sd->buffer_length, (int)scsi->data_len), 2);
dma_bm_write(scsi->data_ptr, sd->sc->temp_buffer, MIN(sd->buffer_length, (int) scsi->data_len), 2);
} else if (sd->phase == SCSI_PHASE_DATA_OUT)
dma_bm_read(scsi->data_ptr, sd->sc->temp_buffer, MIN(sd->buffer_length, (int)scsi->data_len), 2);
dma_bm_read(scsi->data_ptr, sd->sc->temp_buffer, MIN(sd->buffer_length, (int) scsi->data_len), 2);
}
scsi_device_command_phase1(sd);
@@ -961,7 +961,7 @@ static void
spock_callback(void *priv)
{
double period;
spock_t *scsi = (spock_t *)priv;
spock_t *scsi = (spock_t *) priv;
scb_t *scb = &scsi->scb;
scsi->temp_period = 0;
@@ -974,8 +974,7 @@ spock_callback(void *priv)
}
}
if (scsi->attention_wait &&
(scsi->scb_state == 0 || (scsi->attention_pending & 0xf0) == 0xe0)) {
if (scsi->attention_wait && (scsi->scb_state == 0 || (scsi->attention_pending & 0xf0) == 0xe0)) {
scsi->attention_wait--;
if (!scsi->attention_wait) {
scsi->attention = scsi->attention_pending;
@@ -1001,7 +1000,9 @@ spock_callback(void *priv)
}
break;
case 3: case 4: case 0x0f: /*Start SCB*/
case 3:
case 4:
case 0x0f: /*Start SCB*/
scsi->cmd_status = 1;
scsi->scb_addr = scsi->cir[0] | (scsi->cir[1] << 8) | (scsi->cir[2] << 16) | (scsi->cir[3] << 24);
scsi->scb_id = scsi->attention & 0x0f;
@@ -1034,7 +1035,7 @@ spock_callback(void *priv)
static void
spock_mca_write(int port, uint8_t val, void *priv)
{
spock_t *scsi = (spock_t *)priv;
spock_t *scsi = (spock_t *) priv;
if (port < 0x102)
return;
@@ -1059,7 +1060,7 @@ spock_mca_write(int port, uint8_t val, void *priv)
static uint8_t
spock_mca_read(int port, void *priv)
{
spock_t *scsi = (spock_t *)priv;
spock_t *scsi = (spock_t *) priv;
return scsi->pos_regs[port & 7];
}
@@ -1067,7 +1068,7 @@ spock_mca_read(int port, void *priv)
static uint8_t
spock_mca_feedb(void *priv)
{
spock_t *scsi = (spock_t *)priv;
spock_t *scsi = (spock_t *) priv;
return (scsi->pos_regs[2] & 0x01);
}
@@ -1075,7 +1076,7 @@ spock_mca_feedb(void *priv)
static void
spock_mca_reset(void *priv)
{
spock_t *scsi = (spock_t *)priv;
spock_t *scsi = (spock_t *) priv;
int i;
scsi->in_reset = 2;
@@ -1127,11 +1128,11 @@ spock_init(const device_t *info)
scsi->cmd_timer = SPOCK_TIME * 50;
scsi->status = STATUS_BUSY;
for (c = 0; c < (SCSI_ID_MAX-1); c++) {
for (c = 0; c < (SCSI_ID_MAX - 1); c++) {
scsi->dev_id[c].phys_id = -1;
}
scsi->dev_id[SCSI_ID_MAX-1].phys_id = scsi->adapter_id;
scsi->dev_id[SCSI_ID_MAX - 1].phys_id = scsi->adapter_id;
timer_add(&scsi->callback_timer, spock_callback, scsi, 1);
scsi->callback_timer.period = 10.0;
@@ -1143,7 +1144,7 @@ spock_init(const device_t *info)
static void
spock_close(void *p)
{
spock_t *scsi = (spock_t *)p;
spock_t *scsi = (spock_t *) p;
if (scsi) {
free(scsi);
@@ -1154,12 +1155,11 @@ spock_close(void *p)
static int
spock_available(void)
{
return rom_present(SPOCK_U68_1991_ROM) && rom_present(SPOCK_U69_1991_ROM) &&
rom_present(SPOCK_U68_1990_ROM) && rom_present(SPOCK_U69_1990_ROM);
return rom_present(SPOCK_U68_1991_ROM) && rom_present(SPOCK_U69_1991_ROM) && rom_present(SPOCK_U68_1990_ROM) && rom_present(SPOCK_U69_1990_ROM);
}
static const device_config_t spock_rom_config[] = {
// clang-format off
// clang-format off
{
.name = "bios_ver",
.description = "BIOS Version",

253
src/scsi/scsi_x54x.c
View File

@@ -47,17 +47,13 @@
#include <86box/scsi_aha154x.h>
#include <86box/scsi_x54x.h>
#define X54X_RESET_DURATION_US UINT64_C(50000)
static void x54x_cmd_callback(void *priv);
#ifdef ENABLE_X54X_LOG
int x54x_do_log = ENABLE_X54X_LOG;
static void
x54x_log(const char *fmt, ...)
{
@@ -70,10 +66,9 @@ x54x_log(const char *fmt, ...)
}
}
#else
#define x54x_log(fmt, ...)
# define x54x_log(fmt, ...)
#endif
static void
x54x_irq(x54x_t *dev, int set)
{
@@ -107,14 +102,13 @@ x54x_irq(x54x_t *dev, int set)
}
}
static void
raise_irq(x54x_t *dev, int suppress, uint8_t Interrupt)
{
if (Interrupt & (INTR_MBIF | INTR_MBOA)) {
x54x_log("%s: RaiseInterrupt(): Interrupt=%02X %s\n",
dev->name, Interrupt, (! (dev->Interrupt & INTR_HACC)) ? "Immediate" : "Pending");
if (! (dev->Interrupt & INTR_HACC)) {
dev->name, Interrupt, (!(dev->Interrupt & INTR_HACC)) ? "Immediate" : "Pending");
if (!(dev->Interrupt & INTR_HACC)) {
dev->Interrupt |= Interrupt; /* Report now. */
} else {
dev->PendingInterrupt |= Interrupt; /* Report later. */
@@ -135,7 +129,6 @@ raise_irq(x54x_t *dev, int suppress, uint8_t Interrupt)
x54x_irq(dev, 1);
}
static void
clear_irq(x54x_t *dev)
{
@@ -153,15 +146,13 @@ clear_irq(x54x_t *dev)
}
}
static void
target_check(x54x_t *dev, uint8_t id)
{
if (! scsi_device_valid(&scsi_devices[dev->bus][id]))
if (!scsi_device_valid(&scsi_devices[dev->bus][id]))
fatal("BIOS INT13 device on ID %02i has disappeared\n", id);
}
static uint8_t
completion_code(uint8_t *sense)
{
@@ -249,10 +240,9 @@ completion_code(uint8_t *sense)
break;
};
return(ret);
return (ret);
}
static uint8_t
x54x_bios_scsi_command(scsi_device_t *dev, uint8_t *cdb, uint8_t *buf, int len, uint32_t addr, int transfer_size)
{
@@ -261,12 +251,12 @@ x54x_bios_scsi_command(scsi_device_t *dev, uint8_t *cdb, uint8_t *buf, int len,
scsi_device_command_phase0(dev, cdb);
if (dev->phase == SCSI_PHASE_STATUS)
return(completion_code(scsi_device_sense(dev)));
return (completion_code(scsi_device_sense(dev)));
if (len > 0) {
if (dev->buffer_length == -1) {
fatal("Buffer length -1 when doing SCSI DMA\n");
return(0xff);
return (0xff);
}
if (dev->phase == SCSI_PHASE_DATA_IN) {
@@ -287,7 +277,6 @@ x54x_bios_scsi_command(scsi_device_t *dev, uint8_t *cdb, uint8_t *buf, int len,
return (completion_code(scsi_device_sense(dev)));
}
static uint8_t
x54x_bios_read_capacity(scsi_device_t *sd, uint8_t *buf, int transfer_size)
{
@@ -303,10 +292,9 @@ x54x_bios_read_capacity(scsi_device_t *sd, uint8_t *buf, int transfer_size)
free(cdb);
return(ret);
return (ret);
}
static uint8_t
x54x_bios_inquiry(scsi_device_t *sd, uint8_t *buf, int transfer_size)
{
@@ -323,10 +311,9 @@ x54x_bios_inquiry(scsi_device_t *sd, uint8_t *buf, int transfer_size)
free(cdb);
return(ret);
return (ret);
}
static uint8_t
x54x_bios_command_08(scsi_device_t *sd, uint8_t *buffer, int transfer_size)
{
@@ -340,23 +327,22 @@ x54x_bios_command_08(scsi_device_t *sd, uint8_t *buffer, int transfer_size)
ret = x54x_bios_read_capacity(sd, rcbuf, transfer_size);
if (ret) {
free(rcbuf);
return(ret);
return (ret);
}
memset(buffer, 0x00, 6);
for (i=0; i<4; i++)
for (i = 0; i < 4; i++)
buffer[i] = rcbuf[i];
for (i=4; i<6; i++)
for (i = 4; i < 6; i++)
buffer[i] = rcbuf[(i + 2) ^ 1];
x54x_log("BIOS Command 0x08: %02X %02X %02X %02X %02X %02X\n",
buffer[0], buffer[1], buffer[2], buffer[3], buffer[4], buffer[5]);
free(rcbuf);
return(0);
return (0);
}
static int
x54x_bios_command_15(scsi_device_t *sd, uint8_t *buffer, int transfer_size)
{
@@ -370,7 +356,7 @@ x54x_bios_command_15(scsi_device_t *sd, uint8_t *buffer, int transfer_size)
ret = x54x_bios_inquiry(sd, inqbuf, transfer_size);
if (ret) {
free(inqbuf);
return(ret);
return (ret);
}
buffer[4] = inqbuf[0];
@@ -381,7 +367,7 @@ x54x_bios_command_15(scsi_device_t *sd, uint8_t *buffer, int transfer_size)
if (ret) {
free(rcbuf);
free(inqbuf);
return(ret);
return (ret);
}
for (i = 0; i < 4; i++)
@@ -393,10 +379,9 @@ x54x_bios_command_15(scsi_device_t *sd, uint8_t *buffer, int transfer_size)
free(rcbuf);
free(inqbuf);
return(0);
return (0);
}
/* This returns the completion code. */
static uint8_t
x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
@@ -435,7 +420,7 @@ x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
dev = &scsi_devices[x54x->bus][cmd->id];
dev->buffer_length = 0;
if (! scsi_device_present(dev)) {
if (!scsi_device_present(dev)) {
x54x_log("BIOS Target ID %i has no device attached\n", cmd->id);
ret = 0x80;
} else {
@@ -443,7 +428,7 @@ x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
if ((dev->type == SCSI_REMOVABLE_CDROM) && !(x54x->flags & X54X_CDROM_BOOT)) {
x54x_log("BIOS Target ID %i is CD-ROM on unsupported BIOS\n", cmd->id);
return(0x80);
return (0x80);
} else {
dma_address = ADDR_TO_U32(cmd->dma_address);
@@ -453,7 +438,8 @@ x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
}
}
if (!ret) switch(cmd->command) {
if (!ret)
switch (cmd->command) {
case 0x00: /* Reset Disk System, in practice it's a nop */
ret = 0x00;
break;
@@ -472,7 +458,7 @@ x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
dma_bm_write(dma_address, scsi_device_sense(dev), 14, x54x->transfer_size);
}
return(0);
return (0);
break;
case 0x02: /* Read Desired Sectors to Memory */
@@ -502,7 +488,7 @@ x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
case 0x0b: /* ???? */
case 0x12: /* ???? */
case 0x13: /* ???? */
//FIXME: add a longer delay here --FvK
// FIXME: add a longer delay here --FvK
ret = 0x01;
break;
@@ -512,7 +498,7 @@ x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
case 0x0e: /* Read Sector Buffer */
case 0x0f: /* Write Sector Buffer */
case 0x14: /* Controller Diagnostic */
//FIXME: add a longer delay here --FvK
// FIXME: add a longer delay here --FvK
ret = 0x00;
break;
@@ -547,10 +533,9 @@ x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
}
x54x_log("BIOS Request %02X complete: %02X\n", cmd->command, ret);
return(ret);
return (ret);
}
static void
x54x_cmd_done(x54x_t *dev, int suppress)
{
@@ -573,14 +558,12 @@ x54x_cmd_done(x54x_t *dev, int suppress)
dev->CmdParam = 0;
}
static void
x54x_add_to_period(x54x_t *dev, int TransferLength)
{
dev->temp_period += (uint64_t) TransferLength;
}
static void
x54x_mbi_setup(x54x_t *dev, uint32_t CCBPointer, CCBU *CmdBlock,
uint8_t HostStatus, uint8_t TargetStatus, uint8_t mbcc)
@@ -597,12 +580,11 @@ x54x_mbi_setup(x54x_t *dev, uint32_t CCBPointer, CCBU *CmdBlock,
x54x_log("Mailbox in setup\n");
}
static void
x54x_ccb(x54x_t *dev)
{
Req_t *req = &dev->Req;
uint8_t bytes[4] = { 0, 0, 0, 0};
uint8_t bytes[4] = { 0, 0, 0, 0 };
/* Rewrite the CCB up to the CDB. */
x54x_log("CCB completion code and statuses rewritten (pointer %08X)\n", req->CCBPointer);
@@ -619,12 +601,11 @@ x54x_ccb(x54x_t *dev)
dev->ToRaise = 0;
}
static void
x54x_mbi(x54x_t *dev)
{
Req_t *req = &dev->Req;
// uint32_t CCBPointer = req->CCBPointer;
// uint32_t CCBPointer = req->CCBPointer;
addr24 CCBPointer;
CCBU *CmdBlock = &(req->CmdBlock);
uint8_t HostStatus = req->HostStatus;
@@ -650,19 +631,19 @@ x54x_mbi(x54x_t *dev)
x54x_log("Mailbox not found!\n");
}
x54x_log("Host Status 0x%02X, Target Status 0x%02X\n",HostStatus,TargetStatus);
x54x_log("Host Status 0x%02X, Target Status 0x%02X\n", HostStatus, TargetStatus);
if (dev->flags & X54X_MBX_24BIT) {
U32_TO_ADDR(CCBPointer, req->CCBPointer);
x54x_log("Mailbox 24-bit: Status=0x%02X, CCB at 0x%04X\n", req->MailboxCompletionCode, CCBPointer);
bytes[0] = req->MailboxCompletionCode;
memcpy(&(bytes[1]), (uint8_t *)&CCBPointer, 3);
memcpy(&(bytes[1]), (uint8_t *) &CCBPointer, 3);
dma_bm_write(Incoming, (uint8_t *) bytes, 4, dev->transfer_size);
x54x_add_to_period(dev, 4);
x54x_log("%i bytes of 24-bit mailbox written to: %08X\n", sizeof(Mailbox_t), Incoming);
} else {
x54x_log("Mailbox 32-bit: Status=0x%02X, CCB at 0x%04X\n", req->MailboxCompletionCode, CCBPointer);
dma_bm_write(Incoming, (uint8_t *)&(req->CCBPointer), 4, dev->transfer_size);
dma_bm_write(Incoming, (uint8_t *) &(req->CCBPointer), 4, dev->transfer_size);
dma_bm_read(Incoming + 4, (uint8_t *) bytes, 4, dev->transfer_size);
bytes[0] = req->HostStatus;
bytes[1] = req->TargetStatus;
@@ -681,7 +662,6 @@ x54x_mbi(x54x_t *dev)
dev->ToRaise |= INTR_MBOA;
}
static void
x54x_rd_sge(x54x_t *dev, int Is24bit, uint32_t Address, SGE32 *SG)
{
@@ -692,10 +672,10 @@ x54x_rd_sge(x54x_t *dev, int Is24bit, uint32_t Address, SGE32 *SG)
if (dev->transfer_size == 4) {
/* 32-bit device, do this to make the transfer divisible by 4 bytes. */
dma_bm_read(Address, (uint8_t *) bytes, 8, dev->transfer_size);
memcpy((uint8_t *)&SGE24, bytes, sizeof(SGE));
memcpy((uint8_t *) &SGE24, bytes, sizeof(SGE));
} else {
/* 16-bit device, special handling not needed. */
dma_bm_read(Address, (uint8_t *)&SGE24, 8, dev->transfer_size);
dma_bm_read(Address, (uint8_t *) &SGE24, 8, dev->transfer_size);
}
x54x_add_to_period(dev, sizeof(SGE));
@@ -704,12 +684,11 @@ x54x_rd_sge(x54x_t *dev, int Is24bit, uint32_t Address, SGE32 *SG)
SG->Segment = ADDR_TO_U32(SGE24.Segment);
SG->SegmentPointer = ADDR_TO_U32(SGE24.SegmentPointer);
} else {
dma_bm_read(Address, (uint8_t *)SG, sizeof(SGE32), dev->transfer_size);
dma_bm_read(Address, (uint8_t *) SG, sizeof(SGE32), dev->transfer_size);
x54x_add_to_period(dev, sizeof(SGE32));
}
}
static int
x54x_get_length(x54x_t *dev, Req_t *req, int Is24bit)
{
@@ -730,29 +709,26 @@ x54x_get_length(x54x_t *dev, Req_t *req, int Is24bit)
DataLength, DataPointer);
if (!DataLength)
return(0);
return (0);
if (req->CmdBlock.common.ControlByte != 0x03) {
if (req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND ||
req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND_RES) {
if (req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND || req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND_RES) {
for (i = 0; i < DataLength; i += SGEntryLength) {
x54x_rd_sge(dev, Is24bit, DataPointer + i, &SGBuffer);
DataToTransfer += SGBuffer.Segment;
}
return(DataToTransfer);
} else if (req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND ||
req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND_RES) {
return(DataLength);
return (DataToTransfer);
} else if (req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND || req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND_RES) {
return (DataLength);
} else {
return(0);
return (0);
}
} else {
return(0);
return (0);
}
}
static void
x54x_set_residue(x54x_t *dev, Req_t *req, int32_t TransferLength)
{
@@ -761,8 +737,7 @@ x54x_set_residue(x54x_t *dev, Req_t *req, int32_t TransferLength)
int32_t BufLen = scsi_devices[dev->bus][req->TargetID].buffer_length;
uint8_t bytes[4] = { 0, 0, 0, 0 };
if ((req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND_RES) ||
(req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND_RES)) {
if ((req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND_RES) || (req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND_RES)) {
if ((TransferLength > 0) && (req->CmdBlock.common.ControlByte < 0x03)) {
TransferLength -= BufLen;
@@ -773,19 +748,18 @@ x54x_set_residue(x54x_t *dev, Req_t *req, int32_t TransferLength)
if (req->Is24bit) {
U32_TO_ADDR(Residue24, Residue);
dma_bm_read(req->CCBPointer + 0x0004, (uint8_t *) bytes, 4, dev->transfer_size);
memcpy((uint8_t *) bytes, (uint8_t *)&Residue24, 3);
memcpy((uint8_t *) bytes, (uint8_t *) &Residue24, 3);
dma_bm_write(req->CCBPointer + 0x0004, (uint8_t *) bytes, 4, dev->transfer_size);
x54x_add_to_period(dev, 3);
x54x_log("24-bit Residual data length for reading: %d\n", Residue);
} else {
dma_bm_write(req->CCBPointer + 0x0004, (uint8_t *)&Residue, 4, dev->transfer_size);
dma_bm_write(req->CCBPointer + 0x0004, (uint8_t *) &Residue, 4, dev->transfer_size);
x54x_add_to_period(dev, 4);
x54x_log("32-bit Residual data length for reading: %d\n", Residue);
}
}
}
static void
x54x_buf_dma_transfer(x54x_t *dev, Req_t *req, int Is24bit, int TransferLength, int dir)
{
@@ -810,8 +784,7 @@ x54x_buf_dma_transfer(x54x_t *dev, Req_t *req, int Is24bit, int TransferLength,
dir ? "write" : "read", BufLen, DataLength, DataPointer);
if ((req->CmdBlock.common.ControlByte != 0x03) && TransferLength && BufLen) {
if ((req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND) ||
(req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND_RES)) {
if ((req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND) || (req->CmdBlock.common.Opcode == SCATTER_GATHER_COMMAND_RES)) {
/* If the control byte is 0x00, it means that the transfer direction is set up by the SCSI command without
checking its length, so do this procedure for both no read/write commands. */
@@ -825,12 +798,10 @@ x54x_buf_dma_transfer(x54x_t *dev, Req_t *req, int Is24bit, int TransferLength,
if (read_from_host && DataToTransfer) {
x54x_log("Reading S/G segment %i: length %i, pointer %08X\n", i, DataToTransfer, Address);
dma_bm_read(Address, &(scsi_devices[dev->bus][req->TargetID].sc->temp_buffer[sg_pos]), DataToTransfer, dev->transfer_size);
}
else if (write_to_host && DataToTransfer) {
} else if (write_to_host && DataToTransfer) {
x54x_log("Writing S/G segment %i: length %i, pointer %08X\n", i, DataToTransfer, Address);
dma_bm_write(Address, &(scsi_devices[dev->bus][req->TargetID].sc->temp_buffer[sg_pos]), DataToTransfer, dev->transfer_size);
}
else
} else
x54x_log("No action on S/G segment %i: length %i, pointer %08X\n", i, DataToTransfer, Address);
sg_pos += SGBuffer.Segment;
@@ -842,8 +813,7 @@ x54x_buf_dma_transfer(x54x_t *dev, Req_t *req, int Is24bit, int TransferLength,
x54x_log("After S/G segment done: %i, %i\n", sg_pos, BufLen);
}
}
} else if ((req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND) ||
(req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND_RES)) {
} else if ((req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND) || (req->CmdBlock.common.Opcode == SCSI_INITIATOR_COMMAND_RES)) {
Address = DataPointer;
if ((DataLength > 0) && (BufLen > 0) && (req->CmdBlock.common.ControlByte < 0x03)) {
@@ -856,7 +826,6 @@ x54x_buf_dma_transfer(x54x_t *dev, Req_t *req, int Is24bit, int TransferLength,
}
}
static uint8_t
ConvertSenseLength(uint8_t RequestSenseLength)
{
@@ -869,10 +838,9 @@ ConvertSenseLength(uint8_t RequestSenseLength)
x54x_log("Request Sense length %i\n", RequestSenseLength);
return(RequestSenseLength);
return (RequestSenseLength);
}
uint32_t
SenseBufferPointer(Req_t *req)
{
@@ -884,10 +852,9 @@ SenseBufferPointer(Req_t *req)
SenseBufferAddress = req->CmdBlock.new.SensePointer;
}
return(SenseBufferAddress);
return (SenseBufferAddress);
}
static void
SenseBufferFree(x54x_t *dev, Req_t *req, int Copy)
{
@@ -916,7 +883,6 @@ SenseBufferFree(x54x_t *dev, Req_t *req, int Copy)
}
}
static void
x54x_scsi_cmd(x54x_t *dev)
{
@@ -938,7 +904,7 @@ x54x_scsi_cmd(x54x_t *dev)
x54x_log("SCSI command being executed on ID %i, LUN %i\n", req->TargetID, req->LUN);
x54x_log("SCSI CDB[0]=0x%02X\n", req->CmdBlock.common.Cdb[0]);
for (i=1; i<req->CmdBlock.common.CdbLength; i++)
for (i = 1; i < req->CmdBlock.common.CdbLength; i++)
x54x_log("SCSI CDB[%i]=%i\n", i, req->CmdBlock.common.Cdb[i]);
memset(dev->temp_cdb, 0x00, target_cdb_len);
@@ -968,7 +934,6 @@ x54x_scsi_cmd(x54x_t *dev)
x54x_log("scsi_devices[%02i][%02i].Status = %02X\n", dev->bus, req->TargetID, sd->status);
}
static void
x54x_scsi_cmd_phase1(x54x_t *dev)
{
@@ -995,7 +960,6 @@ x54x_scsi_cmd_phase1(x54x_t *dev)
x54x_log("scsi_devices[%02xi][%02i].Status = %02X\n", x54x->bus, req->TargetID, sd->status);
}
static void
x54x_request_sense(x54x_t *dev)
{
@@ -1036,7 +1000,6 @@ x54x_request_sense(x54x_t *dev)
x54x_log("scsi_devices[%02i][%02i].Status = %02X\n", dev->bus, req->TargetID, sd->status);
}
static void
x54x_mbo_free(x54x_t *dev)
{
@@ -1049,7 +1012,6 @@ x54x_mbo_free(x54x_t *dev)
dma_bm_write(dev->Outgoing + CodeOffset, &CmdStatus, 1, dev->transfer_size);
}
static void
x54x_notify(x54x_t *dev)
{
@@ -1070,7 +1032,6 @@ x54x_notify(x54x_t *dev)
scsi_device_identify(sd, SCSI_LUN_USE_CDB);
}
static void
x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, Mailbox32_t *Mailbox32)
{
@@ -1079,7 +1040,7 @@ x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, Mailbox32_t *Mailbox32)
scsi_device_t *sd;
/* Fetch data from the Command Control Block. */
dma_bm_read(CCBPointer, (uint8_t *)&req->CmdBlock, sizeof(CCB32), dev->transfer_size);
dma_bm_read(CCBPointer, (uint8_t *) &req->CmdBlock, sizeof(CCB32), dev->transfer_size);
x54x_add_to_period(dev, sizeof(CCB32));
req->Is24bit = !!(dev->flags & X54X_MBX_24BIT);
@@ -1091,7 +1052,7 @@ x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, Mailbox32_t *Mailbox32)
sd = &scsi_devices[dev->bus][id];
lun = req->LUN;
if ((id > dev->max_id) || (lun > 7)) {
x54x_log("SCSI Target ID %i or LUN %i is not valid\n",id,lun);
x54x_log("SCSI Target ID %i or LUN %i is not valid\n", id, lun);
x54x_mbi_setup(dev, CCBPointer, &req->CmdBlock,
CCB_SELECTION_TIMEOUT, SCSI_STATUS_OK, MBI_ERROR);
dev->callback_sub_phase = 4;
@@ -1103,7 +1064,7 @@ x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, Mailbox32_t *Mailbox32)
sd->status = SCSI_STATUS_OK;
if (!scsi_device_present(sd) || (lun > 0)) {
x54x_log("SCSI Target ID %i and LUN %i have no device attached\n",id,lun);
x54x_log("SCSI Target ID %i and LUN %i have no device attached\n", id, lun);
x54x_mbi_setup(dev, CCBPointer, &req->CmdBlock,
CCB_SELECTION_TIMEOUT, SCSI_STATUS_OK, MBI_ERROR);
dev->callback_sub_phase = 4;
@@ -1134,14 +1095,13 @@ x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, Mailbox32_t *Mailbox32)
}
}
static void
x54x_req_abort(x54x_t *dev, uint32_t CCBPointer)
{
CCBU CmdBlock;
/* Fetch data from the Command Control Block. */
dma_bm_read(CCBPointer, (uint8_t *)&CmdBlock, sizeof(CCB32), dev->transfer_size);
dma_bm_read(CCBPointer, (uint8_t *) &CmdBlock, sizeof(CCB32), dev->transfer_size);
x54x_add_to_period(dev, sizeof(CCB32));
x54x_mbi_setup(dev, CCBPointer, &CmdBlock,
@@ -1149,7 +1109,6 @@ x54x_req_abort(x54x_t *dev, uint32_t CCBPointer)
dev->callback_sub_phase = 4;
}
static uint32_t
x54x_mbo(x54x_t *dev, Mailbox32_t *Mailbox32)
{
@@ -1169,7 +1128,7 @@ x54x_mbo(x54x_t *dev, Mailbox32_t *Mailbox32)
if (dev->flags & X54X_MBX_24BIT) {
Outgoing = Addr + (Cur * sizeof(Mailbox_t));
dma_bm_read(Outgoing, (uint8_t *)&MailboxOut, sizeof(Mailbox_t), dev->transfer_size);
dma_bm_read(Outgoing, (uint8_t *) &MailboxOut, sizeof(Mailbox_t), dev->transfer_size);
x54x_add_to_period(dev, sizeof(Mailbox_t));
ccbp = *(uint32_t *) &MailboxOut;
@@ -1178,14 +1137,13 @@ x54x_mbo(x54x_t *dev, Mailbox32_t *Mailbox32)
} else {
Outgoing = Addr + (Cur * sizeof(Mailbox32_t));
dma_bm_read(Outgoing, (uint8_t *)Mailbox32, sizeof(Mailbox32_t), dev->transfer_size);
dma_bm_read(Outgoing, (uint8_t *) Mailbox32, sizeof(Mailbox32_t), dev->transfer_size);
x54x_add_to_period(dev, sizeof(Mailbox32_t));
}
return(Outgoing);
return (Outgoing);
}
uint8_t
x54x_mbo_process(x54x_t *dev)
{
@@ -1211,13 +1169,12 @@ x54x_mbo_process(x54x_t *dev)
else
dev->MailboxReq--;
return(1);
return (1);
}
return(0);
return (0);
}
static void
x54x_do_mail(x54x_t *dev)
{
@@ -1228,7 +1185,7 @@ x54x_do_mail(x54x_t *dev)
if (dev->is_aggressive_mode) {
aggressive = dev->is_aggressive_mode(dev);
x54x_log("Processing mailboxes in %s mode...\n", aggressive ? "aggressive" : "strict");
}/* else {
} /* else {
x54x_log("Defaulting to process mailboxes in %s mode...\n", aggressive ? "aggressive" : "strict");
}*/
@@ -1252,11 +1209,9 @@ x54x_do_mail(x54x_t *dev)
}
}
static void
x54x_cmd_done(x54x_t *dev, int suppress);
static void
x54x_cmd_callback(void *priv)
{
@@ -1326,11 +1281,10 @@ x54x_cmd_callback(void *priv)
// x54x_log("Temporary period: %lf us (%" PRIi64 " periods)\n", dev->timer.period, dev->temp_period);
}
static uint8_t
x54x_in(uint16_t port, void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
uint8_t ret;
switch (port & 3) {
@@ -1344,7 +1298,7 @@ x54x_in(uint16_t port, void *priv)
if (dev->DataReplyLeft) {
dev->DataReply++;
dev->DataReplyLeft--;
if (! dev->DataReplyLeft)
if (!dev->DataReplyLeft)
x54x_cmd_done(dev, 0);
}
break;
@@ -1370,11 +1324,20 @@ x54x_in(uint16_t port, void *priv)
if (dev->flags & X54X_INT_GEOM_WRITABLE)
ret = dev->Geometry;
else {
switch(dev->Geometry) {
case 0: default: ret = 'A'; break;
case 1: ret = 'D'; break;
case 2: ret = 'A'; break;
case 3: ret = 'P'; break;
switch (dev->Geometry) {
case 0:
default:
ret = 'A';
break;
case 1:
ret = 'D';
break;
case 2:
ret = 'A';
break;
case 3:
ret = 'P';
break;
}
ret ^= 1;
dev->Geometry++;
@@ -1391,54 +1354,47 @@ x54x_in(uint16_t port, void *priv)
x54x_log("x54x_in(): %04X, %02X\n", port, ret);
#endif
return(ret);
return (ret);
}
static uint16_t
x54x_inw(uint16_t port, void *priv)
{
return((uint16_t) x54x_in(port, priv));
return ((uint16_t) x54x_in(port, priv));
}
static uint32_t
x54x_inl(uint16_t port, void *priv)
{
return((uint32_t) x54x_in(port, priv));
return ((uint32_t) x54x_in(port, priv));
}
static uint8_t
x54x_readb(uint32_t port, void *priv)
{
return(x54x_in(port & 3, priv));
return (x54x_in(port & 3, priv));
}
static uint16_t
x54x_readw(uint32_t port, void *priv)
{
return(x54x_inw(port & 3, priv));
return (x54x_inw(port & 3, priv));
}
static uint32_t
x54x_readl(uint32_t port, void *priv)
{
return(x54x_inl(port & 3, priv));
return (x54x_inl(port & 3, priv));
}
static void
x54x_reset_poll(void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
dev->Status = STAT_INIT | STAT_IDLE;
}
static void
x54x_reset(x54x_t *dev)
{
@@ -1472,7 +1428,6 @@ x54x_reset(x54x_t *dev)
dev->ven_reset(dev);
}
void
x54x_reset_ctrl(x54x_t *dev, uint8_t Reset)
{
@@ -1490,12 +1445,11 @@ x54x_reset_ctrl(x54x_t *dev, uint8_t Reset)
dev->Status = STAT_INIT | STAT_IDLE;
}
static void
x54x_out(uint16_t port, uint8_t val, void *priv)
{
ReplyInquireSetupInformation *ReplyISI;
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
MailboxInit_t *mbi;
int i = 0;
BIOSCMD *cmd;
@@ -1594,7 +1548,7 @@ x54x_out(uint16_t port, uint8_t val, void *priv)
dev->ven_cmd_phase1(dev);
}
if (! dev->CmdParamLeft) {
if (!dev->CmdParamLeft) {
x54x_log("Running Operation Code 0x%02X\n", dev->Command);
switch (dev->Command) {
case CMD_NOP: /* No Operation */
@@ -1604,7 +1558,7 @@ x54x_out(uint16_t port, uint8_t val, void *priv)
case CMD_MBINIT: /* mailbox initialization */
dev->flags |= X54X_MBX_24BIT;
mbi = (MailboxInit_t *)dev->CmdBuf;
mbi = (MailboxInit_t *) dev->CmdBuf;
dev->MailboxInit = 1;
dev->MailboxCount = mbi->Count;
@@ -1623,7 +1577,7 @@ x54x_out(uint16_t port, uint8_t val, void *priv)
break;
case CMD_BIOSCMD: /* execute BIOS */
cmd = (BIOSCMD *)dev->CmdBuf;
cmd = (BIOSCMD *) dev->CmdBuf;
if (!(dev->flags & X54X_LBA_BIOS)) {
/* 1640 uses LBA. */
cyl = ((cmd->u.chs.cyl & 0xff) << 8) | ((cmd->u.chs.cyl >> 8) & 0xff);
@@ -1692,11 +1646,12 @@ x54x_out(uint16_t port, uint8_t val, void *priv)
if (dev->ven_get_host_id)
host_id = dev->ven_get_host_id(dev);
for (i=0; i<8; i++) {
for (i = 0; i < 8; i++) {
dev->DataBuf[i] = 0x00;
/* Skip the HA .. */
if (i == host_id) continue;
if (i == host_id)
continue;
/* TODO: Query device for LUN's. */
if (scsi_device_present(&scsi_devices[dev->bus][i]))
@@ -1717,9 +1672,9 @@ x54x_out(uint16_t port, uint8_t val, void *priv)
irq = dev->Irq;
if (irq >= 9)
dev->DataBuf[1]=(1<<(irq-9));
dev->DataBuf[1] = (1 << (irq - 9));
else
dev->DataBuf[1]=0;
dev->DataBuf[1] = 0;
if (dev->ven_get_host_id)
dev->DataBuf[2] = dev->ven_get_host_id(dev);
else
@@ -1729,7 +1684,7 @@ x54x_out(uint16_t port, uint8_t val, void *priv)
break;
case CMD_RETSETUP: /* return Setup */
ReplyISI = (ReplyInquireSetupInformation *)dev->DataBuf;
ReplyISI = (ReplyInquireSetupInformation *) dev->DataBuf;
memset(ReplyISI, 0x00, sizeof(ReplyInquireSetupInformation));
ReplyISI->uBusTransferRate = dev->ATBusSpeed;
@@ -1805,42 +1760,36 @@ x54x_out(uint16_t port, uint8_t val, void *priv)
}
}
static void
x54x_outw(uint16_t port, uint16_t val, void *priv)
{
x54x_out(port, val & 0xFF, priv);
}
static void
x54x_outl(uint16_t port, uint32_t val, void *priv)
{
x54x_out(port, val & 0xFF, priv);
}
static void
x54x_writeb(uint32_t port, uint8_t val, void *priv)
{
x54x_out(port & 3, val, priv);
}
static void
x54x_writew(uint32_t port, uint16_t val, void *priv)
{
x54x_outw(port & 3, val, priv);
}
static void
x54x_writel(uint32_t port, uint32_t val, void *priv)
{
x54x_outl(port & 3, val, priv);
}
static int
x54x_is_32bit(x54x_t *dev)
{
@@ -1854,7 +1803,6 @@ x54x_is_32bit(x54x_t *dev)
return bit32;
}
void
x54x_io_set(x54x_t *dev, uint32_t base, uint8_t len)
{
@@ -1871,7 +1819,6 @@ x54x_io_set(x54x_t *dev, uint32_t base, uint8_t len)
}
}
void
x54x_io_remove(x54x_t *dev, uint32_t base, uint8_t len)
{
@@ -1888,7 +1835,6 @@ x54x_io_remove(x54x_t *dev, uint32_t base, uint8_t len)
}
}
void
x54x_mem_init(x54x_t *dev, uint32_t addr)
{
@@ -1905,28 +1851,24 @@ x54x_mem_init(x54x_t *dev, uint32_t addr)
}
}
void
x54x_mem_enable(x54x_t *dev)
{
mem_mapping_enable(&dev->mmio_mapping);
}
void
x54x_mem_set_addr(x54x_t *dev, uint32_t base)
{
mem_mapping_set_addr(&dev->mmio_mapping, base, 0x20);
}
void
x54x_mem_disable(x54x_t *dev)
{
mem_mapping_disable(&dev->mmio_mapping);
}
/* General initialization routine for all boards. */
void *
x54x_init(const device_t *info)
@@ -1935,7 +1877,8 @@ x54x_init(const device_t *info)
/* Allocate control block and set up basic stuff. */
dev = malloc(sizeof(x54x_t));
if (dev == NULL) return(dev);
if (dev == NULL)
return (dev);
memset(dev, 0x00, sizeof(x54x_t));
dev->type = info->local;
@@ -1952,14 +1895,13 @@ x54x_init(const device_t *info)
else
dev->transfer_size = 2;
return(dev);
return (dev);
}
void
x54x_close(void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
if (dev) {
/* Tell the timer to terminate. */
@@ -1983,11 +1925,10 @@ x54x_close(void *priv)
}
}
void
x54x_device_reset(void *priv)
{
x54x_t *dev = (x54x_t *)priv;
x54x_t *dev = (x54x_t *) priv;
x54x_reset_ctrl(dev, 1);