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clang-format in src/sio/

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This commit is contained in:
Jasmine Iwanek
2022-09-18 17:17:00 -04:00
parent 645732b7bf
commit 99893d1175
24 changed files with 4626 additions and 4804 deletions
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22
src/sio/sio_82091aa.c
View File

@@ -34,16 +34,14 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t cur_reg, has_ide,
regs[81];
uint16_t base_address;
fdc_t * fdc;
serial_t * uart[2];
fdc_t *fdc;
serial_t *uart[2];
} i82091aa_t;
static void
fdc_handler(i82091aa_t *dev)
{
@@ -52,7 +50,6 @@ fdc_handler(i82091aa_t *dev)
fdc_set_base(dev->fdc, (dev->regs[0x10] & 0x02) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
static void
lpt1_handler(i82091aa_t *dev)
{
@@ -81,7 +78,6 @@ lpt1_handler(i82091aa_t *dev)
lpt1_irq((dev->regs[0x20] & 0x08) ? LPT1_IRQ : LPT2_IRQ);
}
static void
serial_handler(i82091aa_t *dev, int uart)
{
@@ -121,7 +117,6 @@ serial_handler(i82091aa_t *dev, int uart)
serial_setup(dev->uart[uart], uart_port, (dev->regs[reg] & 0x10) ? COM1_IRQ : COM2_IRQ);
}
static void
ide_handler(i82091aa_t *dev)
{
@@ -134,7 +129,6 @@ ide_handler(i82091aa_t *dev)
ide_set_handlers(board);
}
static void
i82091aa_write(uint16_t port, uint8_t val, void *priv)
{
@@ -153,7 +147,7 @@ i82091aa_write(uint16_t port, uint8_t val, void *priv)
else if (dev->cur_reg >= 0x51)
return;
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x02:
*reg = (*reg & 0x78) | (val & 0x01);
break;
@@ -178,14 +172,16 @@ i82091aa_write(uint16_t port, uint8_t val, void *priv)
case 0x21:
*reg = (val & 0x2f);
break;
case 0x30: case 0x40:
case 0x30:
case 0x40:
*reg = (val & 0x9f);
if (valxor & 0x1f)
serial_handler(dev, uart);
if (valxor & 0x80)
serial_set_clock_src(dev->uart[uart], (val & 0x80) ? 2000000.0 : (24000000.0 / 13.0));
break;
case 0x31: case 0x41:
case 0x31:
case 0x41:
*reg = (val & 0x1f);
if ((valxor & 0x04) && (val & 0x04))
serial_reset_port(dev->uart[uart]);
@@ -198,7 +194,6 @@ i82091aa_write(uint16_t port, uint8_t val, void *priv)
}
}
uint8_t
i82091aa_read(uint16_t port, void *priv)
{
@@ -215,7 +210,6 @@ i82091aa_read(uint16_t port, void *priv)
return ret;
}
void
i82091aa_reset(i82091aa_t *dev)
{
@@ -239,7 +233,6 @@ i82091aa_reset(i82091aa_t *dev)
ide_handler(dev);
}
static void
i82091aa_close(void *priv)
{
@@ -248,7 +241,6 @@ i82091aa_close(void *priv)
free(dev);
}
static void *
i82091aa_init(const device_t *info)
{

20
src/sio/sio_acc3221.c
View File

@@ -32,15 +32,13 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct acc3221_t
{
typedef struct acc3221_t {
int reg_idx;
uint8_t regs[256];
fdc_t * fdc;
serial_t * uart[2];
fdc_t *fdc;
serial_t *uart[2];
} acc3221_t;
/* Configuration Register Index, BE (R/W):
Bit Function
7 PIRQ 5 polarity.
@@ -300,7 +298,6 @@ typedef struct acc3221_t
Note: Bits 6-4 are reserved in 3221-SP. */
#define REG_FE_IDE_DISABLE (1 << 1)
static void
acc3221_lpt_handle(acc3221_t *dev)
{
@@ -310,7 +307,6 @@ acc3221_lpt_handle(acc3221_t *dev)
lpt1_init(dev->regs[0xbf] << 2);
}
static void
acc3221_serial1_handler(acc3221_t *dev)
{
@@ -328,7 +324,6 @@ acc3221_serial1_handler(acc3221_t *dev)
}
}
static void
acc3221_serial2_handler(acc3221_t *dev)
{
@@ -348,11 +343,10 @@ acc3221_serial2_handler(acc3221_t *dev)
}
}
static void
acc3221_write(uint16_t addr, uint8_t val, void *p)
{
acc3221_t *dev = (acc3221_t *)p;
acc3221_t *dev = (acc3221_t *) p;
uint8_t old;
if (!(addr & 1))
@@ -415,11 +409,10 @@ acc3221_write(uint16_t addr, uint8_t val, void *p)
}
}
static uint8_t
acc3221_read(uint16_t addr, void *p)
{
acc3221_t *dev = (acc3221_t *)p;
acc3221_t *dev = (acc3221_t *) p;
if (!(addr & 1))
return dev->reg_idx;
@@ -430,7 +423,6 @@ acc3221_read(uint16_t addr, void *p)
return dev->regs[dev->reg_idx];
}
static void
acc3221_reset(acc3221_t *dev)
{
@@ -455,7 +447,6 @@ acc3221_close(void *priv)
free(dev);
}
static void *
acc3221_init(const device_t *info)
{
@@ -474,7 +465,6 @@ acc3221_init(const device_t *info)
return dev;
}
const device_t acc3221_device = {
.name = "ACC 3221-SP Super I/O",
.internal_name = "acc3221",

44
src/sio/sio_ali5123.c
View File

@@ -34,10 +34,8 @@
#include "cpu.h"
#include <86box/sio.h>
#define AB_RST 0x80
typedef struct {
uint8_t chip_id, is_apm,
tries,
@@ -49,11 +47,9 @@ typedef struct {
serial_t *uart[3];
} ali5123_t;
static void ali5123_write(uint16_t port, uint8_t val, void *priv);
static uint8_t ali5123_read(uint16_t port, void *priv);
static uint16_t
make_port(ali5123_t *dev, uint8_t ld)
{
@@ -65,7 +61,6 @@ make_port(ali5123_t *dev, uint8_t ld)
return p;
}
static void
ali5123_fdc_handler(ali5123_t *dev)
{
@@ -81,7 +76,6 @@ ali5123_fdc_handler(ali5123_t *dev)
}
}
static void
ali5123_lpt_handler(ali5123_t *dev)
{
@@ -102,7 +96,6 @@ ali5123_lpt_handler(ali5123_t *dev)
lpt1_irq(lpt_irq);
}
static void
ali5123_serial_handler(ali5123_t *dev, int uart)
{
@@ -126,13 +119,13 @@ ali5123_serial_handler(ali5123_t *dev, int uart)
case 0x04:
serial_set_clock_src(dev->uart[uart], 8000000.0);
break;
case 0x01: case 0x05:
case 0x01:
case 0x05:
serial_set_clock_src(dev->uart[uart], 2000000.0);
break;
}
}
static void
ali5123_reset(ali5123_t *dev)
{
@@ -208,7 +201,6 @@ ali5123_reset(ali5123_t *dev)
dev->locked = 0;
}
static void
ali5123_write(uint16_t port, uint8_t val, void *priv)
{
@@ -218,8 +210,7 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
uint8_t cur_ld;
if (index) {
if (((val == 0x51) && (!dev->tries) && (!dev->locked)) ||
((val == 0x23) && (dev->tries) && (!dev->locked))) {
if (((val == 0x51) && (!dev->tries) && (!dev->locked)) || ((val == 0x23) && (dev->tries) && (!dev->locked))) {
if (dev->tries) {
dev->locked = 1;
fdc_3f1_enable(dev->fdc, 0);
@@ -254,9 +245,14 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
/* Block writes to some logical devices. */
if (dev->regs[7] > 0x0c)
return;
else switch (dev->regs[7]) {
case 0x01: case 0x02: case 0x06: case 0x08:
case 0x09: case 0x0a:
else
switch (dev->regs[7]) {
case 0x01:
case 0x02:
case 0x06:
case 0x08:
case 0x09:
case 0x0a:
return;
}
dev->ld_regs[dev->regs[7]][dev->cur_reg] = val | keep;
@@ -266,7 +262,7 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
}
if (dev->cur_reg < 48) {
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x02:
if (val & 0x01)
ali5123_reset(dev);
@@ -294,10 +290,10 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
cur_ld = 0x0b;
else if ((dev->regs[7] == 0x0b) && (dev->regs[0x2d] & 0x20))
cur_ld = 5;
switch(cur_ld) {
switch (cur_ld) {
case 0:
/* FDD */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -336,7 +332,7 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
break;
case 3:
/* Parallel port */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -350,7 +346,7 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
break;
case 4:
/* Serial port 1 */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -365,7 +361,7 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
break;
case 5:
/* Serial port 2 - HP like module */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -380,7 +376,7 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
break;
case 0x0b:
/* Serial port 3 */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -396,7 +392,6 @@ ali5123_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
ali5123_read(uint16_t port, void *priv)
{
@@ -428,7 +423,6 @@ ali5123_read(uint16_t port, void *priv)
return ret;
}
static void
ali5123_close(void *priv)
{
@@ -437,7 +431,6 @@ ali5123_close(void *priv)
free(dev);
}
static void *
ali5123_init(const device_t *info)
{
@@ -462,7 +455,6 @@ ali5123_init(const device_t *info)
return dev;
}
const device_t ali5123_device = {
.name = "ALi M5123/M1543C Super I/O",
.internal_name = "ali5123",

6
src/sio/sio_detect.c
View File

@@ -27,12 +27,10 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t regs[2];
} sio_detect_t;
static void
sio_detect_write(uint16_t port, uint8_t val, void *priv)
{
@@ -45,7 +43,6 @@ sio_detect_write(uint16_t port, uint8_t val, void *priv)
return;
}
static uint8_t
sio_detect_read(uint16_t port, void *priv)
{
@@ -56,7 +53,6 @@ sio_detect_read(uint16_t port, void *priv)
return 0xff /*dev->regs[port & 1]*/;
}
static void
sio_detect_close(void *priv)
{
@@ -65,7 +61,6 @@ sio_detect_close(void *priv)
free(dev);
}
static void *
sio_detect_init(const device_t *info)
{
@@ -106,7 +101,6 @@ sio_detect_init(const device_t *info)
return dev;
}
const device_t sio_detect_device = {
.name = "Super I/O Detection Helper",
.internal_name = "sio_detect",

67
src/sio/sio_f82c710.c
View File

@@ -43,9 +43,7 @@
#include <86box/nvr.h>
#include <86box/sio.h>
typedef struct upc_t
{
typedef struct upc_t {
uint32_t local;
int configuration_state; /* state of algorithm to enter configuration mode */
int configuration_mode;
@@ -56,13 +54,12 @@ typedef struct upc_t
/* these regs are not affected by reset */
uint8_t regs[15]; /* there are 16 indexes, but there is no need to store the last one which is: R = cri_addr / 4, W = exit config mode */
fdc_t * fdc;
nvr_t * nvr;
void * gameport;
serial_t * uart[2];
fdc_t *fdc;
nvr_t *nvr;
void *gameport;
serial_t *uart[2];
} upc_t;
static void
f82c710_update_ports(upc_t *dev, int set)
{
@@ -103,7 +100,6 @@ f82c710_update_ports(upc_t *dev, int set)
fdc_set_base(dev->fdc, FDC_PRIMARY_ADDR);
}
static void
f82c606_update_ports(upc_t *dev, int set)
{
@@ -126,27 +122,51 @@ f82c606_update_ports(upc_t *dev, int set)
return;
switch (dev->regs[8] & 0xc0) {
case 0x40: nvr_int = 3; break;
case 0x80: uart1_int = COM2_IRQ; break;
case 0xc0: uart2_int = COM2_IRQ; break;
case 0x40:
nvr_int = 3;
break;
case 0x80:
uart1_int = COM2_IRQ;
break;
case 0xc0:
uart2_int = COM2_IRQ;
break;
}
switch (dev->regs[8] & 0x30) {
case 0x10: nvr_int = 4; break;
case 0x20: uart1_int = COM1_IRQ; break;
case 0x30: uart2_int = COM1_IRQ; break;
case 0x10:
nvr_int = 4;
break;
case 0x20:
uart1_int = COM1_IRQ;
break;
case 0x30:
uart2_int = COM1_IRQ;
break;
}
switch (dev->regs[8] & 0x0c) {
case 0x04: nvr_int = 5; break;
case 0x08: uart1_int = 5; break;
case 0x0c: lpt1_int = LPT2_IRQ; break;
case 0x04:
nvr_int = 5;
break;
case 0x08:
uart1_int = 5;
break;
case 0x0c:
lpt1_int = LPT2_IRQ;
break;
}
switch (dev->regs[8] & 0x03) {
case 0x01: nvr_int = 7; break;
case 0x02: uart2_int = 7; break;
case 0x03: lpt1_int = LPT1_IRQ; break;
case 0x01:
nvr_int = 7;
break;
case 0x02:
uart2_int = 7;
break;
case 0x03:
lpt1_int = LPT1_IRQ;
break;
}
if (dev->regs[0] & 1) {
@@ -175,7 +195,6 @@ f82c606_update_ports(upc_t *dev, int set)
pclog("RTC at %04X, IRQ %i\n", ((uint16_t) dev->regs[3]) << 2, nvr_int);
}
static uint8_t
f82c710_config_read(uint16_t port, void *priv)
{
@@ -196,7 +215,6 @@ f82c710_config_read(uint16_t port, void *priv)
return temp;
}
static void
f82c710_config_write(uint16_t port, uint8_t val, void *priv)
{
@@ -265,7 +283,6 @@ f82c710_config_write(uint16_t port, uint8_t val, void *priv)
dev->configuration_state = 0;
}
static void
f82c710_reset(void *priv)
{
@@ -306,7 +323,6 @@ f82c710_reset(void *priv)
f82c710_update_ports(dev, 1);
}
static void
f82c710_close(void *priv)
{
@@ -315,7 +331,6 @@ f82c710_close(void *priv)
free(dev);
}
static void *
f82c710_init(const device_t *info)
{

13
src/sio/sio_fdc37c669.c
View File

@@ -31,7 +31,6 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t id, tries,
regs[42];
@@ -41,17 +40,15 @@ typedef struct {
serial_t *uart[2];
} fdc37c669_t;
static int next_id = 0;
static uint16_t
make_port(fdc37c669_t *dev, uint8_t reg)
{
uint16_t p = 0;
uint16_t mask = 0;
switch(reg) {
switch (reg) {
case 0x20:
case 0x21:
case 0x22:
@@ -73,7 +70,6 @@ make_port(fdc37c669_t *dev, uint8_t reg)
return p;
}
static void
fdc37c669_write(uint16_t port, uint8_t val, void *priv)
{
@@ -115,7 +111,7 @@ fdc37c669_write(uint16_t port, uint8_t val, void *priv)
return;
}
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0:
if (!dev->id && (valxor & 8)) {
fdc_remove(dev->fdc);
@@ -223,7 +219,6 @@ fdc37c669_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
fdc37c669_read(uint16_t port, void *priv)
{
@@ -241,7 +236,6 @@ fdc37c669_read(uint16_t port, void *priv)
return ret;
}
static void
fdc37c669_reset(fdc37c669_t *dev)
{
@@ -290,7 +284,6 @@ fdc37c669_reset(fdc37c669_t *dev)
dev->rw_locked = 0;
}
static void
fdc37c669_close(void *priv)
{
@@ -301,7 +294,6 @@ fdc37c669_close(void *priv)
free(dev);
}
static void *
fdc37c669_init(const device_t *info)
{
@@ -340,7 +332,6 @@ const device_t fdc37c669_device = {
.config = NULL
};
const device_t fdc37c669_370_device = {
.name = "SMC FDC37C669 Super I/O (Port 370h)",
.internal_name = "fdc37c669_370",

44
src/sio/sio_fdc37c67x.c
View File

@@ -33,10 +33,8 @@
#include "cpu.h"
#include <86box/sio.h>
#define AB_RST 0x80
typedef struct {
uint8_t chip_id, is_apm,
tries,
@@ -51,11 +49,9 @@ typedef struct {
serial_t *uart[2];
} fdc37c67x_t;
static void fdc37c67x_write(uint16_t port, uint8_t val, void *priv);
static uint8_t fdc37c67x_read(uint16_t port, void *priv);
static uint16_t
make_port(fdc37c67x_t *dev, uint8_t ld)
{
@@ -67,7 +63,6 @@ make_port(fdc37c67x_t *dev, uint8_t ld)
return p;
}
static uint8_t
fdc37c67x_auxio_read(uint16_t port, void *priv)
{
@@ -76,7 +71,6 @@ fdc37c67x_auxio_read(uint16_t port, void *priv)
return dev->auxio_reg;
}
static void
fdc37c67x_auxio_write(uint16_t port, uint8_t val, void *priv)
{
@@ -85,7 +79,6 @@ fdc37c67x_auxio_write(uint16_t port, uint8_t val, void *priv)
dev->auxio_reg = val;
}
static uint8_t
fdc37c67x_gpio_read(uint16_t port, void *priv)
{
@@ -97,7 +90,6 @@ fdc37c67x_gpio_read(uint16_t port, void *priv)
return ret;
}
static void
fdc37c67x_gpio_write(uint16_t port, uint8_t val, void *priv)
{
@@ -107,7 +99,6 @@ fdc37c67x_gpio_write(uint16_t port, uint8_t val, void *priv)
dev->gpio_regs[0] = (dev->gpio_regs[0] & 0xfc) | (val & 0x03);
}
static void
fdc37c67x_fdc_handler(fdc37c67x_t *dev)
{
@@ -123,7 +114,6 @@ fdc37c67x_fdc_handler(fdc37c67x_t *dev)
}
}
static void
fdc37c67x_lpt_handler(fdc37c67x_t *dev)
{
@@ -144,7 +134,6 @@ fdc37c67x_lpt_handler(fdc37c67x_t *dev)
lpt1_irq(lpt_irq);
}
static void
fdc37c67x_serial_handler(fdc37c67x_t *dev, int uart)
{
@@ -161,7 +150,6 @@ fdc37c67x_serial_handler(fdc37c67x_t *dev, int uart)
}
}
static void
fdc37c67x_auxio_handler(fdc37c67x_t *dev)
{
@@ -178,7 +166,6 @@ fdc37c67x_auxio_handler(fdc37c67x_t *dev)
}
}
static void
fdc37c67x_sio_handler(fdc37c67x_t *dev)
{
@@ -195,7 +182,6 @@ fdc37c67x_sio_handler(fdc37c67x_t *dev)
#endif
}
static void
fdc37c67x_gpio_handler(fdc37c67x_t *dev)
{
@@ -228,7 +214,6 @@ fdc37c67x_gpio_handler(fdc37c67x_t *dev)
}
}
static void
fdc37c67x_smi_handler(fdc37c67x_t *dev)
{
@@ -243,7 +228,6 @@ fdc37c67x_smi_handler(fdc37c67x_t *dev)
pic_set_smi_irq_mask(10, dev->ld_regs[8][0xb5] & 0x80);
}
static void
fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
{
@@ -287,7 +271,8 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
/* Block writes to some logical devices. */
if (dev->regs[7] > 0x0a)
return;
else switch (dev->regs[7]) {
else
switch (dev->regs[7]) {
case 0x01:
case 0x02:
case 0x07:
@@ -300,7 +285,7 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
}
if (dev->cur_reg < 48) {
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x03:
if (valxor & 0x83)
fdc37c67x_gpio_handler(dev);
@@ -316,17 +301,18 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
if (valxor & 0x20)
fdc37c67x_serial_handler(dev, 1);
break;
case 0x26: case 0x27:
case 0x26:
case 0x27:
fdc37c67x_sio_handler(dev);
}
return;
}
switch(dev->regs[7]) {
switch (dev->regs[7]) {
case 0:
/* FDD */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -375,7 +361,7 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
break;
case 3:
/* Parallel port */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -391,7 +377,7 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
break;
case 4:
/* Serial port 1 */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -407,7 +393,7 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
break;
case 5:
/* Serial port 2 */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -423,7 +409,7 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
break;
case 8:
/* Auxiliary I/O */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -440,7 +426,6 @@ fdc37c67x_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
fdc37c67x_read(uint16_t port, void *priv)
{
@@ -464,8 +449,7 @@ fdc37c67x_read(uint16_t port, void *priv)
ret = dev->regs[dev->cur_reg];
} else {
if ((dev->regs[7] == 0) && (dev->cur_reg == 0xF2)) {
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) |
(fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
} else
ret = dev->ld_regs[dev->regs[7]][dev->cur_reg];
@@ -489,7 +473,6 @@ fdc37c67x_read(uint16_t port, void *priv)
return ret;
}
static void
fdc37c67x_reset(fdc37c67x_t *dev)
{
@@ -565,7 +548,6 @@ fdc37c67x_reset(fdc37c67x_t *dev)
dev->locked = 0;
}
static void
fdc37c67x_close(void *priv)
{
@@ -574,7 +556,6 @@ fdc37c67x_close(void *priv)
free(dev);
}
static void *
fdc37c67x_init(const device_t *info)
{
@@ -602,7 +583,6 @@ fdc37c67x_init(const device_t *info)
return dev;
}
const device_t fdc37c67x_device = {
.name = "SMC FDC37C67X Super I/O",
.internal_name = "fdc37c67x",

20
src/sio/sio_fdc37c6xx.c
View File

@@ -35,7 +35,6 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t max_reg, chip_id,
tries, has_ide,
@@ -46,7 +45,6 @@ typedef struct {
serial_t *uart[2];
} fdc37c6xx_t;
static void
set_com34_addr(fdc37c6xx_t *dev)
{
@@ -70,7 +68,6 @@ set_com34_addr(fdc37c6xx_t *dev)
}
}
static void
set_serial_addr(fdc37c6xx_t *dev, int port)
{
@@ -101,7 +98,6 @@ set_serial_addr(fdc37c6xx_t *dev, int port)
serial_set_clock_src(dev->uart[port], clock_src);
}
static void
lpt1_handler(fdc37c6xx_t *dev)
{
@@ -122,7 +118,6 @@ lpt1_handler(fdc37c6xx_t *dev)
}
}
static void
fdc_handler(fdc37c6xx_t *dev)
{
@@ -131,8 +126,6 @@ fdc_handler(fdc37c6xx_t *dev)
fdc_set_base(dev->fdc, (dev->regs[5] & 0x01) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
static void
ide_handler(fdc37c6xx_t *dev)
{
@@ -152,7 +145,6 @@ ide_handler(fdc37c6xx_t *dev)
}
}
static void
fdc37c6xx_write(uint16_t port, uint8_t val, void *priv)
{
@@ -172,7 +164,7 @@ fdc37c6xx_write(uint16_t port, uint8_t val, void *priv)
valxor = val ^ dev->regs[dev->cur_reg];
dev->regs[dev->cur_reg] = val;
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0:
if (dev->has_ide && (valxor & 0x01))
ide_handler(dev);
@@ -220,7 +212,6 @@ fdc37c6xx_write(uint16_t port, uint8_t val, void *priv)
dev->tries++;
}
static uint8_t
fdc37c6xx_read(uint16_t port, void *priv)
{
@@ -235,7 +226,6 @@ fdc37c6xx_read(uint16_t port, void *priv)
return ret;
}
static void
fdc37c6xx_reset(fdc37c6xx_t *dev)
{
@@ -258,11 +248,13 @@ fdc37c6xx_reset(fdc37c6xx_t *dev)
memset(dev->regs, 0, 16);
switch (dev->chip_id) {
case 0x63: case 0x65:
case 0x63:
case 0x65:
dev->max_reg = 0x0f;
dev->regs[0x0] = 0x3b;
break;
case 0x64: case 0x66:
case 0x64:
case 0x66:
dev->max_reg = 0x0f;
dev->regs[0x0] = 0x2b;
break;
@@ -296,7 +288,6 @@ fdc37c6xx_reset(fdc37c6xx_t *dev)
ide_handler(dev);
}
static void
fdc37c6xx_close(void *priv)
{
@@ -305,7 +296,6 @@ fdc37c6xx_close(void *priv)
free(dev);
}
static void *
fdc37c6xx_init(const device_t *info)
{

77
src/sio/sio_fdc37c93x.c
View File

@@ -35,10 +35,8 @@
#include <86box/acpi.h>
#include <86box/sio.h>
#define AB_RST 0x80
typedef struct {
uint8_t control;
uint8_t status;
@@ -65,7 +63,6 @@ typedef struct {
acpi_t *acpi;
} fdc37c93x_t;
static uint16_t
make_port(fdc37c93x_t *dev, uint8_t ld)
{
@@ -77,7 +74,6 @@ make_port(fdc37c93x_t *dev, uint8_t ld)
return p;
}
static uint16_t
make_port_sec(fdc37c93x_t *dev, uint8_t ld)
{
@@ -89,7 +85,6 @@ make_port_sec(fdc37c93x_t *dev, uint8_t ld)
return p;
}
static uint8_t
fdc37c93x_auxio_read(uint16_t port, void *priv)
{
@@ -98,7 +93,6 @@ fdc37c93x_auxio_read(uint16_t port, void *priv)
return dev->auxio_reg;
}
static void
fdc37c93x_auxio_write(uint16_t port, uint8_t val, void *priv)
{
@@ -107,7 +101,6 @@ fdc37c93x_auxio_write(uint16_t port, uint8_t val, void *priv)
dev->auxio_reg = val;
}
static uint8_t
fdc37c93x_gpio_read(uint16_t port, void *priv)
{
@@ -119,7 +112,6 @@ fdc37c93x_gpio_read(uint16_t port, void *priv)
return ret;
}
static void
fdc37c93x_gpio_write(uint16_t port, uint8_t val, void *priv)
{
@@ -129,7 +121,6 @@ fdc37c93x_gpio_write(uint16_t port, uint8_t val, void *priv)
dev->gpio_regs[0] = (dev->gpio_regs[0] & 0xfc) | (val & 0x03);
}
static void
fdc37c93x_fdc_handler(fdc37c93x_t *dev)
{
@@ -145,7 +136,6 @@ fdc37c93x_fdc_handler(fdc37c93x_t *dev)
}
}
static void
fdc37c93x_lpt_handler(fdc37c93x_t *dev)
{
@@ -166,7 +156,6 @@ fdc37c93x_lpt_handler(fdc37c93x_t *dev)
lpt1_irq(lpt_irq);
}
static void
fdc37c93x_serial_handler(fdc37c93x_t *dev, int uart)
{
@@ -183,7 +172,6 @@ fdc37c93x_serial_handler(fdc37c93x_t *dev, int uart)
}
}
static void
fdc37c93x_nvr_pri_handler(fdc37c93x_t *dev)
{
@@ -194,7 +182,6 @@ fdc37c93x_nvr_pri_handler(fdc37c93x_t *dev)
nvr_at_handler(1, 0x70, dev->nvr);
}
static void
fdc37c93x_nvr_sec_handler(fdc37c93x_t *dev)
{
@@ -211,7 +198,6 @@ fdc37c93x_nvr_sec_handler(fdc37c93x_t *dev)
}
}
static void
fdc37c93x_auxio_handler(fdc37c93x_t *dev)
{
@@ -228,7 +214,6 @@ fdc37c93x_auxio_handler(fdc37c93x_t *dev)
}
}
static void
fdc37c93x_gpio_handler(fdc37c93x_t *dev)
{
@@ -261,14 +246,13 @@ fdc37c93x_gpio_handler(fdc37c93x_t *dev)
}
}
static uint8_t
fdc37c93x_access_bus_read(uint16_t port, void *priv)
{
access_bus_t *dev = (access_bus_t *) priv;
uint8_t ret = 0xff;
switch(port & 3) {
switch (port & 3) {
case 0:
ret = (dev->status & 0xBF);
break;
@@ -286,13 +270,12 @@ fdc37c93x_access_bus_read(uint16_t port, void *priv)
return ret;
}
static void
fdc37c93x_access_bus_write(uint16_t port, uint8_t val, void *priv)
{
access_bus_t *dev = (access_bus_t *) priv;
switch(port & 3) {
switch (port & 3) {
case 0:
dev->control = (val & 0xCF);
break;
@@ -309,7 +292,6 @@ fdc37c93x_access_bus_write(uint16_t port, uint8_t val, void *priv)
}
}
static void
fdc37c93x_access_bus_handler(fdc37c93x_t *dev)
{
@@ -327,7 +309,6 @@ fdc37c93x_access_bus_handler(fdc37c93x_t *dev)
}
}
static void
fdc37c93x_acpi_handler(fdc37c93x_t *dev)
{
@@ -352,7 +333,6 @@ fdc37c93x_acpi_handler(fdc37c93x_t *dev)
acpi_set_irq_line(dev->acpi, sci_irq);
}
static void
fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
{
@@ -402,7 +382,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
/* Block writes to some logical devices. */
if (dev->regs[7] > 0x0a)
return;
else switch (dev->regs[7]) {
else
switch (dev->regs[7]) {
case 0x01:
case 0x02:
case 0x07:
@@ -435,7 +416,7 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
}
if (dev->cur_reg < 48) {
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x03:
if (valxor & 0x83)
fdc37c93x_gpio_handler(dev);
@@ -458,10 +439,10 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
return;
}
switch(dev->regs[7]) {
switch (dev->regs[7]) {
case 0:
/* FDD */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -510,7 +491,7 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
break;
case 3:
/* Parallel port */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -524,7 +505,7 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
break;
case 4:
/* Serial port 1 */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -538,7 +519,7 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
break;
case 5:
/* Serial port 2 */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -554,7 +535,7 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
/* RTC/NVR */
if (dev->chip_id != 0x30)
break;
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
if (valxor)
fdc37c93x_nvr_pri_handler(dev);
@@ -569,7 +550,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
nvr_lock_set(0xa0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x02), dev->nvr);
nvr_lock_set(0xc0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x04), dev->nvr);
nvr_lock_set(0xe0, 0x20, !!(dev->ld_regs[6][dev->cur_reg] & 0x08), dev->nvr);
if (dev->ld_regs[6][dev->cur_reg] & 0x80) switch ((dev->ld_regs[6][dev->cur_reg] >> 4) & 0x07) {
if (dev->ld_regs[6][dev->cur_reg] & 0x80)
switch ((dev->ld_regs[6][dev->cur_reg] >> 4) & 0x07) {
case 0x00:
default:
nvr_bank_set(0, 0xff, dev->nvr);
@@ -579,11 +561,13 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
nvr_bank_set(0, 0, dev->nvr);
nvr_bank_set(1, 1, dev->nvr);
break;
case 0x02: case 0x04:
case 0x02:
case 0x04:
nvr_bank_set(0, 0xff, dev->nvr);
nvr_bank_set(1, 0xff, dev->nvr);
break;
case 0x03: case 0x05:
case 0x03:
case 0x05:
nvr_bank_set(0, 0, dev->nvr);
nvr_bank_set(1, 0xff, dev->nvr);
break;
@@ -595,7 +579,8 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
nvr_bank_set(0, 0, dev->nvr);
nvr_bank_set(1, 2, dev->nvr);
break;
} else {
}
else {
nvr_bank_set(0, 0, dev->nvr);
nvr_bank_set(1, 0xff, dev->nvr);
}
@@ -605,7 +590,7 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
break;
case 8:
/* Auxiliary I/O */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -617,7 +602,7 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
break;
case 9:
/* Access bus (FDC37C932FR and FDC37C931APM only) */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -631,7 +616,7 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
break;
case 10:
/* Access bus (FDC37C931APM only) */
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
case 0x60:
case 0x61:
@@ -646,7 +631,6 @@ fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
fdc37c93x_read(uint16_t port, void *priv)
{
@@ -671,8 +655,7 @@ fdc37c93x_read(uint16_t port, void *priv)
ret = dev->regs[dev->cur_reg];
} else {
if ((dev->regs[7] == 0) && (dev->cur_reg == 0xF2)) {
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) |
(fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
ret = (fdc_get_rwc(dev->fdc, 0) | (fdc_get_rwc(dev->fdc, 1) << 2) | (fdc_get_rwc(dev->fdc, 2) << 4) | (fdc_get_rwc(dev->fdc, 3) << 6));
} else
ret = dev->ld_regs[dev->regs[7]][dev->cur_reg];
}
@@ -682,7 +665,6 @@ fdc37c93x_read(uint16_t port, void *priv)
return ret;
}
static void
fdc37c93x_reset(fdc37c93x_t *dev)
{
@@ -792,7 +774,6 @@ fdc37c93x_reset(fdc37c93x_t *dev)
dev->locked = 0;
}
static void
access_bus_close(void *priv)
{
@@ -801,7 +782,6 @@ access_bus_close(void *priv)
free(dev);
}
static void *
access_bus_init(const device_t *info)
{
@@ -811,18 +791,20 @@ access_bus_init(const device_t *info)
return dev;
}
static const device_t access_bus_device = {
"SMC FDC37C932FR ACCESS.bus",
"access_bus",
0,
0x03,
access_bus_init, access_bus_close, NULL,
{ NULL }, NULL, NULL,
access_bus_init,
access_bus_close,
NULL,
{ NULL },
NULL,
NULL,
NULL
};
static void
fdc37c93x_close(void *priv)
{
@@ -831,7 +813,6 @@ fdc37c93x_close(void *priv)
free(dev);
}
static void *
fdc37c93x_init(const device_t *info)
{

62
src/sio/sio_fdc37m60x.c
View File

@@ -39,8 +39,7 @@
/* Global Device Configuration */
#define ENABLED(ld) dev->device_regs[ld][0x30]
#define BASE_ADDRESS(ld) ((dev->device_regs[ld][0x60] << 8) | \
(dev->device_regs[ld][0x61]))
#define BASE_ADDRESS(ld) ((dev->device_regs[ld][0x60] << 8) | (dev->device_regs[ld][0x61]))
#define IRQ(ld) dev->device_regs[ld][0x70]
#define DMA(ld) dev->device_regs[ld][0x74]
@@ -48,7 +47,6 @@
#define SOFT_RESET (val & 0x01)
#define POWER_CONTROL dev->regs[0x22]
#ifdef ENABLE_FDC37M60X_LOG
int fdc37m60x_do_log = ENABLE_FDC37M60X_LOG;
@@ -57,40 +55,36 @@ fdc37m60x_log(const char *fmt, ...)
{
va_list ap;
if (fdc37m60x_do_log)
{
if (fdc37m60x_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define fdc37m60x_log(fmt, ...)
# define fdc37m60x_log(fmt, ...)
#endif
typedef struct
{
uint8_t index, regs[256], device_regs[10][256], cfg_lock, ide_function;
uint16_t sio_index_port;
fdc_t * fdc;
serial_t * uart[2];
fdc_t *fdc;
serial_t *uart[2];
} fdc37m60x_t;
static void fdc37m60x_fdc_handler(fdc37m60x_t *dev);
static void fdc37m60x_uart_handler(uint8_t num, fdc37m60x_t *dev);
static void fdc37m60x_lpt_handler(fdc37m60x_t *dev);
static void fdc37m60x_logical_device_handler(fdc37m60x_t *dev);
static void fdc37m60x_reset(void *priv);
static void
fdc37m60x_write(uint16_t addr, uint8_t val, void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *)priv;
fdc37m60x_t *dev = (fdc37m60x_t *) priv;
if (addr & 1) {
if (!dev->cfg_lock) {
@@ -118,18 +112,28 @@ fdc37m60x_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[INDEX] = val & 0x4e;
break;
case 0x2b: case 0x2c: case 0x2d: case 0x2e:
case 0x2b:
case 0x2c:
case 0x2d:
case 0x2e:
case 0x2f:
dev->regs[INDEX] = val;
break;
/* Device Configuration */
case 0x30:
case 0x60: case 0x61:
case 0x60:
case 0x61:
case 0x70:
case 0x74:
case 0xf0: case 0xf1: case 0xf2: case 0xf3:
case 0xf4: case 0xf5: case 0xf6: case 0xf7:
case 0xf0:
case 0xf1:
case 0xf2:
case 0xf3:
case 0xf4:
case 0xf5:
case 0xf6:
case 0xf7:
if (CURRENT_LOGICAL_DEVICE <= 0x81) /* Avoid Overflow */
dev->device_regs[CURRENT_LOGICAL_DEVICE][INDEX] = (INDEX == 0x30) ? (val & 1) : val;
fdc37m60x_logical_device_handler(dev);
@@ -147,11 +151,10 @@ fdc37m60x_write(uint16_t addr, uint8_t val, void *priv)
}
}
static uint8_t
fdc37m60x_read(uint16_t addr, void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *)priv;
fdc37m60x_t *dev = (fdc37m60x_t *) priv;
uint8_t ret = 0xff;
if (addr & 1)
@@ -160,14 +163,12 @@ fdc37m60x_read(uint16_t addr, void *priv)
return ret;
}
static void
fdc37m60x_fdc_handler(fdc37m60x_t *dev)
{
fdc_remove(dev->fdc);
if (ENABLED(0) || (POWER_CONTROL & 0x01))
{
if (ENABLED(0) || (POWER_CONTROL & 0x01)) {
fdc_set_base(dev->fdc, BASE_ADDRESS(0));
fdc_set_irq(dev->fdc, IRQ(0) & 0xf);
fdc_set_dma_ch(dev->fdc, DMA(0) & 0x07);
@@ -189,21 +190,19 @@ fdc37m60x_fdc_handler(fdc37m60x_t *dev)
fdc_update_drvrate(dev->fdc, 3, (dev->device_regs[0][0xf7] & 0x18) >> 3);
}
static void
fdc37m60x_uart_handler(uint8_t num, fdc37m60x_t *dev)
{
serial_remove(dev->uart[num & 1]);
if (ENABLED(4 + (num & 1)) || (POWER_CONTROL & (1 << (4 + (num & 1)))))
{
if (ENABLED(4 + (num & 1)) || (POWER_CONTROL & (1 << (4 + (num & 1))))) {
serial_setup(dev->uart[num & 1], BASE_ADDRESS(4 + (num & 1)), IRQ(4 + (num & 1)) & 0xf);
fdc37m60x_log("SMC60x-UART%d: BASE %04x IRQ %d\n", num & 1, BASE_ADDRESS(4 + (num & 1)), IRQ(4 + (num & 1)) & 0xf);
}
}
void fdc37m60x_lpt_handler(fdc37m60x_t *dev)
void
fdc37m60x_lpt_handler(fdc37m60x_t *dev)
{
lpt1_remove();
@@ -214,8 +213,8 @@ void fdc37m60x_lpt_handler(fdc37m60x_t *dev)
}
}
void fdc37m60x_logical_device_handler(fdc37m60x_t *dev)
void
fdc37m60x_logical_device_handler(fdc37m60x_t *dev)
{
/* Register 07h:
Device 0: FDC
@@ -243,7 +242,6 @@ void fdc37m60x_logical_device_handler(fdc37m60x_t *dev)
}
}
static void
fdc37m60x_reset(void *priv)
{
@@ -286,20 +284,18 @@ fdc37m60x_reset(void *priv)
fdc37m60x_lpt_handler(dev);
}
static void
fdc37m60x_close(void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *)priv;
fdc37m60x_t *dev = (fdc37m60x_t *) priv;
free(dev);
}
static void *
fdc37m60x_init(const device_t *info)
{
fdc37m60x_t *dev = (fdc37m60x_t *)malloc(sizeof(fdc37m60x_t));
fdc37m60x_t *dev = (fdc37m60x_t *) malloc(sizeof(fdc37m60x_t));
memset(dev, 0, sizeof(fdc37m60x_t));
SIO_INDEX_PORT = info->local;

29
src/sio/sio_it8661f.c
View File

@@ -33,10 +33,8 @@
#include <86box/fdd_common.h>
#include <86box/sio.h>
#define LDN dev->regs[7]
typedef struct
{
fdc_t *fdc_controller;
@@ -46,17 +44,13 @@ typedef struct
int unlocked, enumerator;
} it8661f_t;
static uint8_t mb_pnp_key[32] = {0x6a, 0xb5, 0xda, 0xed, 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, 0xce, 0xe7, 0x73, 0x39};
static uint8_t mb_pnp_key[32] = { 0x6a, 0xb5, 0xda, 0xed, 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, 0xce, 0xe7, 0x73, 0x39 };
static void it8661f_reset(void *priv);
#ifdef ENABLE_IT8661_LOG
int it8661_do_log = ENABLE_IT8661_LOG;
void
it8661_log(const char *fmt, ...)
{
@@ -69,10 +63,9 @@ it8661_log(const char *fmt, ...)
}
}
#else
#define it8661_log(fmt, ...)
# define it8661_log(fmt, ...)
#endif
static void
it8661_fdc(uint16_t addr, uint8_t val, it8661f_t *dev)
{
@@ -120,7 +113,6 @@ it8661_fdc(uint16_t addr, uint8_t val, it8661f_t *dev)
}
}
static void
it8661_serial(int uart, uint16_t addr, uint8_t val, it8661f_t *dev)
{
@@ -158,7 +150,6 @@ it8661_serial(int uart, uint16_t addr, uint8_t val, it8661f_t *dev)
}
}
void
it8661_lpt(uint16_t addr, uint8_t val, it8661f_t *dev)
{
@@ -196,7 +187,6 @@ it8661_lpt(uint16_t addr, uint8_t val, it8661f_t *dev)
}
}
void
it8661_ldn(uint16_t addr, uint8_t val, it8661f_t *dev)
{
@@ -214,11 +204,10 @@ it8661_ldn(uint16_t addr, uint8_t val, it8661f_t *dev)
}
}
static void
it8661f_write(uint16_t addr, uint8_t val, void *priv)
{
it8661f_t *dev = (it8661f_t *)priv;
it8661f_t *dev = (it8661f_t *) priv;
switch (addr) {
case FDC_SECONDARY_ADDR:
@@ -262,21 +251,19 @@ it8661f_write(uint16_t addr, uint8_t val, void *priv)
return;
}
static uint8_t
it8661f_read(uint16_t addr, void *priv)
{
it8661f_t *dev = (it8661f_t *)priv;
it8661f_t *dev = (it8661f_t *) priv;
it8661_log("IT8661F:\n", addr, dev->regs[dev->index]);
return (addr == 0xa79) ? dev->regs[dev->index] : 0xff;
}
static void
it8661f_reset(void *priv)
{
it8661f_t *dev = (it8661f_t *)priv;
it8661f_t *dev = (it8661f_t *) priv;
dev->regs[0x20] = 0x86;
dev->regs[0x21] = 0x61;
@@ -304,20 +291,18 @@ it8661f_reset(void *priv)
dev->device_regs[3][0xf0] = 3;
}
static void
it8661f_close(void *priv)
{
it8661f_t *dev = (it8661f_t *)priv;
it8661f_t *dev = (it8661f_t *) priv;
free(dev);
}
static void *
it8661f_init(const device_t *info)
{
it8661f_t *dev = (it8661f_t *)malloc(sizeof(it8661f_t));
it8661f_t *dev = (it8661f_t *) malloc(sizeof(it8661f_t));
memset(dev, 0, sizeof(it8661f_t));
dev->fdc_controller = device_add(&fdc_at_smc_device);

14
src/sio/sio_pc87306.c
View File

@@ -34,7 +34,6 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t tries,
regs[29], gpio[2];
@@ -44,7 +43,6 @@ typedef struct {
nvr_t *nvr;
} pc87306_t;
static void
pc87306_gpio_write(uint16_t port, uint8_t val, void *priv)
{
@@ -53,7 +51,6 @@ pc87306_gpio_write(uint16_t port, uint8_t val, void *priv)
dev->gpio[port & 1] = val;
}
uint8_t
pc87306_gpio_read(uint16_t port, void *priv)
{
@@ -62,7 +59,6 @@ pc87306_gpio_read(uint16_t port, void *priv)
return dev->gpio[port & 1];
}
static void
pc87306_gpio_remove(pc87306_t *dev)
{
@@ -72,7 +68,6 @@ pc87306_gpio_remove(pc87306_t *dev)
pc87306_gpio_read, NULL, NULL, pc87306_gpio_write, NULL, NULL, dev);
}
static void
pc87306_gpio_init(pc87306_t *dev)
{
@@ -85,7 +80,6 @@ pc87306_gpio_init(pc87306_t *dev)
pc87306_gpio_read, NULL, NULL, pc87306_gpio_write, NULL, NULL, dev);
}
static void
lpt1_handler(pc87306_t *dev)
{
@@ -127,7 +121,6 @@ lpt1_handler(pc87306_t *dev)
lpt1_irq(lpt_irq);
}
static void
serial_handler(pc87306_t *dev, int uart)
{
@@ -189,7 +182,6 @@ serial_handler(pc87306_t *dev, int uart)
}
}
static void
pc87306_write(uint16_t port, uint8_t val, void *priv)
{
@@ -222,7 +214,7 @@ pc87306_write(uint16_t port, uint8_t val, void *priv)
}
}
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0:
if (valxor & 1) {
lpt1_remove();
@@ -330,7 +322,6 @@ pc87306_write(uint16_t port, uint8_t val, void *priv)
}
}
uint8_t
pc87306_read(uint16_t port, void *priv)
{
@@ -353,7 +344,6 @@ pc87306_read(uint16_t port, void *priv)
return ret;
}
void
pc87306_reset(pc87306_t *dev)
{
@@ -387,7 +377,6 @@ pc87306_reset(pc87306_t *dev)
pc87306_gpio_init(dev);
}
static void
pc87306_close(void *priv)
{
@@ -396,7 +385,6 @@ pc87306_close(void *priv)
free(dev);
}
static void *
pc87306_init(const device_t *info)
{

39
src/sio/sio_pc87307.c
View File

@@ -34,7 +34,6 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t id, pm_idx,
regs[48], ld_regs[256][208],
@@ -47,12 +46,10 @@ typedef struct {
serial_t *uart[2];
} pc87307_t;
static void fdc_handler(pc87307_t *dev);
static void lpt1_handler(pc87307_t *dev);
static void serial_handler(pc87307_t *dev, int uart);
static void
pc87307_gpio_write(uint16_t port, uint8_t val, void *priv)
{
@@ -62,7 +59,6 @@ pc87307_gpio_write(uint16_t port, uint8_t val, void *priv)
dev->gpio[bank][port & 3] = val;
}
uint8_t
pc87307_gpio_read(uint16_t port, void *priv)
{
@@ -80,7 +76,6 @@ pc87307_gpio_read(uint16_t port, void *priv)
return ret;
}
static void
pc87307_gpio_remove(pc87307_t *dev)
{
@@ -97,7 +92,6 @@ pc87307_gpio_remove(pc87307_t *dev)
}
}
static void
pc87307_gpio_init(pc87307_t *dev, int bank, uint16_t addr)
{
@@ -109,7 +103,6 @@ pc87307_gpio_init(pc87307_t *dev, int bank, uint16_t addr)
pc87307_gpio_read, NULL, NULL, pc87307_gpio_write, NULL, NULL, dev);
}
static void
pc87307_pm_write(uint16_t port, uint8_t val, void *priv)
{
@@ -130,7 +123,6 @@ pc87307_pm_write(uint16_t port, uint8_t val, void *priv)
}
}
uint8_t
pc87307_pm_read(uint16_t port, void *priv)
{
@@ -142,7 +134,6 @@ pc87307_pm_read(uint16_t port, void *priv)
return dev->pm_idx;
}
static void
pc87307_pm_remove(pc87307_t *dev)
{
@@ -153,7 +144,6 @@ pc87307_pm_remove(pc87307_t *dev)
}
}
static void
pc87307_pm_init(pc87307_t *dev, uint16_t addr)
{
@@ -163,7 +153,6 @@ pc87307_pm_init(pc87307_t *dev, uint16_t addr)
pc87307_pm_read, NULL, NULL, pc87307_pm_write, NULL, NULL, dev);
}
static void
fdc_handler(pc87307_t *dev)
{
@@ -182,7 +171,6 @@ fdc_handler(pc87307_t *dev)
}
}
static void
lpt1_handler(pc87307_t *dev)
{
@@ -201,7 +189,6 @@ lpt1_handler(pc87307_t *dev)
}
}
static void
serial_handler(pc87307_t *dev, int uart)
{
@@ -218,7 +205,6 @@ serial_handler(pc87307_t *dev, int uart)
serial_setup(dev->uart[uart], addr, irq);
}
static void
gpio_handler(pc87307_t *dev)
{
@@ -239,7 +225,6 @@ gpio_handler(pc87307_t *dev)
pc87307_gpio_init(dev, 1, addr);
}
static void
pm_handler(pc87307_t *dev)
{
@@ -255,7 +240,6 @@ pm_handler(pc87307_t *dev)
pc87307_pm_init(dev, addr);
}
static void
pc87307_write(uint16_t port, uint8_t val, void *priv)
{
@@ -269,8 +253,12 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
return;
} else {
switch (dev->cur_reg) {
case 0x00: case 0x02: case 0x03: case 0x06:
case 0x07: case 0x21:
case 0x00:
case 0x02:
case 0x03:
case 0x06:
case 0x07:
case 0x21:
dev->regs[dev->cur_reg] = val;
break;
case 0x22:
@@ -291,7 +279,7 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
}
}
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x01;
switch (dev->regs[0x07]) {
@@ -315,7 +303,8 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
break;
}
break;
case 0x60: case 0x62:
case 0x60:
case 0x62:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x07;
if ((dev->cur_reg == 0x62) && (dev->regs[0x07] != 0x07))
break;
@@ -380,7 +369,8 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
}
break;
case 0x70:
case 0x74: case 0x75:
case 0x74:
case 0x75:
switch (dev->regs[0x07]) {
case 0x03:
fdc_handler(dev);
@@ -416,7 +406,8 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf3;
lpt1_handler(dev);
break;
case 0x05: case 0x06:
case 0x05:
case 0x06:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x87;
break;
}
@@ -428,7 +419,6 @@ pc87307_write(uint16_t port, uint8_t val, void *priv)
}
}
uint8_t
pc87307_read(uint16_t port, void *priv)
{
@@ -451,7 +441,6 @@ pc87307_read(uint16_t port, void *priv)
return ret;
}
void
pc87307_reset(pc87307_t *dev)
{
@@ -553,7 +542,6 @@ pc87307_reset(pc87307_t *dev)
fdc_reset(dev->fdc);
}
static void
pc87307_close(void *priv)
{
@@ -562,7 +550,6 @@ pc87307_close(void *priv)
free(dev);
}
static void *
pc87307_init(const device_t *info)
{

34
src/sio/sio_pc87309.c
View File

@@ -34,7 +34,6 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t id, pm_idx,
regs[48], ld_regs[256][208],
@@ -45,12 +44,10 @@ typedef struct {
serial_t *uart[2];
} pc87309_t;
static void fdc_handler(pc87309_t *dev);
static void lpt1_handler(pc87309_t *dev);
static void serial_handler(pc87309_t *dev, int uart);
static void
pc87309_pm_write(uint16_t port, uint8_t val, void *priv)
{
@@ -71,7 +68,6 @@ pc87309_pm_write(uint16_t port, uint8_t val, void *priv)
dev->pm_idx = val & 0x07;
}
uint8_t
pc87309_pm_read(uint16_t port, void *priv)
{
@@ -83,7 +79,6 @@ pc87309_pm_read(uint16_t port, void *priv)
return dev->pm_idx;
}
static void
pc87309_pm_remove(pc87309_t *dev)
{
@@ -94,7 +89,6 @@ pc87309_pm_remove(pc87309_t *dev)
}
}
static void
pc87309_pm_init(pc87309_t *dev, uint16_t addr)
{
@@ -104,7 +98,6 @@ pc87309_pm_init(pc87309_t *dev, uint16_t addr)
pc87309_pm_read, NULL, NULL, pc87309_pm_write, NULL, NULL, dev);
}
static void
fdc_handler(pc87309_t *dev)
{
@@ -123,7 +116,6 @@ fdc_handler(pc87309_t *dev)
}
}
static void
lpt1_handler(pc87309_t *dev)
{
@@ -142,7 +134,6 @@ lpt1_handler(pc87309_t *dev)
}
}
static void
serial_handler(pc87309_t *dev, int uart)
{
@@ -159,7 +150,6 @@ serial_handler(pc87309_t *dev, int uart)
serial_setup(dev->uart[uart], addr, irq);
}
static void
pm_handler(pc87309_t *dev)
{
@@ -175,7 +165,6 @@ pm_handler(pc87309_t *dev)
pc87309_pm_init(dev, addr);
}
static void
pc87309_write(uint16_t port, uint8_t val, void *priv)
{
@@ -189,8 +178,12 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
return;
} else {
switch (dev->cur_reg) {
case 0x00: case 0x02: case 0x03: case 0x06:
case 0x07: case 0x21:
case 0x00:
case 0x02:
case 0x03:
case 0x06:
case 0x07:
case 0x21:
dev->regs[dev->cur_reg] = val;
break;
case 0x22:
@@ -205,7 +198,7 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
}
}
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0x30:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x01;
switch (dev->regs[0x07]) {
@@ -226,7 +219,8 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
break;
}
break;
case 0x60: case 0x62:
case 0x60:
case 0x62:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x07;
if (dev->cur_reg == 0x62)
break;
@@ -280,7 +274,8 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
}
break;
case 0x70:
case 0x74: case 0x75:
case 0x74:
case 0x75:
switch (dev->regs[0x07]) {
case 0x00:
fdc_handler(dev);
@@ -310,7 +305,8 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0xf3;
lpt1_handler(dev);
break;
case 0x02: case 0x03:
case 0x02:
case 0x03:
dev->ld_regs[dev->regs[0x07]][dev->cur_reg - 0x30] = val & 0x87;
break;
case 0x06:
@@ -325,7 +321,6 @@ pc87309_write(uint16_t port, uint8_t val, void *priv)
}
}
uint8_t
pc87309_read(uint16_t port, void *priv)
{
@@ -346,7 +341,6 @@ pc87309_read(uint16_t port, void *priv)
return ret;
}
void
pc87309_reset(pc87309_t *dev)
{
@@ -435,7 +429,6 @@ pc87309_reset(pc87309_t *dev)
fdc_reset(dev->fdc);
}
static void
pc87309_close(void *priv)
{
@@ -444,7 +437,6 @@ pc87309_close(void *priv)
free(dev);
}
static void *
pc87309_init(const device_t *info)
{

21
src/sio/sio_pc87310.c
View File

@@ -50,15 +50,14 @@ pc87310_log(const char *fmt, ...)
{
va_list ap;
if (pc87310_do_log)
{
if (pc87310_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define pc87310_log(fmt, ...)
# define pc87310_log(fmt, ...)
#endif
typedef struct {
@@ -68,7 +67,6 @@ typedef struct {
serial_t *uart[2];
} pc87310_t;
static void
lpt1_handler(pc87310_t *dev)
{
@@ -106,7 +104,6 @@ lpt1_handler(pc87310_t *dev)
lpt1_irq(lpt_irq);
}
static void
serial_handler(pc87310_t *dev, int uart)
{
@@ -117,9 +114,9 @@ serial_handler(pc87310_t *dev, int uart)
*/
temp = (dev->reg >> (2 + uart)) & 1;
//current serial port is enabled
if (!temp){
//configure serial port as COM2
// current serial port is enabled
if (!temp) {
// configure serial port as COM2
if (((dev->reg >> 4) & 1) ^ uart)
serial_setup(dev->uart[uart], COM2_ADDR, COM2_IRQ);
// configure serial port as COM1
@@ -128,7 +125,6 @@ serial_handler(pc87310_t *dev, int uart)
}
}
static void
pc87310_write(uint16_t port, uint8_t val, void *priv)
{
@@ -191,7 +187,6 @@ pc87310_write(uint16_t port, uint8_t val, void *priv)
return;
}
uint8_t
pc87310_read(uint16_t port, void *priv)
{
@@ -207,7 +202,6 @@ pc87310_read(uint16_t port, void *priv)
return ret;
}
void
pc87310_reset(pc87310_t *dev)
{
@@ -224,10 +218,9 @@ pc87310_reset(pc87310_t *dev)
serial_handler(dev, 0);
serial_handler(dev, 1);
fdc_reset(dev->fdc);
//ide_pri_enable();
// ide_pri_enable();
}
static void
pc87310_close(void *priv)
{
@@ -236,7 +229,6 @@ pc87310_close(void *priv)
free(dev);
}
static void *
pc87310_init(const device_t *info)
{
@@ -259,7 +251,6 @@ pc87310_init(const device_t *info)
io_sethandler(0x3f3, 0x0001,
pc87310_read, NULL, NULL, pc87310_write, NULL, NULL, dev);
return dev;
}

58
src/sio/sio_pc87311.c
View File

@@ -50,15 +50,14 @@ pc87311_log(const char *fmt, ...)
{
va_list ap;
if (pc87311_do_log)
{
if (pc87311_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define pc87311_log(fmt, ...)
# define pc87311_log(fmt, ...)
#endif
typedef struct
@@ -79,10 +78,9 @@ void pc87311_enable(pc87311_t *dev);
static void
pc87311_write(uint16_t addr, uint8_t val, void *priv)
{
pc87311_t *dev = (pc87311_t *)priv;
pc87311_t *dev = (pc87311_t *) priv;
switch (addr)
{
switch (addr) {
case 0x398:
case 0x26e:
dev->index = val;
@@ -90,8 +88,7 @@ pc87311_write(uint16_t addr, uint8_t val, void *priv)
case 0x399:
case 0x26f:
switch (dev->index)
{
switch (dev->index) {
case 0x00:
FUNCTION_ENABLE = val;
break;
@@ -111,22 +108,23 @@ pc87311_write(uint16_t addr, uint8_t val, void *priv)
static uint8_t
pc87311_read(uint16_t addr, void *priv)
{
pc87311_t *dev = (pc87311_t *)priv;
pc87311_t *dev = (pc87311_t *) priv;
return dev->regs[dev->index];
}
void pc87311_fdc_handler(pc87311_t *dev)
void
pc87311_fdc_handler(pc87311_t *dev)
{
fdc_remove(dev->fdc_controller);
fdc_set_base(dev->fdc_controller, (FUNCTION_ENABLE & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
pc87311_log("PC87311-FDC: BASE %04x\n", (FUNCTION_ENABLE & 0x20) ? FDC_SECONDARY_ADDR : FDC_PRIMARY_ADDR);
}
uint16_t com3(pc87311_t *dev)
uint16_t
com3(pc87311_t *dev)
{
switch (COM_BA)
{
switch (COM_BA) {
case 0:
return COM3_ADDR;
case 1:
@@ -140,10 +138,10 @@ uint16_t com3(pc87311_t *dev)
}
}
uint16_t com4(pc87311_t *dev)
uint16_t
com4(pc87311_t *dev)
{
switch (COM_BA)
{
switch (COM_BA) {
case 0:
return COM4_ADDR;
case 1:
@@ -157,12 +155,12 @@ uint16_t com4(pc87311_t *dev)
}
}
void pc87311_uart_handler(uint8_t num, pc87311_t *dev)
void
pc87311_uart_handler(uint8_t num, pc87311_t *dev)
{
serial_remove(dev->uart[num & 1]);
switch (!(num & 1) ? UART1_BA : UART2_BA)
{
switch (!(num & 1) ? UART1_BA : UART2_BA) {
case 0:
dev->base = COM1_ADDR;
dev->irq = COM1_IRQ;
@@ -184,11 +182,11 @@ void pc87311_uart_handler(uint8_t num, pc87311_t *dev)
pc87311_log("PC87311-UART%01x: BASE %04x IRQ %01x\n", num & 1, dev->base, dev->irq);
}
void pc87311_lpt_handler(pc87311_t *dev)
void
pc87311_lpt_handler(pc87311_t *dev)
{
lpt1_remove();
switch (LPT_BA)
{
switch (LPT_BA) {
case 0:
dev->base = LPT1_ADDR;
dev->irq = (POWER_TEST & 0x08) ? LPT1_IRQ : LPT2_IRQ;
@@ -207,7 +205,8 @@ void pc87311_lpt_handler(pc87311_t *dev)
pc87311_log("PC87311-LPT: BASE %04x IRQ %01x\n", dev->base, dev->irq);
}
void pc87311_ide_handler(pc87311_t *dev)
void
pc87311_ide_handler(pc87311_t *dev)
{
ide_pri_disable();
ide_sec_disable();
@@ -216,8 +215,7 @@ void pc87311_ide_handler(pc87311_t *dev)
ide_set_side(0, 0x3f6);
ide_pri_enable();
if (FUNCTION_ENABLE & 0x80)
{
if (FUNCTION_ENABLE & 0x80) {
ide_set_base(1, 0x170);
ide_set_side(1, 0x376);
ide_sec_enable();
@@ -225,7 +223,8 @@ void pc87311_ide_handler(pc87311_t *dev)
pc87311_log("PC87311-IDE: PRI %01x SEC %01x\n", (FUNCTION_ENABLE >> 6) & 1, (FUNCTION_ENABLE >> 7) & 1);
}
void pc87311_enable(pc87311_t *dev)
void
pc87311_enable(pc87311_t *dev)
{
(FUNCTION_ENABLE & 0x01) ? pc87311_lpt_handler(dev) : lpt1_remove();
(FUNCTION_ENABLE & 0x02) ? pc87311_uart_handler(0, dev) : serial_remove(dev->uart[0]);
@@ -233,8 +232,7 @@ void pc87311_enable(pc87311_t *dev)
(FUNCTION_ENABLE & 0x08) ? pc87311_fdc_handler(dev) : fdc_remove(dev->fdc_controller);
if (FUNCTION_ENABLE & 0x20)
pc87311_fdc_handler(dev);
if (HAS_IDE_FUNCTIONALITY)
{
if (HAS_IDE_FUNCTIONALITY) {
(FUNCTION_ENABLE & 0x40) ? pc87311_ide_handler(dev) : ide_pri_disable();
(FUNCTION_ADDRESS & 0x80) ? pc87311_ide_handler(dev) : ide_sec_disable();
}
@@ -243,7 +241,7 @@ void pc87311_enable(pc87311_t *dev)
static void
pc87311_close(void *priv)
{
pc87311_t *dev = (pc87311_t *)priv;
pc87311_t *dev = (pc87311_t *) priv;
free(dev);
}
@@ -251,7 +249,7 @@ pc87311_close(void *priv)
static void *
pc87311_init(const device_t *info)
{
pc87311_t *dev = (pc87311_t *)malloc(sizeof(pc87311_t));
pc87311_t *dev = (pc87311_t *) malloc(sizeof(pc87311_t));
memset(dev, 0, sizeof(pc87311_t));
/* Avoid conflicting with machines that make no use of the PC87311 Internal IDE */

11
src/sio/sio_pc87332.c
View File

@@ -34,7 +34,6 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t tries, has_ide,
fdc_on, regs[15];
@@ -43,7 +42,6 @@ typedef struct {
serial_t *uart[2];
} pc87332_t;
static void
lpt1_handler(pc87332_t *dev)
{
@@ -78,7 +76,6 @@ lpt1_handler(pc87332_t *dev)
lpt1_irq(lpt_irq);
}
static void
serial_handler(pc87332_t *dev, int uart)
{
@@ -128,7 +125,6 @@ serial_handler(pc87332_t *dev, int uart)
}
}
static void
ide_handler(pc87332_t *dev)
{
@@ -148,7 +144,6 @@ ide_handler(pc87332_t *dev)
}
}
static void
pc87332_write(uint16_t port, uint8_t val, void *priv)
{
@@ -175,7 +170,7 @@ pc87332_write(uint16_t port, uint8_t val, void *priv)
}
}
switch(dev->cur_reg) {
switch (dev->cur_reg) {
case 0:
if (valxor & 1) {
lpt1_remove();
@@ -244,7 +239,6 @@ pc87332_write(uint16_t port, uint8_t val, void *priv)
}
}
uint8_t
pc87332_read(uint16_t port, void *priv)
{
@@ -267,7 +261,6 @@ pc87332_read(uint16_t port, void *priv)
return ret;
}
void
pc87332_reset(pc87332_t *dev)
{
@@ -299,7 +292,6 @@ pc87332_reset(pc87332_t *dev)
ide_handler(dev);
}
static void
pc87332_close(void *priv)
{
@@ -308,7 +300,6 @@ pc87332_close(void *priv)
free(dev);
}
static void *
pc87332_init(const device_t *info)
{

44
src/sio/sio_prime3b.c
View File

@@ -42,15 +42,14 @@ prime3b_log(const char *fmt, ...)
{
va_list ap;
if (prime3b_do_log)
{
if (prime3b_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define prime3b_log(fmt, ...)
# define prime3b_log(fmt, ...)
#endif
typedef struct
@@ -73,10 +72,9 @@ void prime3b_powerdown(prime3b_t *dev);
static void
prime3b_write(uint16_t addr, uint8_t val, void *priv)
{
prime3b_t *dev = (prime3b_t *)priv;
prime3b_t *dev = (prime3b_t *) priv;
if (addr == 0x398)
{
if (addr == 0x398) {
dev->index = val;
/* Enter/Escape Configuration Mode */
@@ -84,11 +82,8 @@ prime3b_write(uint16_t addr, uint8_t val, void *priv)
dev->cfg_lock = 0;
else if (val == 0xcc)
dev->cfg_lock = 1;
}
else if ((addr == 0x399) && !dev->cfg_lock)
{
switch (dev->index)
{
} else if ((addr == 0x399) && !dev->cfg_lock) {
switch (dev->index) {
case 0xa0: /* Function Selection Register (FSR) */
FSR = val;
prime3b_enable(dev);
@@ -105,8 +100,7 @@ prime3b_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0xa4: /* Miscellaneous Function Register */
dev->regs[0xa4] = val;
switch ((dev->regs[0xa4] >> 6) & 3)
{
switch ((dev->regs[0xa4] >> 6) & 3) {
case 0:
dev->com3_addr = COM3_ADDR;
dev->com4_addr = COM4_ADDR;
@@ -135,12 +129,13 @@ prime3b_write(uint16_t addr, uint8_t val, void *priv)
static uint8_t
prime3b_read(uint16_t addr, void *priv)
{
prime3b_t *dev = (prime3b_t *)priv;
prime3b_t *dev = (prime3b_t *) priv;
return dev->regs[dev->index];
}
void prime3b_fdc_handler(prime3b_t *dev)
void
prime3b_fdc_handler(prime3b_t *dev)
{
uint16_t fdc_base = !(ASR & 0x40) ? FDC_PRIMARY_ADDR : FDC_SECONDARY_ADDR;
fdc_remove(dev->fdc_controller);
@@ -148,7 +143,8 @@ void prime3b_fdc_handler(prime3b_t *dev)
prime3b_log("Prime3B-FDC: Enabled with base %03x\n", fdc_base);
}
void prime3b_uart_handler(uint8_t num, prime3b_t *dev)
void
prime3b_uart_handler(uint8_t num, prime3b_t *dev)
{
uint16_t uart_base;
if ((ASR >> (3 + 2 * num)) & 1)
@@ -161,7 +157,8 @@ void prime3b_uart_handler(uint8_t num, prime3b_t *dev)
prime3b_log("Prime3B-UART%d: Enabled with base %03x\n", num, uart_base);
}
void prime3b_lpt_handler(prime3b_t *dev)
void
prime3b_lpt_handler(prime3b_t *dev)
{
uint16_t lpt_base = (ASR & 2) ? LPT_MDA_ADDR : (!(ASR & 1) ? LPT1_ADDR : LPT2_ADDR);
lpt1_remove();
@@ -170,7 +167,8 @@ void prime3b_lpt_handler(prime3b_t *dev)
prime3b_log("Prime3B-LPT: Enabled with base %03x\n", lpt_base);
}
void prime3b_ide_handler(prime3b_t *dev)
void
prime3b_ide_handler(prime3b_t *dev)
{
ide_pri_disable();
uint16_t ide_base = !(ASR & 0x80) ? 0x1f0 : 0x170;
@@ -180,7 +178,8 @@ void prime3b_ide_handler(prime3b_t *dev)
prime3b_log("Prime3B-IDE: Enabled with base %03x and side %03x\n", ide_base, ide_side);
}
void prime3b_enable(prime3b_t *dev)
void
prime3b_enable(prime3b_t *dev)
{
/*
Simulate a device enable/disable scenario
@@ -205,7 +204,8 @@ void prime3b_enable(prime3b_t *dev)
(FSR & 0x20) ? prime3b_ide_handler(dev) : ide_pri_disable();
}
void prime3b_powerdown(prime3b_t *dev)
void
prime3b_powerdown(prime3b_t *dev)
{
/* Note: It can be done more efficiently for sure */
uint8_t old_base = PDR;
@@ -235,7 +235,7 @@ void prime3b_powerdown(prime3b_t *dev)
static void
prime3b_close(void *priv)
{
prime3b_t *dev = (prime3b_t *)priv;
prime3b_t *dev = (prime3b_t *) priv;
free(dev);
}
@@ -243,7 +243,7 @@ prime3b_close(void *priv)
static void *
prime3b_init(const device_t *info)
{
prime3b_t *dev = (prime3b_t *)malloc(sizeof(prime3b_t));
prime3b_t *dev = (prime3b_t *) malloc(sizeof(prime3b_t));
memset(dev, 0, sizeof(prime3b_t));
/* Avoid conflicting with machines that make no use of the Prime3B Internal IDE */

83
src/sio/sio_prime3c.c
View File

@@ -37,15 +37,14 @@ prime3c_log(const char *fmt, ...)
{
va_list ap;
if (prime3c_do_log)
{
if (prime3c_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define prime3c_log(fmt, ...)
# define prime3c_log(fmt, ...)
#endif
/* Function Select(Note on prime3c_enable) */
@@ -90,10 +89,9 @@ void prime3c_enable(prime3c_t *dev);
static void
prime3c_write(uint16_t addr, uint8_t val, void *priv)
{
prime3c_t *dev = (prime3c_t *)priv;
prime3c_t *dev = (prime3c_t *) priv;
switch (addr)
{
switch (addr) {
case 0x398:
dev->index = val;
@@ -105,10 +103,8 @@ prime3c_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x399:
if (!dev->cfg_lock)
{
switch (dev->index)
{
if (!dev->cfg_lock) {
switch (dev->index) {
case 0xc2:
FUNCTION_SELECT = val & 0xbf;
prime3c_enable(dev);
@@ -198,16 +194,16 @@ prime3c_write(uint16_t addr, uint8_t val, void *priv)
static uint8_t
prime3c_read(uint16_t addr, void *priv)
{
prime3c_t *dev = (prime3c_t *)priv;
prime3c_t *dev = (prime3c_t *) priv;
return dev->regs[dev->index];
}
void prime3c_fdc_handler(prime3c_t *dev)
void
prime3c_fdc_handler(prime3c_t *dev)
{
fdc_remove(dev->fdc_controller);
if (FUNCTION_SELECT & 0x10)
{
if (FUNCTION_SELECT & 0x10) {
fdc_set_base(dev->fdc_controller, FDC_BASE_ADDRESS << 2);
fdc_set_irq(dev->fdc_controller, (FDC_LPT_IRQ >> 4) & 0xf);
fdc_set_dma_ch(dev->fdc_controller, (FDC_LPT_DMA >> 4) & 0xf);
@@ -216,21 +212,21 @@ void prime3c_fdc_handler(prime3c_t *dev)
}
}
void prime3c_uart_handler(uint8_t num, prime3c_t *dev)
void
prime3c_uart_handler(uint8_t num, prime3c_t *dev)
{
serial_remove(dev->uart[num & 1]);
if (FUNCTION_SELECT & (!(num & 1) ? 0x04 : 0x08))
{
if (FUNCTION_SELECT & (!(num & 1) ? 0x04 : 0x08)) {
serial_setup(dev->uart[num & 1], (!(num & 1) ? UART1_BASE_ADDRESS : UART2_BASE_ADDRESS) << 2, (UART_IRQ >> (!(num & 1) ? 4 : 0)) & 0xf);
prime3c_log("Prime3C-UART%01x: BASE %04x IRQ %01x\n", num & 1, (!(num & 1) ? UART1_BASE_ADDRESS : UART2_BASE_ADDRESS) << 2, (UART_IRQ >> (!(num & 1) ? 4 : 0)) & 0xf);
}
}
void prime3c_lpt_handler(prime3c_t *dev)
void
prime3c_lpt_handler(prime3c_t *dev)
{
lpt1_remove();
if (!(FUNCTION_SELECT & 0x03))
{
if (!(FUNCTION_SELECT & 0x03)) {
lpt1_init(LPT_BASE_ADDRESS << 2);
lpt1_irq(FDC_LPT_IRQ & 0xf);
@@ -238,11 +234,11 @@ void prime3c_lpt_handler(prime3c_t *dev)
}
}
void prime3c_ide_handler(prime3c_t *dev)
void
prime3c_ide_handler(prime3c_t *dev)
{
ide_pri_disable();
if (FUNCTION_SELECT & 0x20)
{
if (FUNCTION_SELECT & 0x20) {
ide_set_base(0, IDE_BASE_ADDRESS << 2);
ide_set_side(0, IDE_SIDE_ADDRESS << 2);
ide_pri_enable();
@@ -250,35 +246,36 @@ void prime3c_ide_handler(prime3c_t *dev)
}
}
void prime3c_enable(prime3c_t *dev)
void
prime3c_enable(prime3c_t *dev)
{
/*
Simulate a device enable/disable scenario
/*
Simulate a device enable/disable scenario
Register C2: Function Select
Bit 7: Gameport
Bit 6: Reserved
Bit 5: IDE
Bit 4: FDC
Bit 3: UART 2
Bit 2: UART 1
Bit 1/0: PIO (0/0 Unidirectional , 0/1 ECP, 1/0 EPP, 1/1 Disabled)
Register C2: Function Select
Bit 7: Gameport
Bit 6: Reserved
Bit 5: IDE
Bit 4: FDC
Bit 3: UART 2
Bit 2: UART 1
Bit 1/0: PIO (0/0 Unidirectional , 0/1 ECP, 1/0 EPP, 1/1 Disabled)
Note: 86Box LPT is simplistic and can't do ECP or EPP.
*/
Note: 86Box LPT is simplistic and can't do ECP or EPP.
*/
!(FUNCTION_SELECT & 0x03) ? prime3c_lpt_handler(dev) : lpt1_remove();
(FUNCTION_SELECT & 0x04) ? prime3c_uart_handler(0, dev) : serial_remove(dev->uart[0]);
(FUNCTION_SELECT & 0x08) ? prime3c_uart_handler(1, dev) : serial_remove(dev->uart[1]);
(FUNCTION_SELECT & 0x10) ? prime3c_fdc_handler(dev) : fdc_remove(dev->fdc_controller);
if (HAS_IDE_FUNCTIONALITY)
!(FUNCTION_SELECT & 0x03) ? prime3c_lpt_handler(dev) : lpt1_remove();
(FUNCTION_SELECT & 0x04) ? prime3c_uart_handler(0, dev) : serial_remove(dev->uart[0]);
(FUNCTION_SELECT & 0x08) ? prime3c_uart_handler(1, dev) : serial_remove(dev->uart[1]);
(FUNCTION_SELECT & 0x10) ? prime3c_fdc_handler(dev) : fdc_remove(dev->fdc_controller);
if (HAS_IDE_FUNCTIONALITY)
(FUNCTION_SELECT & 0x20) ? prime3c_ide_handler(dev) : ide_pri_disable();
}
static void
prime3c_close(void *priv)
{
prime3c_t *dev = (prime3c_t *)priv;
prime3c_t *dev = (prime3c_t *) priv;
free(dev);
}
@@ -286,7 +283,7 @@ prime3c_close(void *priv)
static void *
prime3c_init(const device_t *info)
{
prime3c_t *dev = (prime3c_t *)malloc(sizeof(prime3c_t));
prime3c_t *dev = (prime3c_t *) malloc(sizeof(prime3c_t));
memset(dev, 0, sizeof(prime3c_t));
/* Avoid conflicting with machines that make no use of the Prime3C Internal IDE */

16
src/sio/sio_um8669f.c
View File

@@ -38,7 +38,6 @@
#include <86box/sio.h>
#include <86box/isapnp.h>
/* This ROM was reconstructed out of many assumptions, some of which based on the IT8671F. */
static uint8_t um8669f_pnp_rom[] = {
0x55, 0xa3, 0x86, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, /* UMC8669, dummy checksum (filled in by isapnp_add_card) */
@@ -94,11 +93,9 @@ static const isapnp_device_config_t um8669f_pnp_defaults[] = {
}
};
#ifdef ENABLE_UM8669F_LOG
int um8669f_do_log = ENABLE_UM8669F_LOG;
static void
um8669f_log(const char *fmt, ...)
{
@@ -111,12 +108,10 @@ um8669f_log(const char *fmt, ...)
}
}
#else
#define um8669f_log(fmt, ...)
# define um8669f_log(fmt, ...)
#endif
typedef struct um8669f_t
{
typedef struct um8669f_t {
int locked, cur_reg_108;
void *pnp_card;
isapnp_device_config_t *pnp_config[5];
@@ -128,7 +123,6 @@ typedef struct um8669f_t
void *gameport;
} um8669f_t;
static void
um8669f_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
{
@@ -193,7 +187,6 @@ um8669f_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *pri
}
}
void
um8669f_write(uint16_t port, uint8_t val, void *priv)
{
@@ -221,7 +214,6 @@ um8669f_write(uint16_t port, uint8_t val, void *priv)
}
}
uint8_t
um8669f_read(uint16_t port, void *priv)
{
@@ -240,7 +232,6 @@ um8669f_read(uint16_t port, void *priv)
return ret;
}
void
um8669f_reset(um8669f_t *dev)
{
@@ -261,7 +252,6 @@ um8669f_reset(um8669f_t *dev)
isapnp_reset_card(dev->pnp_card);
}
static void
um8669f_close(void *priv)
{
@@ -272,7 +262,6 @@ um8669f_close(void *priv)
free(dev);
}
static void *
um8669f_init(const device_t *info)
{
@@ -300,7 +289,6 @@ um8669f_init(const device_t *info)
return dev;
}
const device_t um8669f_device = {
.name = "UMC UM8669F Super I/O",
.internal_name = "um8669f",

18
src/sio/sio_vt82c686.c
View File

@@ -32,7 +32,6 @@
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t cur_reg, last_val, regs[25],
fdc_dma, fdc_irq, uart_irq[2], lpt_dma, lpt_irq;
@@ -40,7 +39,6 @@ typedef struct {
serial_t *uart[2];
} vt82c686_t;
static uint8_t
get_lpt_length(vt82c686_t *dev)
{
@@ -52,7 +50,6 @@ get_lpt_length(vt82c686_t *dev)
return length;
}
static void
vt82c686_fdc_handler(vt82c686_t *dev)
{
@@ -68,7 +65,6 @@ vt82c686_fdc_handler(vt82c686_t *dev)
fdc_set_swap(dev->fdc, dev->regs[0x16] & 0x01);
}
static void
vt82c686_lpt_handler(vt82c686_t *dev)
{
@@ -91,7 +87,6 @@ vt82c686_lpt_handler(vt82c686_t *dev)
}
}
static void
vt82c686_serial_handler(vt82c686_t *dev, int uart)
{
@@ -101,7 +96,6 @@ vt82c686_serial_handler(vt82c686_t *dev, int uart)
serial_setup(dev->uart[uart], dev->regs[0x07 + uart] << 2, dev->uart_irq[uart]);
}
static void
vt82c686_write(uint16_t port, uint8_t val, void *priv)
{
@@ -155,7 +149,8 @@ vt82c686_write(uint16_t port, uint8_t val, void *priv)
vt82c686_lpt_handler(dev);
break;
case 0x07: case 0x08:
case 0x07:
case 0x08:
dev->regs[reg] &= 0xfe;
vt82c686_serial_handler(dev, reg == 0x08);
break;
@@ -180,7 +175,8 @@ vt82c686_write(uint16_t port, uint8_t val, void *priv)
dev->regs[reg] &= 0xfb;
break;
case 0x14: case 0x17:
case 0x14:
case 0x17:
dev->regs[reg] &= 0xfe;
break;
@@ -191,7 +187,6 @@ vt82c686_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
vt82c686_read(uint16_t port, void *priv)
{
@@ -208,7 +203,6 @@ vt82c686_read(uint16_t port, void *priv)
return dev->last_val;
}
/* Writes to Super I/O-related configuration space registers
of the VT82C686 PCI-ISA bridge are sent here by via_pipc.c */
void
@@ -246,7 +240,6 @@ vt82c686_sio_write(uint8_t addr, uint8_t val, void *priv)
}
}
static void
vt82c686_reset(vt82c686_t *dev)
{
@@ -272,7 +265,6 @@ vt82c686_reset(vt82c686_t *dev)
vt82c686_sio_write(0x85, 0x00, dev);
}
static void
vt82c686_close(void *priv)
{
@@ -281,7 +273,6 @@ vt82c686_close(void *priv)
free(dev);
}
static void *
vt82c686_init(const device_t *info)
{
@@ -301,7 +292,6 @@ vt82c686_init(const device_t *info)
return dev;
}
const device_t via_vt82c686_sio_device = {
.name = "VIA VT82C686 Integrated Super I/O",
.internal_name = "via_vt82c686_sio",

18
src/sio/sio_w83787f.c
View File

@@ -44,15 +44,14 @@ w83787_log(const char *fmt, ...)
{
va_list ap;
if (w83787_do_log)
{
if (w83787_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define w83787_log(fmt, ...)
# define w83787_log(fmt, ...)
#endif
#define FDDA_TYPE (dev->regs[7] & 3)
@@ -86,11 +85,9 @@ typedef struct {
void *gameport;
} w83787f_t;
static void w83787f_write(uint16_t port, uint8_t val, void *priv);
static uint8_t w83787f_read(uint16_t port, void *priv);
static void
w83787f_remap(w83787f_t *dev)
{
@@ -101,7 +98,6 @@ w83787f_remap(w83787f_t *dev)
dev->key = 0x88 | HEFERE;
}
#ifdef FIXME
/* FIXME: Implement EPP (and ECP) parallel port modes. */
static uint8_t
@@ -120,7 +116,6 @@ get_lpt_length(w83787f_t *dev)
}
#endif
static void
w83787f_serial_handler(w83787f_t *dev, int uart)
{
@@ -164,7 +159,6 @@ w83787f_serial_handler(w83787f_t *dev, int uart)
serial_setup(dev->uart[uart], addr, irq);
}
static void
w83787f_lpt_handler(w83787f_t *dev)
{
@@ -201,7 +195,6 @@ w83787f_lpt_handler(w83787f_t *dev)
}
}
static void
w83787f_gameport_handler(w83787f_t *dev)
{
@@ -211,7 +204,6 @@ w83787f_gameport_handler(w83787f_t *dev)
gameport_remap(dev->gameport, 0);
}
static void
w83787f_fdc_handler(w83787f_t *dev)
{
@@ -220,7 +212,6 @@ w83787f_fdc_handler(w83787f_t *dev)
fdc_set_base(dev->fdc, (dev->regs[0] & 0x10) ? FDC_PRIMARY_ADDR : FDC_SECONDARY_ADDR);
}
static void
w83787f_ide_handler(w83787f_t *dev)
{
@@ -241,7 +232,6 @@ w83787f_ide_handler(w83787f_t *dev)
}
}
static void
w83787f_write(uint16_t port, uint8_t val, void *priv)
{
@@ -351,7 +341,6 @@ w83787f_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
w83787f_read(uint16_t port, void *priv)
{
@@ -372,7 +361,6 @@ w83787f_read(uint16_t port, void *priv)
return ret;
}
static void
w83787f_reset(w83787f_t *dev)
{
@@ -430,7 +418,6 @@ w83787f_reset(w83787f_t *dev)
dev->rw_locked = 0;
}
static void
w83787f_close(void *priv)
{
@@ -439,7 +426,6 @@ w83787f_close(void *priv)
free(dev);
}
static void *
w83787f_init(const device_t *info)
{

26
src/sio/sio_w83877f.c
View File

@@ -34,7 +34,6 @@
#include <86box/fdc.h>
#include <86box/sio.h>
#define FDDA_TYPE (dev->regs[7] & 3)
#define FDDB_TYPE ((dev->regs[7] >> 2) & 3)
#define FDDC_TYPE ((dev->regs[7] >> 4) & 3)
@@ -57,7 +56,6 @@
#define PRTIQS (dev->regs[0x27] & 0x0f)
#define ECPIRQ ((dev->regs[0x27] >> 5) & 0x07)
typedef struct {
uint8_t tries, regs[42];
uint16_t reg_init;
@@ -69,11 +67,9 @@ typedef struct {
serial_t *uart[2];
} w83877f_t;
static void w83877f_write(uint16_t port, uint8_t val, void *priv);
static uint8_t w83877f_read(uint16_t port, void *priv);
static void
w83877f_remap(w83877f_t *dev)
{
@@ -90,7 +86,6 @@ w83877f_remap(w83877f_t *dev)
dev->key = (hefras ? 0x86 : 0x88) | HEFERE;
}
static uint8_t
get_lpt_length(w83877f_t *dev)
{
@@ -106,7 +101,6 @@ get_lpt_length(w83877f_t *dev)
return length;
}
static uint16_t
make_port(w83877f_t *dev, uint8_t reg)
{
@@ -117,7 +111,8 @@ make_port(w83877f_t *dev, uint8_t reg)
case 0x20:
p = ((uint16_t) (dev->regs[reg] & 0xfc)) << 2;
p &= 0xFF0;
if ((p < 0x100) || (p > 0x3F0)) p = 0x3F0;
if ((p < 0x100) || (p > 0x3F0))
p = 0x3F0;
break;
case 0x23:
l = get_lpt_length(dev);
@@ -127,7 +122,8 @@ make_port(w83877f_t *dev, uint8_t reg)
p &= 0x3F8;
else
p &= 0x3FC;
if ((p < 0x100) || (p > 0x3FF)) p = LPT1_ADDR;
if ((p < 0x100) || (p > 0x3FF))
p = LPT1_ADDR;
/* In ECP mode, A10 is active. */
if (l & 0x80)
p |= 0x400;
@@ -135,19 +131,20 @@ make_port(w83877f_t *dev, uint8_t reg)
case 0x24:
p = ((uint16_t) (dev->regs[reg] & 0xfe)) << 2;
p &= 0xFF8;
if ((p < 0x100) || (p > 0x3F8)) p = COM1_ADDR;
if ((p < 0x100) || (p > 0x3F8))
p = COM1_ADDR;
break;
case 0x25:
p = ((uint16_t) (dev->regs[reg] & 0xfe)) << 2;
p &= 0xFF8;
if ((p < 0x100) || (p > 0x3F8)) p = COM2_ADDR;
if ((p < 0x100) || (p > 0x3F8))
p = COM2_ADDR;
break;
}
return p;
}
static void
w83877f_fdc_handler(w83877f_t *dev)
{
@@ -156,7 +153,6 @@ w83877f_fdc_handler(w83877f_t *dev)
fdc_set_base(dev->fdc, FDC_PRIMARY_ADDR);
}
static void
w83877f_lpt_handler(w83877f_t *dev)
{
@@ -176,7 +172,6 @@ w83877f_lpt_handler(w83877f_t *dev)
lpt1_irq(lpt_irq);
}
static void
w83877f_serial_handler(w83877f_t *dev, int uart)
{
@@ -201,7 +196,6 @@ w83877f_serial_handler(w83877f_t *dev, int uart)
serial_set_clock_src(dev->uart[uart], clock_src);
}
static void
w83877f_write(uint16_t port, uint8_t val, void *priv)
{
@@ -367,7 +361,6 @@ w83877f_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
w83877f_read(uint16_t port, void *priv)
{
@@ -388,7 +381,6 @@ w83877f_read(uint16_t port, void *priv)
return ret;
}
static void
w83877f_reset(w83877f_t *dev)
{
@@ -431,7 +423,6 @@ w83877f_reset(w83877f_t *dev)
dev->rw_locked = 0;
}
static void
w83877f_close(void *priv)
{
@@ -440,7 +431,6 @@ w83877f_close(void *priv)
free(dev);
}
static void *
w83877f_init(const device_t *info)
{

112
src/sio/sio_w83977f.c
View File

@@ -34,10 +34,8 @@
#include <86box/fdc.h>
#include <86box/sio.h>
#define HEFRAS (dev->regs[0x26] & 0x40)
typedef struct {
uint8_t id, tries,
regs[48],
@@ -49,14 +47,11 @@ typedef struct {
serial_t *uart[2];
} w83977f_t;
static int next_id = 0;
static void w83977f_write(uint16_t port, uint8_t val, void *priv);
static uint8_t w83977f_read(uint16_t port, void *priv);
static void
w83977f_remap(w83977f_t *dev)
{
@@ -71,20 +66,17 @@ w83977f_remap(w83977f_t *dev)
w83977f_read, NULL, NULL, w83977f_write, NULL, NULL, dev);
}
static uint8_t
get_lpt_length(w83977f_t *dev)
{
uint8_t length = 4;
if (((dev->dev_regs[1][0xc0] & 0x07) != 0x00) && ((dev->dev_regs[1][0xc0] & 0x07) != 0x02) &&
((dev->dev_regs[1][0xc0] & 0x07) != 0x04))
if (((dev->dev_regs[1][0xc0] & 0x07) != 0x00) && ((dev->dev_regs[1][0xc0] & 0x07) != 0x02) && ((dev->dev_regs[1][0xc0] & 0x07) != 0x04))
length = 8;
return length;
}
static void
w83977f_fdc_handler(w83977f_t *dev)
{
@@ -101,7 +93,6 @@ w83977f_fdc_handler(w83977f_t *dev)
fdc_set_irq(dev->fdc, dev->dev_regs[0][0x40] & 0x0f);
}
static void
w83977f_lpt_handler(w83977f_t *dev)
{
@@ -129,7 +120,6 @@ w83977f_lpt_handler(w83977f_t *dev)
}
}
static void
w83977f_serial_handler(w83977f_t *dev, int uart)
{
@@ -159,7 +149,6 @@ w83977f_serial_handler(w83977f_t *dev, int uart)
serial_set_clock_src(dev->uart[uart], clock_src);
}
static void
w83977f_write(uint16_t port, uint8_t val, void *priv)
{
@@ -224,40 +213,47 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
dev->rw_locked = (val & 0x20) ? 1 : 0;
break;
case 0x30:
if (valxor & 0x01) switch (ld) {
if (valxor & 0x01)
switch (ld) {
case 0x00:
w83977f_fdc_handler(dev);
break;
case 0x01:
w83977f_lpt_handler(dev);
break;
case 0x02: case 0x03:
case 0x02:
case 0x03:
w83977f_serial_handler(dev, ld - 2);
break;
}
break;
case 0x60: case 0x61:
if (valxor & 0xff) switch (ld) {
case 0x60:
case 0x61:
if (valxor & 0xff)
switch (ld) {
case 0x00:
w83977f_fdc_handler(dev);
break;
case 0x01:
w83977f_lpt_handler(dev);
break;
case 0x02: case 0x03:
case 0x02:
case 0x03:
w83977f_serial_handler(dev, ld - 2);
break;
}
break;
case 0x70:
if (valxor & 0x0f) switch (ld) {
if (valxor & 0x0f)
switch (ld) {
case 0x00:
w83977f_fdc_handler(dev);
break;
case 0x01:
w83977f_lpt_handler(dev);
break;
case 0x02: case 0x03:
case 0x02:
case 0x03:
w83977f_serial_handler(dev, ld - 2);
break;
}
@@ -279,7 +275,8 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
if (valxor & 0x07)
w83977f_lpt_handler(dev);
break;
case 0x02: case 0x03:
case 0x02:
case 0x03:
if (valxor & 0x03)
w83977f_serial_handler(dev, ld - 2);
break;
@@ -319,7 +316,10 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
break;
}
break;
case 0xf4: case 0xf5: case 0xf6: case 0xf7:
case 0xf4:
case 0xf5:
case 0xf6:
case 0xf7:
switch (ld) {
case 0x00:
if (dev->id == 1)
@@ -333,7 +333,6 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
}
}
static uint8_t
w83977f_read(uint16_t port, void *priv)
{
@@ -360,7 +359,6 @@ w83977f_read(uint16_t port, void *priv)
return ret;
}
static void
w83977f_reset(w83977f_t *dev)
{
@@ -387,9 +385,11 @@ w83977f_reset(w83977f_t *dev)
if (!dev->type)
dev->dev_regs[0][0x01] = 0x02;
if (next_id == 1) {
dev->dev_regs[0][0x30] = 0x03; dev->dev_regs[0][0x31] = 0x70;
dev->dev_regs[0][0x30] = 0x03;
dev->dev_regs[0][0x31] = 0x70;
} else {
dev->dev_regs[0][0x30] = 0x03; dev->dev_regs[0][0x31] = 0xf0;
dev->dev_regs[0][0x30] = 0x03;
dev->dev_regs[0][0x31] = 0xf0;
}
dev->dev_regs[0][0x40] = 0x06;
if (!dev->type)
@@ -402,10 +402,12 @@ w83977f_reset(w83977f_t *dev)
if (!dev->type)
dev->dev_regs[1][0x01] = 0x02;
if (next_id == 1) {
dev->dev_regs[1][0x30] = 0x02; dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x30] = 0x02;
dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x40] = 0x05;
} else {
dev->dev_regs[1][0x30] = 0x03; dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x30] = 0x03;
dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x40] = 0x07;
}
if (!dev->type)
@@ -418,9 +420,11 @@ w83977f_reset(w83977f_t *dev)
if (!dev->type)
dev->dev_regs[2][0x01] = 0x02;
if (next_id == 1) {
dev->dev_regs[2][0x30] = 0x03; dev->dev_regs[2][0x31] = 0xe8;
dev->dev_regs[2][0x30] = 0x03;
dev->dev_regs[2][0x31] = 0xe8;
} else {
dev->dev_regs[2][0x30] = 0x03; dev->dev_regs[2][0x31] = 0xf8;
dev->dev_regs[2][0x30] = 0x03;
dev->dev_regs[2][0x31] = 0xf8;
}
dev->dev_regs[2][0x40] = 0x04;
if (!dev->type)
@@ -431,9 +435,11 @@ w83977f_reset(w83977f_t *dev)
if (!dev->type)
dev->dev_regs[3][0x01] = 0x02;
if (next_id == 1) {
dev->dev_regs[3][0x30] = 0x02; dev->dev_regs[3][0x31] = 0xe8;
dev->dev_regs[3][0x30] = 0x02;
dev->dev_regs[3][0x31] = 0xe8;
} else {
dev->dev_regs[3][0x30] = 0x02; dev->dev_regs[3][0x31] = 0xf8;
dev->dev_regs[3][0x30] = 0x02;
dev->dev_regs[3][0x31] = 0xf8;
}
dev->dev_regs[3][0x40] = 0x03;
if (!dev->type)
@@ -443,7 +449,8 @@ w83977f_reset(w83977f_t *dev)
if (!dev->type) {
dev->dev_regs[4][0x00] = 0x01;
dev->dev_regs[4][0x01] = 0x02;
dev->dev_regs[4][0x30] = 0x00; dev->dev_regs[4][0x31] = 0x70;
dev->dev_regs[4][0x30] = 0x00;
dev->dev_regs[4][0x31] = 0x70;
dev->dev_regs[4][0x40] = 0x08;
dev->dev_regs[4][0x41] = 0x02; /* Read-only */
}
@@ -452,8 +459,10 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[5][0x00] = 0x01;
if (!dev->type)
dev->dev_regs[5][0x01] = 0x02;
dev->dev_regs[5][0x30] = 0x00; dev->dev_regs[5][0x31] = 0x60;
dev->dev_regs[5][0x32] = 0x00; dev->dev_regs[5][0x33] = 0x64;
dev->dev_regs[5][0x30] = 0x00;
dev->dev_regs[5][0x31] = 0x60;
dev->dev_regs[5][0x32] = 0x00;
dev->dev_regs[5][0x33] = 0x64;
dev->dev_regs[5][0x40] = 0x01;
if (!dev->type)
dev->dev_regs[5][0x41] = 0x02; /* Read-only */
@@ -477,9 +486,12 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[7][0x41] = 0x02; /* Read-only */
if (!dev->type)
dev->dev_regs[7][0x43] = 0x02; /* Read-only? */
dev->dev_regs[7][0xb0] = 0x01; dev->dev_regs[7][0xb1] = 0x01;
dev->dev_regs[7][0xb2] = 0x01; dev->dev_regs[7][0xb3] = 0x01;
dev->dev_regs[7][0xb4] = 0x01; dev->dev_regs[7][0xb5] = 0x01;
dev->dev_regs[7][0xb0] = 0x01;
dev->dev_regs[7][0xb1] = 0x01;
dev->dev_regs[7][0xb2] = 0x01;
dev->dev_regs[7][0xb3] = 0x01;
dev->dev_regs[7][0xb4] = 0x01;
dev->dev_regs[7][0xb5] = 0x01;
dev->dev_regs[7][0xb6] = 0x01;
if (dev->type)
dev->dev_regs[7][0xb7] = 0x01;
@@ -491,17 +503,25 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[8][0x41] = 0x02; /* Read-only */
if (!dev->type)
dev->dev_regs[8][0x43] = 0x02; /* Read-only? */
dev->dev_regs[8][0xb8] = 0x01; dev->dev_regs[8][0xb9] = 0x01;
dev->dev_regs[8][0xba] = 0x01; dev->dev_regs[8][0xbb] = 0x01;
dev->dev_regs[8][0xbc] = 0x01; dev->dev_regs[8][0xbd] = 0x01;
dev->dev_regs[8][0xbe] = 0x01; dev->dev_regs[8][0xbf] = 0x01;
dev->dev_regs[8][0xb8] = 0x01;
dev->dev_regs[8][0xb9] = 0x01;
dev->dev_regs[8][0xba] = 0x01;
dev->dev_regs[8][0xbb] = 0x01;
dev->dev_regs[8][0xbc] = 0x01;
dev->dev_regs[8][0xbd] = 0x01;
dev->dev_regs[8][0xbe] = 0x01;
dev->dev_regs[8][0xbf] = 0x01;
/* Logical Device 9 (Auxiliary I/O Part III) */
if (dev->type) {
dev->dev_regs[9][0xb0] = 0x01; dev->dev_regs[9][0xb1] = 0x01;
dev->dev_regs[9][0xb2] = 0x01; dev->dev_regs[9][0xb3] = 0x01;
dev->dev_regs[9][0xb4] = 0x01; dev->dev_regs[9][0xb5] = 0x01;
dev->dev_regs[9][0xb6] = 0x01; dev->dev_regs[9][0xb7] = 0x01;
dev->dev_regs[9][0xb0] = 0x01;
dev->dev_regs[9][0xb1] = 0x01;
dev->dev_regs[9][0xb2] = 0x01;
dev->dev_regs[9][0xb3] = 0x01;
dev->dev_regs[9][0xb4] = 0x01;
dev->dev_regs[9][0xb5] = 0x01;
dev->dev_regs[9][0xb6] = 0x01;
dev->dev_regs[9][0xb7] = 0x01;
dev->dev_regs[10][0xc0] = 0x8f;
}
@@ -528,7 +548,6 @@ w83977f_reset(w83977f_t *dev)
dev->rw_locked = 0;
}
static void
w83977f_close(void *priv)
{
@@ -539,7 +558,6 @@ w83977f_close(void *priv)
free(dev);
}
static void *
w83977f_init(const device_t *info)
{