Committed the two codegen files I forgot to commit in the previous commit.
This commit is contained in:
OBattler
678
src/CPU/codegen_timing_common.c
Normal file
678
src/CPU/codegen_timing_common.c
Normal file
@@ -0,0 +1,678 @@
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#include "../ibm.h"
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#include "codegen_timing_common.h"
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uint64_t opcode_deps[256] =
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{
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/* ADD ADD ADD ADD*/
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/*00*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
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/* ADD ADD PUSH ES POP ES*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
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/* OR OR OR OR*/
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SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
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/* OR OR PUSH CS*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, 0,
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/* ADC ADC ADC ADC*/
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/*10*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
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/* ADC ADC PUSH SS POP SS*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
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/* SBB SBB SBB SBB*/
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SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
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/* SBB SBB PUSH DS POP DS*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
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/* AND AND AND AND*/
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/*20*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
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/* AND AND DAA*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
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/* SUB SUB SUB SUB*/
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SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
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/* SUB SUB DAS*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
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/* XOR XOR XOR XOR*/
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/*30*/ SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
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/* XOR XOR AAA*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
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/* CMP CMP CMP CMP*/
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SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | MODRM,
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/* CMP CMP AAS*/
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SRCDEP_EAX, SRCDEP_EAX, 0, SRCDEP_EAX | DSTDEP_EAX,
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/* INC EAX INC ECX INC EDX INC EBX*/
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/*40*/ SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
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/* INC ESP INC EBP INC ESI INC EDI*/
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SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EBP | DSTDEP_EBP, SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EDI | DSTDEP_EDI,
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/* DEC EAX DEC ECX DEC EDX DEC EBX*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
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/* DEC ESP DEC EBP DEC ESI DEC EDI*/
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SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EBP | DSTDEP_EBP, SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EDI | DSTDEP_EDI,
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/* PUSH EAX PUSH ECX PUSH EDX PUSH EBX*/
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/*50*/ SRCDEP_EAX | IMPL_ESP, SRCDEP_ECX | IMPL_ESP, SRCDEP_EDX | IMPL_ESP, SRCDEP_EBX | IMPL_ESP,
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/* PUSH ESP PUSH EBP PUSH ESI PUSH EDI*/
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SRCDEP_ESP | IMPL_ESP, SRCDEP_EBP | IMPL_ESP, SRCDEP_ESI | IMPL_ESP, SRCDEP_EDI | IMPL_ESP,
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/* POP EAX POP ECX POP EDX POP EBX*/
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DSTDEP_EAX | IMPL_ESP, DSTDEP_ECX | IMPL_ESP, DSTDEP_EDX | IMPL_ESP, DSTDEP_EBX | IMPL_ESP,
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/* POP ESP POP EBP POP ESI POP EDI*/
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DSTDEP_ESP | IMPL_ESP, DSTDEP_EBP | IMPL_ESP, DSTDEP_ESI | IMPL_ESP, DSTDEP_EDI | IMPL_ESP,
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/* PUSHA POPA BOUND ARPL*/
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/*60*/ IMPL_ESP, IMPL_ESP, 0, 0,
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0, 0, 0, 0,
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/* PUSH imm IMUL PUSH imm IMUL*/
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IMPL_ESP, DSTDEP_REG | MODRM, IMPL_ESP, DSTDEP_REG | MODRM,
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/* INSB INSW OUTSB OUTSW*/
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0, 0, 0, 0,
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/* Jxx*/
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/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/*80*/ 0, 0, 0, 0,
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/* TEST TEST XCHG XCHG*/
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SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM, SRCDEP_REG | DSTDEP_REG | MODRM,
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/* MOV MOV MOV MOV*/
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SRCDEP_REG | MODRM, SRCDEP_REG | MODRM, DSTDEP_REG | MODRM, DSTDEP_REG | MODRM,
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/* MOV from seg LEA MOV to seg POP*/
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MODRM, DSTDEP_REG | MODRM, MODRM, IMPL_ESP | MODRM,
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/* NOP XCHG XCHG XCHG*/
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/*90*/ 0, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EBX | DSTDEP_EBX,
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/* XCHG XCHG XCHG XCHG*/
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SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EBP | DSTDEP_EBP, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EDI | DSTDEP_EDI,
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/* CBW CWD CALL far WAIT*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EDX, 0, 0,
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/* PUSHF POPF SAHF LAHF*/
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IMPL_ESP, IMPL_ESP, SRCDEP_EAX, DSTDEP_EAX,
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/* MOV MOV MOV MOV*/
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/*a0*/ DSTDEP_EAX, DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX,
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/* MOVSB MOVSW CMPSB CMPSW*/
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0, 0, 0, 0,
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/* TEST TEST STOSB STOSW*/
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SRCDEP_EAX, SRCDEP_EAX, 0, 0,
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/* LODSB LODSW SCASB SCASW*/
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0, 0, 0, 0,
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/* MOV*/
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/*b0*/ DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
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DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
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DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
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DSTDEP_ESP, DSTDEP_EBP, DSTDEP_ESI, DSTDEP_EDI,
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/* RET imm RET*/
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/*c0*/ 0, 0, SRCDEP_ESP | DSTDEP_ESP, IMPL_ESP,
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/* LES LDS MOV MOV*/
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DSTDEP_REG | MODRM, DSTDEP_REG | MODRM, MODRM, MODRM,
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/* ENTER LEAVE RETF RETF*/
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IMPL_ESP, IMPL_ESP, IMPL_ESP, IMPL_ESP,
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/* INT3 INT INTO IRET*/
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0, 0, 0, 0,
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/*d0*/ 0, 0, 0, 0,
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/* AAM AAD SETALC XLAT*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX | SRCDEP_EBX,
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0, 0, 0, 0,
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0, 0, 0, 0,
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/* LOOPNE LOOPE LOOP JCXZ*/
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/*e0*/ SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX,
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/* IN AL IN AX OUT_AL OUT_AX*/
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DSTDEP_EAX, DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX,
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/* CALL JMP JMP JMP*/
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IMPL_ESP, 0, 0, 0,
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/* IN AL IN AX OUT_AL OUT_AX*/
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SRCDEP_EDX | DSTDEP_EAX, SRCDEP_EDX | DSTDEP_EAX, SRCDEP_EDX | SRCDEP_EAX, SRCDEP_EDX | SRCDEP_EAX,
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/* REPNE REPE*/
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/*f0*/ 0, 0, 0, 0,
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/* HLT CMC*/
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0, 0, 0, 0,
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/* CLC STC CLI STI*/
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0, 0, 0, 0,
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/* CLD STD INCDEC*/
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0, 0, MODRM, 0
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};
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uint64_t opcode_deps_mod3[256] =
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{
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/* ADD ADD ADD ADD*/
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/*00*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
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/* ADD ADD PUSH ES POP ES*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
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/* OR OR OR OR*/
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SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
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/* OR OR PUSH CS*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, 0,
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/* ADC ADC ADC ADC*/
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/*10*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
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/* ADC ADC PUSH SS POP SS*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
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/* SBB SBB SBB SBB*/
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SRCDEP_REG |SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
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/* SBB SBB PUSH DS POP DS*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, IMPL_ESP, IMPL_ESP,
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/* AND AND AND AND*/
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/*20*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
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/* AND AND DAA*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
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/* SUB SUB SUB SUB*/
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SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
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/* SUB SUB DAS*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
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/* XOR XOR XOR XOR*/
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/*30*/ SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | MODRM,
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/* XOR XOR AAA*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX | MODRM, 0, SRCDEP_EAX | DSTDEP_EAX,
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/* CMP CMP CMP CMP*/
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SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM,
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/* CMP CMP AAS*/
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SRCDEP_EAX, SRCDEP_EAX, 0, SRCDEP_EAX | DSTDEP_EAX,
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/* INC EAX INC ECX INC EDX INC EBX*/
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/*40*/ SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
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/* INC ESP INC EBP INC ESI INC EDI*/
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SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EBP | DSTDEP_EBP, SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EDI | DSTDEP_EDI,
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/* DEC EAX DEC ECX DEC EDX DEC EBX*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EBX | DSTDEP_EBX,
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/* DEC ESP DEC EBP DEC ESI DEC EDI*/
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SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EBP | DSTDEP_EBP, SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EDI | DSTDEP_EDI,
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/* PUSH EAX PUSH ECX PUSH EDX PUSH EBX*/
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/*50*/ SRCDEP_EAX | IMPL_ESP, SRCDEP_ECX | IMPL_ESP, SRCDEP_EDX | IMPL_ESP, SRCDEP_EBX | IMPL_ESP,
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/* PUSH ESP PUSH EBP PUSH ESI PUSH EDI*/
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SRCDEP_ESP | IMPL_ESP, SRCDEP_EBP | IMPL_ESP, SRCDEP_ESI | IMPL_ESP, SRCDEP_EDI | IMPL_ESP,
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/* POP EAX POP ECX POP EDX POP EBX*/
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DSTDEP_EAX | IMPL_ESP, DSTDEP_ECX | IMPL_ESP, DSTDEP_EDX | IMPL_ESP, DSTDEP_EBX | IMPL_ESP,
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/* POP ESP POP EBP POP ESI POP EDI*/
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DSTDEP_ESP | IMPL_ESP, DSTDEP_EBP | IMPL_ESP, DSTDEP_ESI | IMPL_ESP, DSTDEP_EDI | IMPL_ESP,
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/* PUSHA POPA BOUND ARPL*/
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/*60*/ IMPL_ESP, IMPL_ESP, 0, 0,
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0, 0, 0, 0,
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/* PUSH imm IMUL PUSH imm IMUL*/
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IMPL_ESP, DSTDEP_REG | SRCDEP_RM | MODRM, IMPL_ESP, DSTDEP_REG | SRCDEP_RM | MODRM,
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/* INSB INSW OUTSB OUTSW*/
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0, 0, 0, 0,
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/* Jxx*/
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/*70*/ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/*80*/ 0, 0, 0, 0,
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/* TEST TEST XCHG XCHG*/
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SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | SRCDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_REG | SRCDEP_RM | DSTDEP_RM | MODRM,
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/* MOV MOV MOV MOV*/
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SRCDEP_REG | DSTDEP_RM | MODRM, SRCDEP_REG | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_REG | MODRM, SRCDEP_RM | DSTDEP_REG | MODRM,
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/* MOV from seg LEA MOV to seg POP*/
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DSTDEP_RM | MODRM, DSTDEP_REG | MODRM, SRCDEP_RM | MODRM, IMPL_ESP | DSTDEP_RM | MODRM,
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/* NOP XCHG XCHG XCHG*/
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/*90*/ 0, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ECX | DSTDEP_ECX, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EDX | DSTDEP_EDX, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EBX | DSTDEP_EBX,
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/* XCHG XCHG XCHG XCHG*/
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SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESP | DSTDEP_ESP, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EBP | DSTDEP_EBP, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_ESI | DSTDEP_ESI, SRCDEP_EAX | DSTDEP_EAX | SRCDEP_EDI | DSTDEP_EDI,
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/* CBW CWD CALL far WAIT*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EDX, 0, 0,
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/* PUSHF POPF SAHF LAHF*/
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IMPL_ESP, IMPL_ESP, SRCDEP_EAX, DSTDEP_EAX,
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/* MOV MOV MOV MOV*/
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/*a0*/ DSTDEP_EAX, DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX,
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/* MOVSB MOVSW CMPSB CMPSW*/
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0, 0, 0, 0,
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/* TEST TEST STOSB STOSW*/
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SRCDEP_EAX, SRCDEP_EAX, 0, 0,
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/* LODSB LODSW SCASB SCASW*/
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0, 0, 0, 0,
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/* MOV*/
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/*b0*/ DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
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DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
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DSTDEP_EAX, DSTDEP_ECX, DSTDEP_EDX, DSTDEP_EBX,
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DSTDEP_ESP, DSTDEP_EBP, DSTDEP_ESI, DSTDEP_EDI,
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/* RET imm RET*/
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/*c0*/ 0, 0, SRCDEP_ESP | DSTDEP_ESP, IMPL_ESP,
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/* LES LDS MOV MOV*/
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DSTDEP_REG | MODRM, DSTDEP_REG | MODRM, DSTDEP_RM | MODRM, DSTDEP_RM | MODRM,
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/* ENTER LEAVE RETF RETF*/
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IMPL_ESP, IMPL_ESP, IMPL_ESP, IMPL_ESP,
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/* INT3 INT INTO IRET*/
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0, 0, 0, 0,
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/*d0*/ 0, 0, 0, 0,
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/* AAM AAD SETALC XLAT*/
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SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX | DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX | SRCDEP_EBX,
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0, 0, 0, 0,
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0, 0, 0, 0,
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/* LOOPNE LOOPE LOOP JCXZ*/
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/*e0*/ SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX | DSTDEP_ECX, SRCDEP_ECX,
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/* IN AL IN AX OUT_AL OUT_AX*/
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DSTDEP_EAX, DSTDEP_EAX, SRCDEP_EAX, SRCDEP_EAX,
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/* CALL JMP JMP JMP*/
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IMPL_ESP, 0, 0, 0,
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/* IN AL IN AX OUT_AL OUT_AX*/
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SRCDEP_EDX | DSTDEP_EAX, SRCDEP_EDX | DSTDEP_EAX, SRCDEP_EDX | SRCDEP_EAX, SRCDEP_EDX | SRCDEP_EAX,
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/* REPNE REPE*/
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/*f0*/ 0, 0, 0, 0,
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/* HLT CMC*/
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0, 0, 0, 0,
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/* CLC STC CLI STI*/
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0, 0, 0, 0,
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/* CLD STD INCDEC*/
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0, 0, SRCDEP_RM | DSTDEP_RM | MODRM, 0
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};
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uint64_t opcode_deps_0f[256] =
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{
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/*00*/ MODRM, MODRM, MODRM, MODRM,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*10*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*20*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*30*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*50*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*60*/ MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, 0, MODRM, MODRM,
|
||||
|
||||
/*70*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, MODRM, MODRM,
|
||||
|
||||
/*80*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*90*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
|
||||
/*a0*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*b0*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
0, 0, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
|
||||
/*c0*/ MODRM, MODRM, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*d0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*e0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, 0,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*f0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
};
|
||||
uint64_t opcode_deps_0f_mod3[256] =
|
||||
{
|
||||
/*00*/ MODRM, MODRM, MODRM, MODRM,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*10*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*20*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*30*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*40*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*50*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*60*/ MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, 0, MODRM, MODRM,
|
||||
|
||||
/*70*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, MODRM, MODRM,
|
||||
|
||||
/*80*/ 0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*90*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
|
||||
/*a0*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*b0*/ MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
0, 0, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
|
||||
/*c0*/ MODRM, MODRM, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
|
||||
/*d0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*e0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, 0,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
MODRM, MODRM, 0, MODRM,
|
||||
|
||||
/*f0*/ 0, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK, MODRM | MMX_SHIFTPACK,
|
||||
0, MODRM | MMX_MULTIPLY, 0, 0,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
MODRM, MODRM, MODRM, 0,
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_shift[8] =
|
||||
{
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
};
|
||||
uint64_t opcode_deps_shift_mod3[8] =
|
||||
{
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_shift_cl[8] =
|
||||
{
|
||||
MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX,
|
||||
MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX, MODRM | SRCDEP_ECX,
|
||||
};
|
||||
uint64_t opcode_deps_shift_cl_mod3[8] =
|
||||
{
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX,
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX, SRCDEP_RM | DSTDEP_RM | MODRM | SRCDEP_ECX,
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_f6[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
MODRM, 0, MODRM, MODRM,
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_f6_mod3[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
SRCDEP_RM | MODRM, 0, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_f7[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
MODRM, 0, MODRM, MODRM,
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_f7_mod3[8] =
|
||||
{
|
||||
/* TST NOT NEG*/
|
||||
SRCDEP_RM | MODRM, 0, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
/* MUL IMUL DIV IDIV*/
|
||||
SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | SRCDEP_RM | MODRM, SRCDEP_EAX | SRCDEP_EDX | DSTDEP_EAX | DSTDEP_EDX | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_ff[8] =
|
||||
{
|
||||
/* INC DEC CALL CALL far*/
|
||||
MODRM, MODRM, MODRM | IMPL_ESP, MODRM,
|
||||
/* JMP JMP far PUSH*/
|
||||
MODRM, MODRM, MODRM | IMPL_ESP, 0
|
||||
};
|
||||
uint64_t opcode_deps_ff_mod3[8] =
|
||||
{
|
||||
/* INC DEC CALL CALL far*/
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | MODRM | IMPL_ESP, MODRM,
|
||||
/* JMP JMP far PUSH*/
|
||||
SRCDEP_RM | MODRM, MODRM, SRCDEP_RM | MODRM | IMPL_ESP, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_d8[8] =
|
||||
{
|
||||
/* FADDs FMULs FCOMs FCOMPs*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_READ_ST0 | MODRM, FPU_POP | FPU_READ_ST0 | MODRM,
|
||||
/* FSUBs FSUBRs FDIVs FDIVRs*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_d8_mod3[8] =
|
||||
{
|
||||
/* FADD FMUL FCOM FCOMP*/
|
||||
FPU_RW_ST0 | FPU_READ_STREG, FPU_RW_ST0 | FPU_READ_STREG, FPU_READ_ST0 | FPU_READ_STREG, FPU_POP | FPU_READ_ST0 | FPU_READ_STREG,
|
||||
/* FSUB FSUBR FDIV FDIVR*/
|
||||
FPU_RW_ST0 | FPU_READ_STREG, FPU_RW_ST0 | FPU_READ_STREG, FPU_RW_ST0 | FPU_READ_STREG, FPU_RW_ST0 | FPU_READ_STREG
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_d9[8] =
|
||||
{
|
||||
/* FLDs FSTs FSTPs*/
|
||||
FPU_PUSH | MODRM, 0, FPU_READ_ST0 | MODRM, FPU_POP | MODRM,
|
||||
/* FLDENV FLDCW FSTENV FSTCW*/
|
||||
MODRM, MODRM, MODRM, MODRM
|
||||
};
|
||||
uint64_t opcode_deps_d9_mod3[64] =
|
||||
{
|
||||
/*FLD*/
|
||||
FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG,
|
||||
FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG, FPU_PUSH | FPU_READ_STREG,
|
||||
/*FXCH*/
|
||||
FPU_FXCH, FPU_FXCH, FPU_FXCH, FPU_FXCH,
|
||||
FPU_FXCH, FPU_FXCH, FPU_FXCH, FPU_FXCH,
|
||||
/*FNOP*/
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
/*FSTP*/
|
||||
FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP,
|
||||
FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP,
|
||||
/* opFCHS opFABS*/
|
||||
0, 0, 0, 0,
|
||||
/* opFTST opFXAM*/
|
||||
0, 0, 0, 0,
|
||||
/* opFLD1 opFLDL2T opFLDL2E opFLDPI*/
|
||||
FPU_PUSH, FPU_PUSH, FPU_PUSH, FPU_PUSH,
|
||||
/* opFLDEG2 opFLDLN2 opFLDZ*/
|
||||
FPU_PUSH, FPU_PUSH, FPU_PUSH, 0,
|
||||
/* opF2XM1 opFYL2X opFPTAN opFPATAN*/
|
||||
0, 0, 0, 0,
|
||||
/* opFDECSTP opFINCSTP,*/
|
||||
0, 0, 0, 0,
|
||||
/* opFPREM opFSQRT opFSINCOS*/
|
||||
0, 0, 0, 0,
|
||||
/* opFRNDINT opFSCALE opFSIN opFCOS*/
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_da[8] =
|
||||
{
|
||||
/* FIADDl FIMULl FICOMl FICOMPl*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FISUBl FISUBRl FIDIVl FIDIVRl*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_da_mod3[8] =
|
||||
{
|
||||
0, 0, 0, 0,
|
||||
/* FCOMPP*/
|
||||
0, FPU_POP2, 0, 0
|
||||
};
|
||||
|
||||
|
||||
uint64_t opcode_deps_db[8] =
|
||||
{
|
||||
/* FLDil FSTil FSTPil*/
|
||||
FPU_PUSH | MODRM, 0, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FLDe FSTPe*/
|
||||
0, FPU_PUSH | MODRM, 0, FPU_READ_ST0 | FPU_POP | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_db_mod3[64] =
|
||||
{
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
/* opFNOP opFCLEX opFINIT*/
|
||||
0, 0, 0, 0,
|
||||
/* opFNOP opFNOP*/
|
||||
0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_dc[8] =
|
||||
{
|
||||
/* FADDd FMULd FCOMd FCOMPd*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FSUBd FSUBRd FDIVd FDIVRd*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_dc_mod3[8] =
|
||||
{
|
||||
/* opFADDr opFMULr*/
|
||||
FPU_READ_ST0 | FPU_RW_STREG, FPU_READ_ST0 | FPU_RW_STREG, 0, 0,
|
||||
/* opFSUBRr opFSUBr opFDIVRr opFDIVr*/
|
||||
FPU_READ_ST0 | FPU_RW_STREG, FPU_READ_ST0 | FPU_RW_STREG, FPU_READ_ST0 | FPU_RW_STREG, FPU_READ_ST0 | FPU_RW_STREG
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_dd[8] =
|
||||
{
|
||||
/* FLDd FSTd FSTPd*/
|
||||
FPU_PUSH | MODRM, 0, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FRSTOR FSAVE FSTSW*/
|
||||
MODRM, 0, MODRM, MODRM
|
||||
};
|
||||
uint64_t opcode_deps_dd_mod3[8] =
|
||||
{
|
||||
/* FFFREE FST FSTP*/
|
||||
0, 0, FPU_READ_ST0 | FPU_WRITE_STREG, FPU_READ_ST0 | FPU_WRITE_STREG | FPU_POP,
|
||||
/* FUCOM FUCOMP*/
|
||||
FPU_READ_ST0 | FPU_READ_STREG, FPU_READ_ST0 | FPU_READ_STREG | FPU_POP, 0, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_de[8] =
|
||||
{
|
||||
/* FIADDw FIMULw FICOMw FICOMPw*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FISUBw FISUBRw FIDIVw FIDIVRw*/
|
||||
FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM, FPU_RW_ST0 | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_de_mod3[8] =
|
||||
{
|
||||
/* FADDP FMULP FCOMPP*/
|
||||
FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, 0, FPU_READ_ST0 | FPU_READ_ST1 | FPU_POP2,
|
||||
/* FSUBP FSUBRP FDIVP FDIVRP*/
|
||||
FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, FPU_READ_ST0 | FPU_RW_STREG | FPU_POP, FPU_READ_ST0 | FPU_RW_STREG | FPU_POP
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_df[8] =
|
||||
{
|
||||
/* FILDiw FISTiw FISTPiw*/
|
||||
FPU_PUSH | MODRM, 0, FPU_READ_ST0 | MODRM, FPU_READ_ST0 | FPU_POP | MODRM,
|
||||
/* FILDiq FBSTP FISTPiq*/
|
||||
0, FPU_PUSH | MODRM, FPU_READ_ST0 | FPU_POP | MODRM, FPU_READ_ST0 | FPU_POP | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_df_mod3[8] =
|
||||
{
|
||||
0, 0, 0, 0,
|
||||
/* FSTSW AX*/
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
uint64_t opcode_deps_81[8] =
|
||||
{
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM
|
||||
};
|
||||
uint64_t opcode_deps_81_mod3[8] =
|
||||
{
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | MODRM
|
||||
};
|
||||
uint64_t opcode_deps_8x[8] =
|
||||
{
|
||||
MODRM, MODRM, MODRM, MODRM,
|
||||
MODRM, MODRM, MODRM, MODRM
|
||||
};
|
||||
uint64_t opcode_deps_8x_mod3[8] =
|
||||
{
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM,
|
||||
SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | DSTDEP_RM | MODRM, SRCDEP_RM | MODRM
|
||||
};
|
||||
226
src/CPU/codegen_timing_common.h
Normal file
226
src/CPU/codegen_timing_common.h
Normal file
@@ -0,0 +1,226 @@
|
||||
#include "codegen_ops.h"
|
||||
|
||||
/*Instruction has input dependency on register in REG field*/
|
||||
#define SRCDEP_REG (1ull << 0)
|
||||
/*Instruction has input dependency on register in R/M field*/
|
||||
#define SRCDEP_RM (1ull << 1)
|
||||
/*Instruction modifies register in REG field*/
|
||||
#define DSTDEP_REG (1ull << 2)
|
||||
/*Instruction modifies register in R/M field*/
|
||||
#define DSTDEP_RM (1ull << 3)
|
||||
|
||||
#define SRCDEP_SHIFT 4
|
||||
#define DSTDEP_SHIFT 12
|
||||
|
||||
/*Instruction has input dependency on given register*/
|
||||
#define SRCDEP_EAX (1ull << 4)
|
||||
#define SRCDEP_ECX (1ull << 5)
|
||||
#define SRCDEP_EDX (1ull << 6)
|
||||
#define SRCDEP_EBX (1ull << 7)
|
||||
#define SRCDEP_ESP (1ull << 8)
|
||||
#define SRCDEP_EBP (1ull << 9)
|
||||
#define SRCDEP_ESI (1ull << 10)
|
||||
#define SRCDEP_EDI (1ull << 11)
|
||||
|
||||
/*Instruction modifies given register*/
|
||||
#define DSTDEP_EAX (1ull << 12)
|
||||
#define DSTDEP_ECX (1ull << 13)
|
||||
#define DSTDEP_EDX (1ull << 14)
|
||||
#define DSTDEP_EBX (1ull << 15)
|
||||
#define DSTDEP_ESP (1ull << 16)
|
||||
#define DSTDEP_EBP (1ull << 17)
|
||||
#define DSTDEP_ESI (1ull << 18)
|
||||
#define DSTDEP_EDI (1ull << 19)
|
||||
|
||||
/*Instruction has ModR/M byte*/
|
||||
#define MODRM (1ull << 20)
|
||||
/*Instruction implicitly uses ESP*/
|
||||
#define IMPL_ESP (1ull << 21)
|
||||
|
||||
/*Instruction is MMX shift or pack/unpack instruction*/
|
||||
#define MMX_SHIFTPACK (1ull << 22)
|
||||
/*Instruction is MMX multiply instruction*/
|
||||
#define MMX_MULTIPLY (1ull << 23)
|
||||
|
||||
/*Instruction pops the FPU stack*/
|
||||
#define FPU_POP (1ull << 24)
|
||||
/*Instruction pops the FPU stack twice*/
|
||||
#define FPU_POP2 (1ull << 25)
|
||||
/*Instruction pushes onto the FPU stack*/
|
||||
#define FPU_PUSH (1ull << 26)
|
||||
|
||||
/*Instruction writes to ST(0)*/
|
||||
#define FPU_WRITE_ST0 (1ull << 27)
|
||||
/*Instruction reads from ST(0)*/
|
||||
#define FPU_READ_ST0 (1ull << 28)
|
||||
/*Instruction reads from and writes to ST(0)*/
|
||||
#define FPU_RW_ST0 (3ull << 27)
|
||||
|
||||
/*Instruction reads from ST(1)*/
|
||||
#define FPU_READ_ST1 (1ull << 29)
|
||||
/*Instruction writes to ST(1)*/
|
||||
#define FPU_WRITE_ST1 (1ull << 30)
|
||||
/*Instruction reads from and writes to ST(1)*/
|
||||
#define FPU_RW_ST1 (3ull << 29)
|
||||
|
||||
/*Instruction reads from ST(reg)*/
|
||||
#define FPU_READ_STREG (1ull << 31)
|
||||
/*Instruction writes to ST(reg)*/
|
||||
#define FPU_WRITE_STREG (1ull << 32)
|
||||
/*Instruction reads from and writes to ST(reg)*/
|
||||
#define FPU_RW_STREG (3ull << 30)
|
||||
|
||||
#define FPU_FXCH (1ull << 33)
|
||||
|
||||
|
||||
#define REGMASK_IMPL_ESP (1 << 8)
|
||||
#define REGMASK_SHIFTPACK (1 << 9)
|
||||
#define REGMASK_MULTIPLY (1 << 9)
|
||||
|
||||
|
||||
extern uint64_t opcode_deps[256];
|
||||
extern uint64_t opcode_deps_mod3[256];
|
||||
extern uint64_t opcode_deps_0f[256];
|
||||
extern uint64_t opcode_deps_0f_mod3[256];
|
||||
extern uint64_t opcode_deps_shift[8];
|
||||
extern uint64_t opcode_deps_shift_mod3[8];
|
||||
extern uint64_t opcode_deps_shift_cl[8];
|
||||
extern uint64_t opcode_deps_shift_cl_mod3[8];
|
||||
extern uint64_t opcode_deps_f6[8];
|
||||
extern uint64_t opcode_deps_f6_mod3[8];
|
||||
extern uint64_t opcode_deps_f7[8];
|
||||
extern uint64_t opcode_deps_f7_mod3[8];
|
||||
extern uint64_t opcode_deps_ff[8];
|
||||
extern uint64_t opcode_deps_ff_mod3[8];
|
||||
extern uint64_t opcode_deps_d8[8];
|
||||
extern uint64_t opcode_deps_d8_mod3[8];
|
||||
extern uint64_t opcode_deps_d9[8];
|
||||
extern uint64_t opcode_deps_d9_mod3[64];
|
||||
extern uint64_t opcode_deps_da[8];
|
||||
extern uint64_t opcode_deps_da_mod3[8];
|
||||
extern uint64_t opcode_deps_db[8];
|
||||
extern uint64_t opcode_deps_db_mod3[64];
|
||||
extern uint64_t opcode_deps_dc[8];
|
||||
extern uint64_t opcode_deps_dc_mod3[8];
|
||||
extern uint64_t opcode_deps_dd[8];
|
||||
extern uint64_t opcode_deps_dd_mod3[8];
|
||||
extern uint64_t opcode_deps_de[8];
|
||||
extern uint64_t opcode_deps_de_mod3[8];
|
||||
extern uint64_t opcode_deps_df[8];
|
||||
extern uint64_t opcode_deps_df_mod3[8];
|
||||
extern uint64_t opcode_deps_81[8];
|
||||
extern uint64_t opcode_deps_81_mod3[8];
|
||||
extern uint64_t opcode_deps_8x[8];
|
||||
extern uint64_t opcode_deps_8x_mod3[8];
|
||||
|
||||
|
||||
|
||||
static inline uint32_t get_addr_regmask(uint64_t data, uint32_t fetchdat, int op_32)
|
||||
{
|
||||
uint32_t addr_regmask = 0;
|
||||
|
||||
if (data & MODRM)
|
||||
{
|
||||
uint8_t modrm = fetchdat & 0xff;
|
||||
|
||||
if ((modrm & 0xc0) != 0xc0)
|
||||
{
|
||||
if (op_32 & 0x200)
|
||||
{
|
||||
if ((modrm & 0x7) == 4)
|
||||
{
|
||||
uint8_t sib = (fetchdat >> 8) & 0xff;
|
||||
|
||||
if ((modrm & 0xc0) != 0xc0 && (sib & 7) != 5)
|
||||
{
|
||||
addr_regmask = 1 << (sib & 7);
|
||||
if ((sib & 0x38) != 0x20)
|
||||
addr_regmask |= 1 << ((sib >> 3) & 7);
|
||||
}
|
||||
}
|
||||
else if ((modrm & 0xc7) != 5)
|
||||
{
|
||||
addr_regmask = 1 << (modrm & 7);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((modrm & 0xc7) != 0x06)
|
||||
{
|
||||
switch (modrm & 7)
|
||||
{
|
||||
case 0: addr_regmask = REG_BX | REG_SI; break;
|
||||
case 1: addr_regmask = REG_BX | REG_DI; break;
|
||||
case 2: addr_regmask = REG_BP | REG_SI; break;
|
||||
case 3: addr_regmask = REG_BP | REG_DI; break;
|
||||
case 4: addr_regmask = REG_SI; break;
|
||||
case 5: addr_regmask = REG_DI; break;
|
||||
case 6: addr_regmask = REG_BP; break;
|
||||
case 7: addr_regmask = REG_BX; break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (data & IMPL_ESP)
|
||||
addr_regmask |= REGMASK_IMPL_ESP;
|
||||
|
||||
return addr_regmask;
|
||||
}
|
||||
|
||||
static inline uint32_t get_srcdep_mask(uint64_t data, uint32_t fetchdat, int bit8, int op_32)
|
||||
{
|
||||
uint32_t mask = 0;
|
||||
if (data & SRCDEP_REG)
|
||||
{
|
||||
int reg = (fetchdat >> 3) & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
if (data & SRCDEP_RM)
|
||||
{
|
||||
int reg = fetchdat & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
mask |= ((data >> SRCDEP_SHIFT) & 0xff);
|
||||
if (data & MMX_SHIFTPACK)
|
||||
mask |= REGMASK_SHIFTPACK;
|
||||
if (data & MMX_MULTIPLY)
|
||||
mask |= REGMASK_MULTIPLY;
|
||||
|
||||
mask |= get_addr_regmask(data, fetchdat, op_32);
|
||||
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline uint32_t get_dstdep_mask(uint64_t data, uint32_t fetchdat, int bit8)
|
||||
{
|
||||
uint32_t mask = 0;
|
||||
if (data & DSTDEP_REG)
|
||||
{
|
||||
int reg = (fetchdat >> 3) & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
if (data & DSTDEP_RM)
|
||||
{
|
||||
int reg = fetchdat & 7;
|
||||
if (bit8)
|
||||
reg &= 3;
|
||||
mask |= (1 << reg);
|
||||
}
|
||||
mask |= ((data >> DSTDEP_SHIFT) & 0xff);
|
||||
if (data & MMX_SHIFTPACK)
|
||||
mask |= REGMASK_SHIFTPACK;
|
||||
if (data & MMX_MULTIPLY)
|
||||
mask |= REGMASK_MULTIPLY;
|
||||
if (data & IMPL_ESP)
|
||||
mask |= REGMASK_IMPL_ESP | (1 << REG_ESP);
|
||||
|
||||
return mask;
|
||||
}
|
||||
Reference in New Issue
Block a user