From 0b7bec3831d00f8fe4a1b8626fdf0ca2a7c293a2 Mon Sep 17 00:00:00 2001
From: Panagiotis <58827426+tiseno100@users.noreply.github.com>
Date: Tue, 13 Apr 2021 15:21:10 +0300
Subject: [PATCH 01/23] Fixes on the Aladdin IV

---
 src/chipset/ali1531.c  | 27 ++++++++++-----------------
 src/chipset/ali1543.c  | 36 ++++++++++++++++++++++++++----------
 src/win/Makefile.mingw |  6 ++++++
 3 files changed, 42 insertions(+), 27 deletions(-)

diff --git a/src/chipset/ali1531.c b/src/chipset/ali1531.c
index 23a4f2564..c29d831fc 100644
--- a/src/chipset/ali1531.c
+++ b/src/chipset/ali1531.c
@@ -41,23 +41,20 @@ typedef struct ali1531_t
     smram_t *smram;
 } ali1531_t;
 
-void ali1531_shadow_recalc(ali1531_t *dev)
+void ali1531_shadow_recalc(int cur_reg, ali1531_t *dev)
 {
     for (uint32_t i = 0; i < 8; i++)
-    {
-        mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4c] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4e] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
-        mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4d] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4f] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
-    }
+        mem_set_mem_state_both(0xc0000 + ((cur_reg & 1) << 17) + (i << 14), 0x4000, (((dev->pci_conf[0x4c + (cur_reg & 1)] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4e + (cur_reg & 1)] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
 
-    shadowbios = !!(dev->pci_conf[0x4d] & 0xf0);
-    shadowbios_write = !!(dev->pci_conf[0x4f] & 0xf0);
-
-    flushmmucache();
+    flushmmucache_nopc();
 }
 
 void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev)
 {
-    if (!!(dev->pci_conf[0x48] & 1))
+
+    smram_disable_all();
+
+    if (dev->pci_conf[0x48] & 1)
     {
         switch (smm_state)
         {
@@ -86,12 +83,9 @@ void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev)
             smram_map(1, 0x30000, 0x10000, 1);
             break;
         }
-        
     }
-    else
-        smram_disable_all();
 
-    flushmmucache();
+    flushmmucache_nopc();
 }
 
 static void
@@ -160,7 +154,7 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
     case 0x4e:
     case 0x4f:
         dev->pci_conf[addr] = val;
-        ali1531_shadow_recalc(dev);
+        ali1531_shadow_recalc(addr, dev);
         break;
 
     case 0x57: /* H2PO */
@@ -202,7 +196,7 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
 	case 0x6e:
 	case 0x6f:
         dev->pci_conf[addr] = val;
-        spd_write_drbs(dev->pci_conf, 0x60, 0x6f, 2);
+        spd_write_drbs(dev->pci_conf, 0x60, 0x6f, 1);
         break;
 
     case 0x72:
@@ -274,7 +268,6 @@ ali1531_reset(void *priv)
     ali1531_write(0, 0x42, 0x00, dev);
     ali1531_write(0, 0x43, 0x00, dev);
     ali1531_write(0, 0x47, 0x00, dev);
-    ali1531_shadow_recalc(dev);
     ali1531_write(0, 0x60, 0x08, dev);
     ali1531_write(0, 0x61, 0x40, dev);
 }
diff --git a/src/chipset/ali1543.c b/src/chipset/ali1543.c
index c14a61e83..67b513a94 100644
--- a/src/chipset/ali1543.c
+++ b/src/chipset/ali1543.c
@@ -96,6 +96,8 @@ typedef struct ali1543_t
 
 */
 
+int ali1533_irq_routing[15] = {9, 3, 0x0a, 4, 5, 7, 6, 1, 0x0b, 0, 0x0c, 0, 0x0e, 0, 0x0f};
+
 void ali1533_ddma_handler(ali1543_t *dev)
 {
     for (uint8_t i = 0; i < 8; i++)
@@ -131,8 +133,23 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
         dev->pci_conf[addr] = val & 0x7f;
         break;
 
-    case 0x42:
+    case 0x42: /* ISA Bus Speed */
         dev->pci_conf[addr] = val & 0xcf;
+        switch(val & 7)
+        {
+            case 0:
+            cpu_set_isa_speed(7.16);
+            break;
+            case 1:
+            case 2:
+            case 3:
+            case 4:
+            case 5:
+            case 6:
+            cpu_set_isa_pci_div(val & 7);
+            break;
+        }
+
         break;
 
     case 0x43:
@@ -146,7 +163,7 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
     case 0x44: /* Set IRQ Line for Primary IDE if it's on native mode */
         dev->pci_conf[addr] = 0xdf;
         if (dev->ide_conf[0x09] & 1)
-            sff_set_irq_line(dev->ide_controller[0], val & 0x0f);
+            sff_set_irq_line(dev->ide_controller[0], ((val & 0x0f) == 0) ? ali1533_irq_routing[(val & 0x0f) - 1] : PCI_IRQ_DISABLED);
         break;
 
     case 0x45: /* DDMA Enable */
@@ -157,8 +174,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
     case 0x48: /* PCI IRQ Routing */
     case 0x49:
         dev->pci_conf[addr] = val;
-        pci_set_irq_routing(((addr & 1) * 2) + 2, ((val & 0xf0) == 0) ? (val & 0xf0) : PCI_IRQ_DISABLED);
-        pci_set_irq_routing(((addr & 1) * 2) + 1, ((val & 0x0f) == 0) ? (val & 0x0f) : PCI_IRQ_DISABLED);
+        pci_set_irq_routing(((addr & 1) * 2) + 2, (((val >> 4) & 0x0f) == 0) ? ali1533_irq_routing[((val >> 4) & 0x0f) - 1] : PCI_IRQ_DISABLED);
+        pci_set_irq_routing(((addr & 1) * 2) + 1, ((val & 0x0f) == 0) ? ali1533_irq_routing[(val & 0x0f) - 1] : PCI_IRQ_DISABLED);
         break;
 
     case 0x53: /* USB Enable */
@@ -222,13 +239,12 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
 
     case 0x74: /* USB IRQ Routing */
         dev->pci_conf[addr] = val & 0xdf;
-        pci_set_irq_routing(dev->usb_slot, ((val & 0x0f) == 0) ? (val & 0x0f) : PCI_IRQ_DISABLED);
         break;
 
     case 0x75: /* Set IRQ Line for Secondary IDE if it's on native mode */
         dev->pci_conf[addr] = val & 0x1f;
         if (dev->ide_conf[0x09] & 8)
-            sff_set_irq_line(dev->ide_controller[1], val & 0x0f);
+            sff_set_irq_line(dev->ide_controller[1], ((val & 0x0f) == 0) ? ali1533_irq_routing[(val & 0x0f) - 1] : PCI_IRQ_DISABLED);
         break;
 
     case 0x76: /* PMU IRQ Routing */
@@ -319,28 +335,28 @@ void ali5229_ide_handler(ali1543_t *dev)
         /* Primary Channel Setup */
         if (dev->ide_conf[0x09] & 0x10)
         {
+            ide_pri_enable();
             if (!(dev->ide_conf[0x09] & 1))
-                sff_set_irq_line(dev->ide_controller[0], dev->ide_conf[0x3c] & 0xf);
+                sff_set_irq_line(dev->ide_controller[0], (dev->ide_conf[0x3c] != 0) ? ali1533_irq_routing[(dev->ide_conf[0x3c] & 0x0f) - 1] : PCI_IRQ_DISABLED);
 
             ide_set_base(0, current_pri_base);
             ide_set_side(0, current_pri_side);
 
             sff_bus_master_handler(dev->ide_controller[0], dev->ide_conf[0x09] & 0x80, (dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8));
-            ide_pri_enable();
             ali1543_log("M5229 PRI: BASE %04x SIDE %04x\n", current_pri_base, current_pri_side);
         }
 
         /* Secondary Channel Setup */
         if (dev->ide_conf[0x09] & 8)
         {
+            ide_sec_enable();
             if (!(dev->ide_conf[0x09] & 4))
-                sff_set_irq_line(dev->ide_controller[1], dev->ide_conf[0x3c] & 0xf);
+                sff_set_irq_line(dev->ide_controller[1], (dev->ide_conf[0x3c] != 0) ? ali1533_irq_routing[(dev->ide_conf[0x3c] & 0x0f) - 1] : PCI_IRQ_DISABLED);
 
             ide_set_base(1, current_sec_base);
             ide_set_side(1, current_sec_side);
 
             sff_bus_master_handler(dev->ide_controller[1], dev->ide_conf[0x09] & 0x80, ((dev->ide_conf[0x20] & 0xf0) | (dev->ide_conf[0x21] << 8)) + 8);
-            ide_sec_enable();
             ali1543_log("M5229 SEC: BASE %04x SIDE %04x\n", current_sec_base, current_sec_side);
         }
     }
diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw
index 7f493d925..a4d5413cf 100644
--- a/src/win/Makefile.mingw
+++ b/src/win/Makefile.mingw
@@ -51,6 +51,9 @@ ifeq ($(DEV_BUILD), y)
  ifndef I450KX
   I450KX		:= y
  endif
+ ifndef M154X
+  M145X		:= y
+ endif
  ifndef LASERXT
   LASERXT	:= y
  endif
@@ -130,6 +133,9 @@ else
  ifndef LASERXT
   LASERXT	:= n
  endif
+ ifndef M154X
+  M145X		:= n
+ endif
  ifndef MGA
   MGA		:= n
  endif

From 71cbebb66234973dd17648cde442ee937a89c90e Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Tue, 13 Apr 2021 14:05:18 -0300
Subject: [PATCH 02/23] Work around P3V133 ACPI I/O space mapping issue

---
 src/chipset/via_pipc.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/chipset/via_pipc.c b/src/chipset/via_pipc.c
index 8202302e3..d488035ee 100644
--- a/src/chipset/via_pipc.c
+++ b/src/chipset/via_pipc.c
@@ -834,7 +834,7 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
 	}
     } else if (func == pm_func) { /* Power */
 	/* Read-only addresses */
-	if ((addr < 0xd) || ((addr >= 0xe) && (addr < 0x40)) || (addr == 0x43) ||
+	if ((addr < 0xd) || ((addr >= 0xe) && (addr < 0x40)) || (addr == 0x43) || (addr == 0x4a) || (addr == 0x4b) ||
 	    (addr == 0x4e) || (addr == 0x4f) || (addr == 0x56) || (addr == 0x57) || ((addr >= 0x5c) && (addr < 0x61)) ||
 	    ((addr >= 0x64) && (addr < 0x70)) || (addr == 0x72) || (addr == 0x73) || ((addr >= 0x75) && (addr < 0x80)) ||
 	    (addr == 0x83) || ((addr >= 0x85) && (addr < 0x90)) || ((addr >= 0x92) && (addr < 0xd2)) || (addr >= 0xd7))
@@ -848,10 +848,20 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
 
 	switch (addr) {
 		case 0x41: case 0x48: case 0x49:
+			if (addr == 0x48) {
+				if (dev->local >= VIA_PIPC_596A)
+					val = (val & 0x80) | 0x01;
+				else
+					val = 0x01;
+			}
+
 			dev->power_regs[addr] = val;
 			c = (dev->power_regs[0x49] << 8);
 			if (dev->local >= VIA_PIPC_596A)
 				c |= (dev->power_regs[0x48] & 0x80);
+			/* Workaround for P3V133 BIOS in 596B mode mapping ACPI to E800 (same as SMBus) instead of E400. */
+			if ((dev->local == VIA_PIPC_596B) && (c == ((dev->power_regs[0x91] << 8) | (dev->power_regs[0x90] & 0xf0))) && (dev->power_regs[0xd2] & 0x01))
+				c -= 0x400;
 			acpi_set_timer32(dev->acpi, dev->power_regs[0x41] & 0x08);
 			acpi_update_io_mapping(dev->acpi, c, dev->power_regs[0x41] & 0x80);
 			break;

From 76395e9fb6c23deb1ca3d8aa3c5c9c6ef4634978 Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Tue, 13 Apr 2021 14:07:21 -0300
Subject: [PATCH 03/23] DPMS screen blanking support

---
 src/include/86box/language.h |  3 ++-
 src/include/86box/vid_svga.h |  1 +
 src/video/vid_svga.c         | 24 ++++++++++++++++++++-
 src/win/86Box.rc             |  1 +
 src/win/win_stbar.c          | 41 ++++++++++++++++++++++++------------
 5 files changed, 54 insertions(+), 16 deletions(-)

diff --git a/src/include/86box/language.h b/src/include/86box/language.h
index b5e7a4304..006bc2312 100644
--- a/src/include/86box/language.h
+++ b/src/include/86box/language.h
@@ -115,6 +115,7 @@
 #define IDS_2139	2139		// "MO images (*.IM?)\0*.IM?..."
 #define IDS_2140	2140		// "CD-ROM images (*.ISO;*.CU.."
 #define IDS_2141	2141		// "%hs Device Configuration"
+#define IDS_2142	2142		// "Monitor in sleep mode"
 
 #define IDS_4096	4096		// "Hard disk (%s)"
 #define IDS_4097	4097		// "%01i:%01i"
@@ -222,7 +223,7 @@
 
 #define IDS_LANG_ENUS	IDS_7168
 
-#define STR_NUM_2048	94
+#define STR_NUM_2048	95
 #define STR_NUM_3072	11
 #define STR_NUM_4096	39
 #define STR_NUM_4352	6
diff --git a/src/include/86box/vid_svga.h b/src/include/86box/vid_svga.h
index ff1a7c985..018c824a5 100644
--- a/src/include/86box/vid_svga.h
+++ b/src/include/86box/vid_svga.h
@@ -135,6 +135,7 @@ typedef struct svga_t
 	    plane_mask, writemask,
 	    colourcompare, colournocare,
 	    dac_mask, dac_status,
+	    dpms, dpms_ui,
 	    ksc5601_sbyte_mask, ksc5601_udc_area_msb[2];
 
     int ksc5601_swap_mode;
diff --git a/src/video/vid_svga.c b/src/video/vid_svga.c
index f641d0bb2..58f361591 100644
--- a/src/video/vid_svga.c
+++ b/src/video/vid_svga.c
@@ -34,6 +34,8 @@
 #include <86box/pit.h>
 #include <86box/mem.h>
 #include <86box/rom.h>
+#include <86box/plat.h>
+#include <86box/ui.h>
 #include <86box/video.h>
 #include <86box/vid_svga.h>
 #include <86box/vid_svga_render.h>
@@ -574,12 +576,29 @@ svga_recalctimings(svga_t *svga)
 	svga->dispontime = TIMER_USEC;
     if (svga->dispofftime < TIMER_USEC)
 	svga->dispofftime = TIMER_USEC;
+
+    /* Inform the user interface of any DPMS mode changes. */
+    if (svga->dpms) {
+	if (!svga->dpms_ui) {
+		svga->dpms_ui = 1;
+		ui_sb_set_text_w(plat_get_string(IDS_2142));
+	}
+    } else if (svga->dpms_ui) {
+	svga->dpms_ui = 0;
+	ui_sb_set_text_w(NULL);
+    }
 }
 
 
 static void
 svga_do_render(svga_t *svga)
 {
+    /* Always render a blank screen and nothing else while in DPMS mode. */
+    if (svga->dpms) {
+	svga_render_blank(svga);
+	return;
+    }
+
     if (!svga->override) {
 	svga->render(svga);
 
@@ -1361,7 +1380,10 @@ svga_doblit(int y1, int y2, int wx, int wy, svga_t *svga)
 	} else
 		suppress_overscan = 0;
 
-	set_screen_size(xsize + x_add, ysize + y_add);
+	/* Block resolution changes while in DPMS mode to avoid getting a bogus
+	   screen width (320). We're already rendering a blank screen anyway. */
+	if (!svga->dpms)
+		set_screen_size(xsize + x_add, ysize + y_add);
 
 	if (video_force_resize_get())
 		video_force_resize_set(0);
diff --git a/src/win/86Box.rc b/src/win/86Box.rc
index 2fc62098e..ccf0fc0e0 100644
--- a/src/win/86Box.rc
+++ b/src/win/86Box.rc
@@ -1054,6 +1054,7 @@ BEGIN
     IDS_2139	"MO images (*.IM?;*.MDI)\0*.IM?;*.MDI\0All files (*.*)\0*.*\0"
     IDS_2140	"CD-ROM images (*.ISO;*.CUE)\0*.ISO;*.CUE\0All files (*.*)\0*.*\0"
     IDS_2141	"%hs Device Configuration"
+    IDS_2142    "Monitor in sleep mode"
 END
 
 STRINGTABLE DISCARDABLE 
diff --git a/src/win/win_stbar.c b/src/win/win_stbar.c
index 58566ab71..ad8b97765 100644
--- a/src/win/win_stbar.c
+++ b/src/win/win_stbar.c
@@ -72,6 +72,8 @@ static int	sb_ready = 0;
 static uint8_t	sb_map[256];
 static int  dpi = 96;
 static int  icon_width = 24;
+static wchar_t	sb_text[512] = L"\0";
+static wchar_t	sb_bugtext[512] = L"\0";
 
 /* Also used by win_settings.c */
 intptr_t
@@ -933,9 +935,8 @@ StatusBarCreate(HWND hwndParent, uintptr_t idStatus, HINSTANCE hInst)
 }
 
 
-/* API */
-void
-ui_sb_set_text_w(wchar_t *wstr)
+static void
+ui_sb_update_text()
 {
     uint8_t part = 0xff;
 
@@ -945,7 +946,19 @@ ui_sb_set_text_w(wchar_t *wstr)
     part = sb_map[SB_TEXT];
 
     if (part != 0xff)
-	SendMessage(hwndSBAR, SB_SETTEXT, part | SBT_NOBORDERS, (LPARAM)wstr);
+	SendMessage(hwndSBAR, SB_SETTEXT, part | SBT_NOBORDERS, (LPARAM)((sb_text[0] != L'\0') ? sb_text : sb_bugtext));
+}
+
+
+/* API */
+void
+ui_sb_set_text_w(wchar_t *wstr)
+{
+    if (wstr)
+	wcscpy(sb_text, wstr);
+    else
+	memset(sb_text, 0x00, sizeof(sb_text));
+    ui_sb_update_text();
 }
 
 
@@ -953,11 +966,11 @@ ui_sb_set_text_w(wchar_t *wstr)
 void
 ui_sb_set_text(char *str)
 {
-    static wchar_t wstr[512];
-
-    memset(wstr, 0x00, sizeof(wstr));
-    mbstowcs(wstr, str, strlen(str) + 1);
-    ui_sb_set_text_w(wstr);
+    if (str)
+	mbstowcs(sb_text, str, strlen(str) + 1);
+    else
+	memset(sb_text, 0x00, sizeof(sb_text));
+    ui_sb_update_text();
 }
 
 
@@ -965,9 +978,9 @@ ui_sb_set_text(char *str)
 void
 ui_sb_bugui(char *str)
 {
-    static wchar_t wstr[512];
-
-    memset(wstr, 0x00, sizeof(wstr));
-    mbstowcs(wstr, str, strlen(str) + 1);
-    ui_sb_set_text_w(wstr);
+    if (str)
+	mbstowcs(sb_bugtext, str, strlen(str) + 1);
+    else
+	memset(sb_bugtext, 0x00, sizeof(sb_bugtext));
+    ui_sb_update_text();
 }

From b02e34694384387ef378a3519c90c5777e98f932 Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Tue, 13 Apr 2021 14:07:46 -0300
Subject: [PATCH 04/23] Add DPMS support to Voodoo Banshee/3

---
 src/video/vid_voodoo_banshee.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/video/vid_voodoo_banshee.c b/src/video/vid_voodoo_banshee.c
index 5d5e1c892..7083c10ee 100644
--- a/src/video/vid_voodoo_banshee.c
+++ b/src/video/vid_voodoo_banshee.c
@@ -678,6 +678,8 @@ static void banshee_ext_outl(uint16_t addr, uint32_t val, void *p)
 
                 case DAC_dacMode:
                 banshee->dacMode = val;
+               	svga->dpms = !!(val & 0x0a);
+               	svga_recalctimings(svga);
                 break;
                 case DAC_dacAddr:
                 banshee->dacAddr = val & 0x1ff;

From 94eae848a35ea99055f6722fd554bac1f3bb40eb Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Tue, 13 Apr 2021 15:21:55 -0300
Subject: [PATCH 05/23] Add DPMS support to S3 chips

---
 src/video/vid_s3.c       | 15 +++++++++++++++
 src/video/vid_s3_virge.c | 13 +++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c
index 33f4a217e..11321dae1 100644
--- a/src/video/vid_s3.c
+++ b/src/video/vid_s3.c
@@ -2172,6 +2172,16 @@ s3_out(uint16_t addr, uint8_t val, void *p)
 		} else if (svga->seqaddr == 0xa) {
 			svga->seqregs[svga->seqaddr] = val & 0x80;
 			return;
+		} else if (s3->chip >= S3_VISION964) {
+			if (svga->seqaddr == 0x08) {
+				svga->seqregs[svga->seqaddr] = val & 0x0f;
+				return;
+			} else if ((svga->seqaddr == 0x0d) && (svga->seqregs[0x08] == 0x06)) {
+				svga->seqregs[svga->seqaddr] = val;
+				svga->dpms = ((s3->chip >= S3_VISION964) && (svga->seqregs[0x0d] & 0xf0)) || (svga->crtc[0x56] & ((s3->chip >= S3_TRIO32) ? 0x06 : 0x20));
+				svga_recalctimings(svga);
+				return;
+			}
 		}
 		break;
 		
@@ -2376,6 +2386,11 @@ s3_out(uint16_t addr, uint8_t val, void *p)
 			}
 			break;
 
+                        case 0x56:
+                        svga->dpms = ((s3->chip >= S3_VISION964) && (svga->seqregs[0x0d] & 0xf0)) || (svga->crtc[0x56] & ((s3->chip >= S3_TRIO32) ? 0x06 : 0x20));
+                        old = ~val; /* force recalc */
+                        break;
+
 			case 0x67:
 			if (s3->chip >= S3_TRIO32) {
 				switch (val >> 4)
diff --git a/src/video/vid_s3_virge.c b/src/video/vid_s3_virge.c
index bf7b64029..0752499b3 100644
--- a/src/video/vid_s3_virge.c
+++ b/src/video/vid_s3_virge.c
@@ -428,6 +428,14 @@ static void s3_virge_out(uint16_t addr, uint8_t val, void *p)
 				svga->write_bank = svga->read_bank = virge->bank << 16;
 			else
 				svga->write_bank = svga->read_bank = virge->bank << 14;
+		} else if (svga->seqaddr == 0x08) {
+			svga->seqregs[svga->seqaddr] = val & 0x0f;
+			return;
+		} else if ((svga->seqaddr == 0x0d) && (svga->seqregs[0x08] == 0x06)) {
+			svga->seqregs[svga->seqaddr] = val;
+			svga->dpms = (svga->seqregs[0x0d] & 0xf0) || (svga->crtc[0x56] & 0x06);
+			svga_recalctimings(svga);
+			return;
 		}
 		break;
                 
@@ -543,6 +551,11 @@ static void s3_virge_out(uint16_t addr, uint8_t val, void *p)
                         case 0x58: case 0x59: case 0x5a:
                         s3_virge_updatemapping(virge);
                         break;
+
+                        case 0x56:
+                        svga->dpms = (svga->seqregs[0x0d] & 0xf0) || (svga->crtc[0x56] & 0x06);
+                        old = ~val; /* force recalc */
+                        break;
                         
                         case 0x67:
                         switch (val >> 4)

From aed2b179ab233c32ce4ab96da2eb2c9a2c6a7151 Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Tue, 13 Apr 2021 15:26:12 -0300
Subject: [PATCH 06/23] Add DPMS support to Mystique

---
 src/video/vid_mga.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/video/vid_mga.c b/src/video/vid_mga.c
index 5a1d7a4b5..8ac16f2d6 100644
--- a/src/video/vid_mga.c
+++ b/src/video/vid_mga.c
@@ -691,6 +691,8 @@ mystique_out(uint16_t addr, uint8_t val, void *p)
 	case 0x3df:
 		if (mystique->crtcext_idx < 6)
 			mystique->crtcext_regs[mystique->crtcext_idx] = val;
+		if (mystique->crtcext_idx == 1)
+			svga->dpms = !!(val & 0x30);
 		if (mystique->crtcext_idx < 4) {
 			svga->fullchange = changeframecount;
 			svga_recalctimings(svga);

From 8667c8871039c3ed1fc27b724923f510e0902474 Mon Sep 17 00:00:00 2001
From: Alexander Babikov <lemondrops358@gmail.com>
Date: Tue, 13 Apr 2021 23:46:32 +0500
Subject: [PATCH 07/23] Fix HDDs on internal SCSI controllers not displaying in
 the status bar

---
 src/win/win_stbar.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/win/win_stbar.c b/src/win/win_stbar.c
index 3ae3f0f5c..e2a768570 100644
--- a/src/win/win_stbar.c
+++ b/src/win/win_stbar.c
@@ -639,7 +639,7 @@ ui_sb_update_panes(void)
 	sb_map[SB_HDD | HDD_BUS_IDE] = sb_parts;
 	sb_parts++;
     }
-    if (c_scsi && (scsi_card_current != 0)) {
+    if (c_scsi && (scsi_int || (scsi_card_current != 0))) {
 	edge += icon_width;
 	iStatusWidths[sb_parts] = edge;
 	sb_part_meanings[sb_parts] = SB_HDD | HDD_BUS_SCSI;

From 451922980fc21501f4f4e09d9b9824fd554d8e9b Mon Sep 17 00:00:00 2001
From: Alexander Babikov <lemondrops358@gmail.com>
Date: Tue, 13 Apr 2021 23:46:50 +0500
Subject: [PATCH 08/23] Handle internal SCSI controllers in the Media menu

---
 src/win/win_media_menu.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/win/win_media_menu.c b/src/win/win_media_menu.c
index dc295b309..a28499a81 100644
--- a/src/win/win_media_menu.c
+++ b/src/win/win_media_menu.c
@@ -23,6 +23,7 @@
 #include <86box/win.h>
 
 #define MACHINE_HAS_IDE	(machines[machine].flags & MACHINE_IDE_QUAD)
+#define MACHINE_HAS_SCSI	(machines[machine].flags & MACHINE_SCSI_DUAL)
 
 #define FDD_FIRST	0
 #define CDROM_FIRST	FDD_FIRST + FDD_NUM
@@ -294,7 +295,7 @@ is_valid_cdrom(int i)
 {
     if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && !MACHINE_HAS_IDE)
 	return 0;
-    if ((cdrom[i].bus_type == CDROM_BUS_SCSI) && (scsi_card_current == 0))
+    if ((cdrom[i].bus_type == CDROM_BUS_SCSI) && !MACHINE_HAS_SCSI && (scsi_card_current == 0))
 	return 0;
     return cdrom[i].bus_type != 0;
 }
@@ -304,7 +305,7 @@ is_valid_zip(int i)
 {
     if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && !MACHINE_HAS_IDE)
 	return 0;
-    if ((zip_drives[i].bus_type == ZIP_BUS_SCSI) && (scsi_card_current == 0))
+    if ((zip_drives[i].bus_type == ZIP_BUS_SCSI) && !MACHINE_HAS_SCSI && (scsi_card_current == 0))
 	return 0;
     return zip_drives[i].bus_type != 0;
 }
@@ -314,7 +315,7 @@ is_valid_mo(int i)
 {
     if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && !MACHINE_HAS_IDE)
 	return 0;
-    if ((mo_drives[i].bus_type == MO_BUS_SCSI) && (scsi_card_current == 0))
+    if ((mo_drives[i].bus_type == MO_BUS_SCSI) && !MACHINE_HAS_SCSI && (scsi_card_current == 0))
 	return 0;
     return mo_drives[i].bus_type != 0;
 }

From 202c4425a4503526b0ba8321b7840d6806c0277b Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Wed, 14 Apr 2021 16:08:20 -0300
Subject: [PATCH 09/23] Add DPMS support to ATI Mach64 (not functional at least
 on Windows XP)

---
 src/video/vid_ati_mach64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/video/vid_ati_mach64.c b/src/video/vid_ati_mach64.c
index ed554309b..0d816ba7f 100644
--- a/src/video/vid_ati_mach64.c
+++ b/src/video/vid_ati_mach64.c
@@ -2282,6 +2282,7 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *p)
                         svga->fb_only = 1;
                 else
                         svga->fb_only = 0;
+                svga->dpms = !!(mach64->crtc_gen_cntl & 0x0c);
                 svga_recalctimings(&mach64->svga);
                 break;
 

From d344fce4d46bf133ed61f40cd230e1646b5cc27c Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Wed, 14 Apr 2021 16:08:45 -0300
Subject: [PATCH 10/23] S3 DPMS shouldn't engage if both hsync and vsync are
 high

---
 src/video/vid_s3.c       | 4 ++--
 src/video/vid_s3_virge.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c
index 11321dae1..fae21a279 100644
--- a/src/video/vid_s3.c
+++ b/src/video/vid_s3.c
@@ -2178,7 +2178,7 @@ s3_out(uint16_t addr, uint8_t val, void *p)
 				return;
 			} else if ((svga->seqaddr == 0x0d) && (svga->seqregs[0x08] == 0x06)) {
 				svga->seqregs[svga->seqaddr] = val;
-				svga->dpms = ((s3->chip >= S3_VISION964) && (svga->seqregs[0x0d] & 0xf0)) || (svga->crtc[0x56] & ((s3->chip >= S3_TRIO32) ? 0x06 : 0x20));
+				svga->dpms = ((s3->chip >= S3_VISION964) && (svga->seqregs[0x0d] & 0x50)) || (svga->crtc[0x56] & ((s3->chip >= S3_TRIO32) ? 0x06 : 0x20));
 				svga_recalctimings(svga);
 				return;
 			}
@@ -2387,7 +2387,7 @@ s3_out(uint16_t addr, uint8_t val, void *p)
 			break;
 
                         case 0x56:
-                        svga->dpms = ((s3->chip >= S3_VISION964) && (svga->seqregs[0x0d] & 0xf0)) || (svga->crtc[0x56] & ((s3->chip >= S3_TRIO32) ? 0x06 : 0x20));
+                        svga->dpms = ((s3->chip >= S3_VISION964) && (svga->seqregs[0x0d] & 0x50)) || (svga->crtc[0x56] & ((s3->chip >= S3_TRIO32) ? 0x06 : 0x20));
                         old = ~val; /* force recalc */
                         break;
 
diff --git a/src/video/vid_s3_virge.c b/src/video/vid_s3_virge.c
index 0752499b3..4b37eda62 100644
--- a/src/video/vid_s3_virge.c
+++ b/src/video/vid_s3_virge.c
@@ -433,7 +433,7 @@ static void s3_virge_out(uint16_t addr, uint8_t val, void *p)
 			return;
 		} else if ((svga->seqaddr == 0x0d) && (svga->seqregs[0x08] == 0x06)) {
 			svga->seqregs[svga->seqaddr] = val;
-			svga->dpms = (svga->seqregs[0x0d] & 0xf0) || (svga->crtc[0x56] & 0x06);
+			svga->dpms = (svga->seqregs[0x0d] & 0x50) || (svga->crtc[0x56] & 0x06);
 			svga_recalctimings(svga);
 			return;
 		}
@@ -553,7 +553,7 @@ static void s3_virge_out(uint16_t addr, uint8_t val, void *p)
                         break;
 
                         case 0x56:
-                        svga->dpms = (svga->seqregs[0x0d] & 0xf0) || (svga->crtc[0x56] & 0x06);
+                        svga->dpms = (svga->seqregs[0x0d] & 0x50) || (svga->crtc[0x56] & 0x06);
                         old = ~val; /* force recalc */
                         break;
                         

From b2dd4fde07a7d9d53d1c5361ae77076671ea44d7 Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Wed, 14 Apr 2021 16:09:08 -0300
Subject: [PATCH 11/23] Fix DPMS text not going away on reset

---
 src/video/vid_svga.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/video/vid_svga.c b/src/video/vid_svga.c
index 58f361591..de84df1f0 100644
--- a/src/video/vid_svga.c
+++ b/src/video/vid_svga.c
@@ -982,6 +982,9 @@ svga_close(svga_t *svga)
     free(svga->changedvram);
     free(svga->vram);
 
+    if (svga->dpms_ui)
+	ui_sb_set_text_w(NULL);
+
     svga_pri = NULL;
 }
 

From fc50bd9bade10a2b92f557af021731088b884104 Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Wed, 14 Apr 2021 16:13:40 -0300
Subject: [PATCH 12/23] Move hard reset handling to the pc thread to avoid
 thread safety issues with GUI-triggered hard resets

---
 src/86box.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/86box.c b/src/86box.c
index 16c99851a..6fb7541a7 100644
--- a/src/86box.c
+++ b/src/86box.c
@@ -175,6 +175,7 @@ int scrnsz_y = SCREEN_RES_Y;		/* current screen size, Y */
 int	config_changed;				/* config has changed */
 int	title_update;
 int	framecountx = 0;
+int	hard_reset_pending = 0;
 
 
 int	unscaled_size_x = SCREEN_RES_X;	/* current unscaled size X */
@@ -856,9 +857,7 @@ pc_reset_hard_init(void)
 void
 pc_reset_hard(void)
 {
-	pc_reset_hard_close();
-
-	pc_reset_hard_init();
+	hard_reset_pending = 1;
 }
 
 
@@ -936,6 +935,13 @@ pc_run(void)
 {
 	wchar_t temp[200];
 
+	/* Trigger a hard reset if one is pending. */
+	if (hard_reset_pending) {
+		hard_reset_pending = 0;
+		pc_reset_hard_close();
+		pc_reset_hard_init();
+	}
+
 	/* Run a block of code. */
 	startblit();
 	cpu_exec(cpu_s->rspeed / 100);

From f0df74f248138644e0c9fbcc83962ddab544588c Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Wed, 14 Apr 2021 16:29:43 -0300
Subject: [PATCH 13/23] Fix ISABugger and POST card persisting after being
 disabled

---
 src/win/win_stbar.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/win/win_stbar.c b/src/win/win_stbar.c
index 34ccb4886..ea7be0212 100644
--- a/src/win/win_stbar.c
+++ b/src/win/win_stbar.c
@@ -426,6 +426,11 @@ StatusBarDestroyTips(void)
 void
 ui_sb_set_ready(int ready)
 {
+    if (ready == 0) {
+	ui_sb_bugui(NULL);
+	ui_sb_set_text(NULL);
+    }
+
     sb_ready = ready;
 }
 

From 96819d71feb91197fbce9d8c99dfd0be3764f36c Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Wed, 14 Apr 2021 16:32:29 -0300
Subject: [PATCH 14/23] Add DPMS as a supported feature on the EDID data

---
 src/video/vid_ddc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/video/vid_ddc.c b/src/video/vid_ddc.c
index d7daefb2e..6fc8276e4 100644
--- a/src/video/vid_ddc.c
+++ b/src/video/vid_ddc.c
@@ -148,7 +148,7 @@ ddc_init(void *i2c)
     edid->input_params = 0x0e; /* analog input; separate sync; composite sync; sync on green */
     edid->horiz_size = horiz_mm / 10;
     edid->vert_size = vert_mm / 10;
-    edid->features = 0x0b; /* RGB color; first timing is preferred; GTF/CVT */
+    edid->features = 0xeb; /* DPMS standby/suspend/active-off; RGB color; first timing is preferred; GTF/CVT */
 
     edid->red_green_lsb = 0x81;
     edid->blue_white_lsb = 0xf1;

From 7881dadd5c0b5172d4211c145d6d54fe80a68e58 Mon Sep 17 00:00:00 2001
From: RichardG867 <richardg867@gmail.com>
Date: Wed, 14 Apr 2021 17:04:08 -0300
Subject: [PATCH 15/23] Add DPMS support to Cirrus Logic

---
 src/video/vid_cl54xx.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/video/vid_cl54xx.c b/src/video/vid_cl54xx.c
index 1d42f4a2d..6a3331b1d 100644
--- a/src/video/vid_cl54xx.c
+++ b/src/video/vid_cl54xx.c
@@ -910,6 +910,13 @@ gd54xx_out(uint16_t addr, uint8_t val, void *p)
 					gd54xx_update_overlay(gd54xx);
 					break;
 
+				case 0x0e:
+					if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5429) {
+						svga->dpms = (val & 0x06) && ((svga->miscout & ((val & 0x06) << 5)) != 0xc0);
+						svga_recalctimings(svga);
+					}
+					break;
+
 				case 0x10:
 					gd543x_mmio_write(0xb8001, val, gd54xx);
 					break;

From eb06201176874a20b7b8139cfceeeaf22e524711 Mon Sep 17 00:00:00 2001
From: OBattler <oubattler@gmail.com>
Date: Thu, 15 Apr 2021 02:17:03 +0200
Subject: [PATCH 16/23] Non-REP string instructions now do segment limit and
 present bit checks.

---
 src/cpu/x86_ops_string.h | 55 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/src/cpu/x86_ops_string.h b/src/cpu/x86_ops_string.h
index fbec20dd9..54a22d4b8 100644
--- a/src/cpu/x86_ops_string.h
+++ b/src/cpu/x86_ops_string.h
@@ -5,10 +5,13 @@ static int opMOVSB_a16(uint32_t fetchdat)
         addr64 = addr64_2 = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI);
         high_page = 0;
         do_mmut_rb(cpu_state.ea_seg->base, SI, &addr64);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, DI, DI);
+
         do_mmut_wb(es, DI, &addr64_2);
         if (cpu_state.abrt) return 1;
         temp = readmemb_n(cpu_state.ea_seg->base, SI, addr64); if (cpu_state.abrt) return 1;
@@ -26,10 +29,12 @@ static int opMOVSB_a32(uint32_t fetchdat)
         addr64 = addr64_2 = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI);
         high_page = 0;
         do_mmut_rb(cpu_state.ea_seg->base, ESI, &addr64);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, EDI, EDI);
         do_mmut_wb(es, EDI, &addr64_2);
         if (cpu_state.abrt) return 1;
         temp = readmemb_n(cpu_state.ea_seg->base, ESI, addr64); if (cpu_state.abrt) return 1;
@@ -49,10 +54,12 @@ static int opMOVSW_a16(uint32_t fetchdat)
         addr64a_2[0] = addr64a_2[1] = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI + 1UL);
         high_page = 0;
         do_mmut_rw(cpu_state.ea_seg->base, SI, addr64a);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, DI, DI + 1UL);
         do_mmut_ww(es, DI, addr64a_2);
         if (cpu_state.abrt) return 1;
         temp = readmemw_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1;
@@ -71,10 +78,12 @@ static int opMOVSW_a32(uint32_t fetchdat)
         addr64a_2[0] = addr64a_2[1] = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI + 1UL);
         high_page = 0;
         do_mmut_rw(cpu_state.ea_seg->base, ESI, addr64a);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 1UL);
         do_mmut_ww(es, EDI, addr64a_2);
         if (cpu_state.abrt) return 1;
         temp = readmemw_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1;
@@ -94,10 +103,12 @@ static int opMOVSL_a16(uint32_t fetchdat)
         addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI + 3UL);
         high_page = 0;
         do_mmut_rl(cpu_state.ea_seg->base, SI, addr64a);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, DI, DI + 3UL);
         do_mmut_wl(es, DI, addr64a_2);
         if (cpu_state.abrt) return 1;
         temp = readmeml_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1;
@@ -116,10 +127,12 @@ static int opMOVSL_a32(uint32_t fetchdat)
         addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI + 3UL);
         high_page = 0;
         do_mmut_rl(cpu_state.ea_seg->base, ESI, addr64a);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 3UL);
         do_mmut_wl(es, EDI, addr64a_2);
         if (cpu_state.abrt) return 1;
         temp = readmeml_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1;
@@ -139,10 +152,12 @@ static int opCMPSB_a16(uint32_t fetchdat)
         addr64 = addr64_2 = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI);
         high_page = uncached = 0;
         do_mmut_rb(cpu_state.ea_seg->base, SI, &addr64);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, DI, DI);
         do_mmut_rb2(es, DI, &addr64_2);
         if (cpu_state.abrt) return 1;
         src = readmemb_n(cpu_state.ea_seg->base, SI, addr64);        if (cpu_state.abrt) return 1;
@@ -165,10 +180,12 @@ static int opCMPSB_a32(uint32_t fetchdat)
         addr64 = addr64_2 = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI);
         high_page = uncached = 0;
         do_mmut_rb(cpu_state.ea_seg->base, ESI, &addr64);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, EDI, EDI);
         do_mmut_rb2(es, EDI, &addr64_2);
         if (cpu_state.abrt) return 1;
         src = readmemb_n(cpu_state.ea_seg->base, ESI, addr64);        if (cpu_state.abrt) return 1;
@@ -193,10 +210,12 @@ static int opCMPSW_a16(uint32_t fetchdat)
         addr64a_2[0] = addr64a_2[1] = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI + 1UL);
         high_page = uncached = 0;
         do_mmut_rw(cpu_state.ea_seg->base, SI, addr64a);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, DI, DI + 1UL);
         do_mmut_rw2(es, DI, addr64a_2);
         if (cpu_state.abrt) return 1;
         src = readmemw_n(cpu_state.ea_seg->base, SI, addr64a);        if (cpu_state.abrt) return 1;
@@ -220,10 +239,12 @@ static int opCMPSW_a32(uint32_t fetchdat)
         addr64a_2[0] = addr64a_2[1] = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI + 1UL);
         high_page = uncached = 0;
         do_mmut_rw(cpu_state.ea_seg->base, ESI, addr64a);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, EDI, EDI + 1UL);
         do_mmut_rw2(es, EDI, addr64a_2);
         if (cpu_state.abrt) return 1;
         src = readmemw_n(cpu_state.ea_seg->base, ESI, addr64a);        if (cpu_state.abrt) return 1;
@@ -248,10 +269,12 @@ static int opCMPSL_a16(uint32_t fetchdat)
         addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI + 3UL);
         high_page = uncached = 0;
         do_mmut_rl(cpu_state.ea_seg->base, SI, addr64a);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, DI, DI + 3UL);
         do_mmut_rl2(es, DI, addr64a_2);
         if (cpu_state.abrt) return 1;
         src = readmeml_n(cpu_state.ea_seg->base, SI, addr64a);        if (cpu_state.abrt) return 1;
@@ -275,10 +298,12 @@ static int opCMPSL_a32(uint32_t fetchdat)
         addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI + 3UL);
         high_page = uncached = 0;
         do_mmut_rl(cpu_state.ea_seg->base, ESI, addr64a);
         if (cpu_state.abrt) return 1;
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, EDI, EDI + 3UL);
         do_mmut_rl2(es, EDI, addr64a_2);
         if (cpu_state.abrt) return 1;
         src = readmeml_n(cpu_state.ea_seg->base, ESI, addr64a);        if (cpu_state.abrt) return 1;
@@ -298,6 +323,7 @@ static int opCMPSL_a32(uint32_t fetchdat)
 static int opSTOSB_a16(uint32_t fetchdat)
 {
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, DI, DI);
         writememb(es, DI, AL);                  if (cpu_state.abrt) return 1;
         if (cpu_state.flags & D_FLAG) DI--;
         else                          DI++;
@@ -308,6 +334,7 @@ static int opSTOSB_a16(uint32_t fetchdat)
 static int opSTOSB_a32(uint32_t fetchdat)
 {
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, EDI, EDI);
         writememb(es, EDI, AL);                 if (cpu_state.abrt) return 1;
         if (cpu_state.flags & D_FLAG) EDI--;
         else                          EDI++;
@@ -319,6 +346,7 @@ static int opSTOSB_a32(uint32_t fetchdat)
 static int opSTOSW_a16(uint32_t fetchdat)
 {
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, DI, DI + 1UL);
         writememw(es, DI, AX);                  if (cpu_state.abrt) return 1;
         if (cpu_state.flags & D_FLAG) DI -= 2;
         else                          DI += 2;
@@ -329,6 +357,7 @@ static int opSTOSW_a16(uint32_t fetchdat)
 static int opSTOSW_a32(uint32_t fetchdat)
 {
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 1UL);
         writememw(es, EDI, AX);                 if (cpu_state.abrt) return 1;
         if (cpu_state.flags & D_FLAG) EDI -= 2;
         else                          EDI += 2;
@@ -340,6 +369,7 @@ static int opSTOSW_a32(uint32_t fetchdat)
 static int opSTOSL_a16(uint32_t fetchdat)
 {
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, DI, DI + 3UL);
         writememl(es, DI, EAX);                 if (cpu_state.abrt) return 1;
         if (cpu_state.flags & D_FLAG) DI -= 4;
         else                          DI += 4;
@@ -350,6 +380,7 @@ static int opSTOSL_a16(uint32_t fetchdat)
 static int opSTOSL_a32(uint32_t fetchdat)
 {
         SEG_CHECK_WRITE(&cpu_state.seg_es);
+        CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 3UL);
         writememl(es, EDI, EAX);                if (cpu_state.abrt) return 1;
         if (cpu_state.flags & D_FLAG) EDI -= 4;
         else                          EDI += 4;
@@ -364,6 +395,7 @@ static int opLODSB_a16(uint32_t fetchdat)
         uint8_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI);
         temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
         AL = temp;
         if (cpu_state.flags & D_FLAG) SI--;
@@ -377,6 +409,7 @@ static int opLODSB_a32(uint32_t fetchdat)
         uint8_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI);
         temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
         AL = temp;
         if (cpu_state.flags & D_FLAG) ESI--;
@@ -391,6 +424,7 @@ static int opLODSW_a16(uint32_t fetchdat)
         uint16_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI + 1UL);
         temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
         AX = temp;
         if (cpu_state.flags & D_FLAG) SI -= 2;
@@ -404,6 +438,7 @@ static int opLODSW_a32(uint32_t fetchdat)
         uint16_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI + 1UL);
         temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
         AX = temp;
         if (cpu_state.flags & D_FLAG) ESI -= 2;
@@ -418,6 +453,7 @@ static int opLODSL_a16(uint32_t fetchdat)
         uint32_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI + 3UL);
         temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
         EAX = temp;
         if (cpu_state.flags & D_FLAG) SI -= 4;
@@ -431,6 +467,7 @@ static int opLODSL_a32(uint32_t fetchdat)
         uint32_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI + 3UL);
         temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
         EAX = temp;
         if (cpu_state.flags & D_FLAG) ESI -= 4;
@@ -446,6 +483,7 @@ static int opSCASB_a16(uint32_t fetchdat)
         uint8_t temp;
 
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, DI, DI);
         temp = readmemb(es, DI);        if (cpu_state.abrt) return 1;
         setsub8(AL, temp);
         if (cpu_state.flags & D_FLAG) DI--;
@@ -459,6 +497,7 @@ static int opSCASB_a32(uint32_t fetchdat)
         uint8_t temp;
 
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, EDI, EDI);
         temp = readmemb(es, EDI);       if (cpu_state.abrt) return 1;
         setsub8(AL, temp);
         if (cpu_state.flags & D_FLAG) EDI--;
@@ -473,6 +512,7 @@ static int opSCASW_a16(uint32_t fetchdat)
         uint16_t temp;
 
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, DI, DI + 1UL);
         temp = readmemw(es, DI);       if (cpu_state.abrt) return 1;
         setsub16(AX, temp);
         if (cpu_state.flags & D_FLAG) DI -= 2;
@@ -486,6 +526,7 @@ static int opSCASW_a32(uint32_t fetchdat)
         uint16_t temp;
 
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, EDI, EDI + 1UL);
         temp = readmemw(es, EDI);      if (cpu_state.abrt) return 1;
         setsub16(AX, temp);
         if (cpu_state.flags & D_FLAG) EDI -= 2;
@@ -500,6 +541,7 @@ static int opSCASL_a16(uint32_t fetchdat)
         uint32_t temp;
 
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, DI, DI + 3UL);
         temp = readmeml(es, DI);       if (cpu_state.abrt) return 1;
         setsub32(EAX, temp);
         if (cpu_state.flags & D_FLAG) DI -= 4;
@@ -513,6 +555,7 @@ static int opSCASL_a32(uint32_t fetchdat)
         uint32_t temp;
 
         SEG_CHECK_READ(&cpu_state.seg_es);
+        CHECK_READ(&cpu_state.seg_es, EDI, EDI + 3UL);
         temp = readmeml(es, EDI);      if (cpu_state.abrt) return 1;
         setsub32(EAX, temp);
         if (cpu_state.flags & D_FLAG) EDI -= 4;
@@ -530,6 +573,7 @@ static int opINSB_a16(uint32_t fetchdat)
 
         SEG_CHECK_WRITE(&cpu_state.seg_es);
         check_io_perm(DX);
+        CHECK_WRITE(&cpu_state.seg_es, DI, DI);
         high_page = 0;
 	do_mmut_wb(es, DI, &addr64);                      if (cpu_state.abrt) return 1;
         temp = inb(DX);
@@ -549,6 +593,7 @@ static int opINSB_a32(uint32_t fetchdat)
         SEG_CHECK_WRITE(&cpu_state.seg_es);
         check_io_perm(DX);
         high_page = 0;
+        CHECK_WRITE(&cpu_state.seg_es, EDI, EDI);
 	do_mmut_wb(es, EDI, &addr64);                     if (cpu_state.abrt) return 1;
         temp = inb(DX);
         writememb_n(es, EDI, addr64, temp);               if (cpu_state.abrt) return 1;
@@ -568,6 +613,7 @@ static int opINSW_a16(uint32_t fetchdat)
         SEG_CHECK_WRITE(&cpu_state.seg_es);
         check_io_perm(DX);
         check_io_perm(DX + 1);
+        CHECK_WRITE(&cpu_state.seg_es, DI, DI + 1UL);
         high_page = 0;
 	do_mmut_ww(es, DI, addr64a);                      if (cpu_state.abrt) return 1;
         temp = inw(DX);
@@ -588,6 +634,7 @@ static int opINSW_a32(uint32_t fetchdat)
         high_page = 0;
         check_io_perm(DX);
         check_io_perm(DX + 1);
+        CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 1UL);
 	do_mmut_ww(es, EDI, addr64a);                     if (cpu_state.abrt) return 1;
         temp = inw(DX);
         writememw_n(es, EDI, addr64a, temp);              if (cpu_state.abrt) return 1;
@@ -609,6 +656,7 @@ static int opINSL_a16(uint32_t fetchdat)
         check_io_perm(DX + 1);
         check_io_perm(DX + 2);
         check_io_perm(DX + 3);
+        CHECK_WRITE(&cpu_state.seg_es, DI, DI + 3UL);
         high_page = 0;
 	do_mmut_wl(es, DI, addr64a);                      if (cpu_state.abrt) return 1;
         temp = inl(DX);
@@ -630,6 +678,7 @@ static int opINSL_a32(uint32_t fetchdat)
         check_io_perm(DX + 1);
         check_io_perm(DX + 2);
         check_io_perm(DX + 3);
+        CHECK_WRITE(&cpu_state.seg_es, EDI, EDI + 3UL);
         high_page = 0;
 	do_mmut_wl(es, DI, addr64a);                      if (cpu_state.abrt) return 1;
         temp = inl(DX);
@@ -646,6 +695,7 @@ static int opOUTSB_a16(uint32_t fetchdat)
         uint8_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI);
         temp = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
         check_io_perm(DX);
         if (cpu_state.flags & D_FLAG) SI--;
@@ -660,6 +710,7 @@ static int opOUTSB_a32(uint32_t fetchdat)
         uint8_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI);
         temp = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
         check_io_perm(DX);
         if (cpu_state.flags & D_FLAG) ESI--;
@@ -675,6 +726,7 @@ static int opOUTSW_a16(uint32_t fetchdat)
         uint16_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI + 1UL);
         temp = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
         check_io_perm(DX);
         check_io_perm(DX + 1);
@@ -690,6 +742,7 @@ static int opOUTSW_a32(uint32_t fetchdat)
         uint16_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI + 1UL);
         temp = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
         check_io_perm(DX);
         check_io_perm(DX + 1);
@@ -706,6 +759,7 @@ static int opOUTSL_a16(uint32_t fetchdat)
         uint32_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, SI, SI + 3UL);
         temp = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) return 1;
         check_io_perm(DX);
         check_io_perm(DX + 1);
@@ -723,6 +777,7 @@ static int opOUTSL_a32(uint32_t fetchdat)
         uint32_t temp;
 
         SEG_CHECK_READ(cpu_state.ea_seg);
+        CHECK_READ(cpu_state.ea_seg, ESI, ESI + 3UL);
         temp = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) return 1;
         check_io_perm(DX);
         check_io_perm(DX + 1);

From cf67dc4fc54c5761a895556654ed4d9883b2b4b7 Mon Sep 17 00:00:00 2001
From: TC1995 <mariogplayer90@gmail.com>
Date: Thu, 15 Apr 2021 02:28:32 +0200
Subject: [PATCH 17/23] Fixed "purple pixels" under Win95 using the built-in S3
 928 driver.

---
 src/video/vid_s3.c | 47 ++++++++++++++++++++++++----------------------
 1 file changed, 25 insertions(+), 22 deletions(-)

diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c
index fae21a279..d82a52f7d 100644
--- a/src/video/vid_s3.c
+++ b/src/video/vid_s3.c
@@ -1006,17 +1006,21 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
 						s3_accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
 						break;
 					case 0x200:
-						if (s3->accel.cmd & 0x1000)
-							s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[1] | (s3->accel.pix_trans[0] << 8), s3);
-						else
-							s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
+						if (s3->chip == S3_86C928) /*Windows 95's built-in driver expects this to be loaded regardless of the byte swap bit (0xE2E9)*/
+							s3_accel_out_pixtrans_w(s3, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8));
+						else {
+							if (s3->accel.cmd & 0x1000)
+								s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[1] | (s3->accel.pix_trans[0] << 8), s3);
+							else
+								s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
+						}
 						break;
 					case 0x400:
 						if (svga->crtc[0x53] & 0x08)
 							s3_accel_start(4, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
 						break;
 				}
-			}			
+			}
 		}
 		break;
 	case 0xe14a: case 0xe2ea:
@@ -1052,7 +1056,7 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
 						}
 						break;
 				}
-			}		
+			}
 		} else {
 			if (s3->accel.cmd & 0x100) {
 				switch (s3->accel.cmd & 0x600) {
@@ -1060,11 +1064,15 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
 						s3_accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
 						break;	
 					case 0x200:
-						if (s3->accel.cmd & 0x1000) 
-							s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), s3);
-						else
-							s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
-						break;						
+						if (s3->chip == S3_86C928) /*Windows 95's built-in S3 928 driver expects the upper 16 bits to be loaded instead of the whole 32-bit one, regardless of the byte swap bit (0xE2EB)*/
+							s3_accel_out_pixtrans_w(s3, s3->accel.pix_trans[2] | (s3->accel.pix_trans[3] << 8));
+						else {
+							if (s3->accel.cmd & 0x1000) 
+								s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), s3);
+							else
+								s3_accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
+						}
+						break;
 					case 0x400:
 						s3_accel_start(4, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
 						break;
@@ -2710,7 +2718,7 @@ s3_updatemapping(s3_t *s3)
 {
 	svga_t *svga = &s3->svga;
 
-	if (!(s3->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
+	if (s3->pci && !(s3->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
 	{
 		mem_mapping_disable(&svga->mapping);
 		mem_mapping_disable(&s3->linear_mapping);
@@ -2787,7 +2795,6 @@ s3_updatemapping(s3_t *s3)
 				}
 				break;
 			}
-
 			s3->linear_base &= ~(s3->linear_size - 1);
 			if (s3->linear_base == 0xa0000) {
 				mem_mapping_disable(&s3->linear_mapping);
@@ -2803,9 +2810,8 @@ s3_updatemapping(s3_t *s3)
 					s3->linear_base &= 0xfe000000;
 				mem_mapping_set_addr(&s3->linear_mapping, s3->linear_base, s3->linear_size);
 			}
-		} else {
+		} else
 			mem_mapping_disable(&s3->linear_mapping);
-		}
 
 		/* Memory mapped I/O. */
 		if ((svga->crtc[0x53] & 0x10) || (s3->accel.advfunc_cntl & 0x20)) {
@@ -2818,9 +2824,8 @@ s3_updatemapping(s3_t *s3)
 			} else {
 				mem_mapping_enable(&s3->mmio_mapping);
 			}
-		} else {
+		} else
 			mem_mapping_disable(&s3->mmio_mapping);
-		}
 		
 		/* New MMIO. */
 		if (svga->crtc[0x53] & 0x08) {
@@ -5862,7 +5867,7 @@ static void *s3_init(const device_t *info)
 	else if (s3->vlb)
 		svga->crtc[0x36] = 1 | (3 << 2) | (1 << 4);
 	else
-		svga->crtc[0x36] = 3 | (3 << 2) | (1 << 4);
+		svga->crtc[0x36] = 3;
 	
 	if (chip >= S3_86C928)
 		svga->crtc[0x36] |= (vram_sizes[vram] << 5);
@@ -6021,8 +6026,7 @@ static void *s3_init(const device_t *info)
 		case S3_PHOENIX_VISION868:
 			svga->decode_mask = (4 << 20) - 1;
 			s3->id = 0xe1; /*Vision868*/
-			s3->id_ext = 0x90; 
-			s3->id_ext_pci = 0x80;
+			s3->id_ext = s3->id_ext_pci = 0x80;
 			s3->packed_mmio = 1;
 			if (s3->pci) {
 				svga->crtc[0x53] = 0x18;
@@ -6045,8 +6049,7 @@ static void *s3_init(const device_t *info)
 		case S3_DIAMOND_STEALTH_SE:
 			svga->decode_mask = (4 << 20) - 1;
 			s3->id = 0xe1; /*Trio32*/
-			s3->id_ext = 0x10;
-			s3->id_ext_pci = 0x11;
+			s3->id_ext = s3->id_ext_pci = 0x10;
 			s3->packed_mmio = 1;
 
 			svga->clock_gen = s3;

From 3edf20b48b0625c9a453a5718d735342b0de98ec Mon Sep 17 00:00:00 2001
From: TC1995 <mariogplayer90@gmail.com>
Date: Thu, 15 Apr 2021 16:42:40 +0200
Subject: [PATCH 18/23] Fix accidental horizontal bug in the 8bpp portion of
 the S3 recalc timing function using the 80x (1280x1024x8bpp).

---
 src/video/vid_s3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c
index d82a52f7d..8fb271bbc 100644
--- a/src/video/vid_s3.c
+++ b/src/video/vid_s3.c
@@ -2560,7 +2560,7 @@ static void s3_recalctimings(svga_t *svga)
 				if (s3->chip == S3_86C928) {
 					if (s3->width == 2048 || s3->width == 1280 || s3->width == 1600)
 						svga->hdisp *= 2;
-				} else {
+				} else if ((s3->chip != S3_86C801) && (s3->chip != S3_86C805)) {
 					if (s3->width == 1280 || s3->width == 1600)
 						svga->hdisp *= 2;					
 				}

From 8e3b09f32348d8463fb3451903e01e1aa4f30dd8 Mon Sep 17 00:00:00 2001
From: nerd73 <nerd7b@gmail.com>
Date: Thu, 15 Apr 2021 21:38:03 -0600
Subject: [PATCH 19/23] Various 486 improvements

- Added SL-Enhanced versions of Intel 486 CPUs and Enhanced AMD Am486DX2/DX4 CPUs
- Cleaned up the 486 CPU types and updated intel_4x0.c to reflect this
- Fixed some incorrect EDX reset and CPUID values
- Blacklisted non-SMM capable 486 CPUs on the Soyo 4SA2 motherboard
- Merged the non-OverDrive and OverDrive Intel DX4s because of further research confirming them to be functionally identical
- Removed SMM support on early 486 CPUs
---
 src/chipset/intel_4x0.c     |   8 +--
 src/cpu/cpu.c               |  60 ++++------------
 src/cpu/cpu.h               |  16 ++---
 src/cpu/cpu_table.c         | 139 ++++++++++++++++++++++++------------
 src/cpu/x86.c               |   2 +-
 src/device/keyboard_at.c    |   2 +-
 src/machine/machine.c       |   2 +-
 src/machine/machine_table.c |   2 +-
 8 files changed, 120 insertions(+), 111 deletions(-)

diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c
index 2f0c7cc39..d8bb5582e 100644
--- a/src/chipset/intel_4x0.c
+++ b/src/chipset/intel_4x0.c
@@ -1303,13 +1303,13 @@ static void
 		regs[0x0d] = 0x20;
 		/* According to information from FreeBSD 3.x source code:
 			0x00 = 486DX, 0x20 = 486SX, 0x40 = 486DX2 or 486DX4, 0x80 = Pentium OverDrive. */
-		if (is486sx)
+		if (!(hasfpu) && (cpu_multi = 1))
 			regs[0x50] = 0x20;
-		else if (is486sx2)
+		else if (!(hasfpu) && (cpu_multi = 2))
 			regs[0x50] = 0x60;	/* Guess based on the SX, DX, and DX2 values. */
-		else if (is486dx)
+		else if (hasfpu && (cpu_multi = 1))
 			regs[0x50] = 0x00;
-		else if (is486dx2 || isdx4)
+		else if (hasfpu && (cpu_multi >= 2) && !(cpu_s->cpu_type == CPU_P24T))
 			regs[0x50] = 0x40;
 		else
 			regs[0x50] = 0x80;	/* Pentium OverDrive. */
diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c
index 191754d7f..ae71bae33 100644
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -108,9 +108,9 @@ int		isa_cycles,
 		cpu_override, cpu_effective, cpu_multi, cpu_16bitbus, cpu_64bitbus, cpu_busspeed,
 		cpu_cyrix_alignment, CPUID,
 
- 		is286, is386, is486 = 1, is486sx, is486dx, is486sx2, is486dx2, isdx4,
+ 		is286, is386, is486 = 1,
 		cpu_isintel, cpu_iscyrix, hascache, isibm486, israpidcad, is_vpc,
-		is_am486, is_486_org, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
+		is_am486, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
 
 		timing_rr, timing_mr, timing_mrl, timing_rm, timing_rml,
 		timing_mm, timing_mml, timing_bt, timing_bnt,
@@ -368,23 +368,16 @@ cpu_set(void)
     isibm486     = (cpu_s->cpu_type == CPU_IBM386SLC) || (cpu_s->cpu_type == CPU_IBM486SLC) ||
 		   (cpu_s->cpu_type == CPU_IBM486BL);
     is486        = (cpu_s->cpu_type >= CPU_RAPIDCAD);
-    is486sx      = (cpu_s->cpu_type >= CPU_i486SX) && (cpu_s->cpu_type < CPU_i486SX2);
-    is486sx2     = (cpu_s->cpu_type >= CPU_i486SX2) && (cpu_s->cpu_type < CPU_i486DX);
-    is486dx      = (cpu_s->cpu_type >= CPU_i486DX) && (cpu_s->cpu_type < CPU_i486DX2);
-    is486dx2     = (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_iDX4);	
-    isdx4        = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP);
-    is_486_org   = (cpu_s->cpu_type == CPU_i486SX) || (cpu_s->cpu_type == CPU_i486DX) ||
-		   (cpu_s->cpu_type == CPU_Am486SX) || (cpu_s->cpu_type == CPU_Am486DX);
-    is_am486     = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type >= CPU_Am486SX) && (cpu_s->cpu_type <= CPU_Am5x86);
+    is_am486     = (cpu_s->cpu_type == CPU_ENH_Am486DX);
 
     cpu_isintel = !strcmp(cpu_f->manufacturer, "Intel");
     cpu_iscyrix = !strcmp(cpu_f->manufacturer, "Cyrix");
 
-    /* The 486DX2 and iDX4 have the same SMM save state table layout as Pentiums,
+    /* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums,
        and the WinChip datasheet claims those are Pentium-compatible as well. */
-    is_pentium   = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) ||
+    is_pentium   = (cpu_isintel && (((cpu_s->cpu_type >= CPU_i486SX_SLENH)) && (cpu_s->cpu_type < CPU_PENTIUMPRO))) ||
 		   !strcmp(cpu_f->manufacturer, "IDT");
-    is_k5        = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_Am5x86);
+    is_k5        = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_ENH_Am486DX);
     is_k6        = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD");
     /* The Samuel 2 datasheet claims it's Celeron-compatible. */
     is_p6        = (cpu_isintel && (cpu_s->cpu_type >= CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "VIA");
@@ -758,21 +751,17 @@ cpu_set(void)
 		timing_misaligned		=   3;
 		break;
 
-	case CPU_iDX4:
+	case CPU_i486SX_SLENH:
+	case CPU_i486DX_SLENH:
 		cpu_features = CPU_FEATURE_CR4 | CPU_FEATURE_VME;
 		cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_VME;
 		/* FALLTHROUGH */
 	case CPU_RAPIDCAD:
 	case CPU_i486SX:
-	case CPU_i486SX2:
 	case CPU_i486DX:
-	case CPU_i486DX2:
 	case CPU_Am486SX:
-	case CPU_Am486SX2:
 	case CPU_Am486DX:
-	case CPU_Am486DX2:
-	case CPU_Am486DX4:
-	case CPU_Am5x86:
+	case CPU_ENH_Am486DX:
 		/*AMD timing identical to Intel*/
 #ifdef USE_DYNAREC
 		x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
@@ -815,8 +804,6 @@ cpu_set(void)
 
 	case CPU_Cx486S:
 	case CPU_Cx486DX:
-	case CPU_Cx486DX2:
-	case CPU_Cx486DX4:
 #ifdef USE_DYNAREC
 		x86_setopcodes(ops_386, ops_c486_0f, dynarec_ops_386, dynarec_ops_c486_0f);
 #else
@@ -1468,9 +1455,7 @@ void
 cpu_CPUID(void)
 {
     switch (cpu_s->cpu_type) {
-	case CPU_RAPIDCAD:
-	case CPU_i486DX:
-	case CPU_i486DX2:
+	case CPU_i486SX_SLENH:
 		if (!EAX) {
 			EAX = 0x00000001;
 			EBX = 0x756e6547;
@@ -1479,12 +1464,12 @@ cpu_CPUID(void)
 		} else if (EAX == 1) {
 			EAX = CPUID;
 			EBX = ECX = 0;
-			EDX = CPUID_FPU;	/*FPU*/
+			EDX = CPUID_VME;
 		} else
 			EAX = EBX = ECX = EDX = 0;
 		break;
 
-	case CPU_iDX4:
+	case CPU_i486DX_SLENH:
 		if (!EAX) {
 			EAX = 0x00000001;
 			EBX = 0x756e6547;
@@ -1497,25 +1482,8 @@ cpu_CPUID(void)
 		} else
 			EAX = EBX = ECX = EDX = 0;
 		break;
-
-	case CPU_Am486SX:
-	case CPU_Am486SX2:
-		if (!EAX) {
-			EAX = 1;
-			EBX = 0x68747541;
-			ECX = 0x444D4163;
-			EDX = 0x69746E65;
-		} else if (EAX == 1) {
-			EAX = CPUID;
-			EBX = ECX = EDX = 0;	/*No FPU*/
-		} else
-			EAX = EBX = ECX = EDX = 0;
-		break;
-
-	case CPU_Am486DX:
-	case CPU_Am486DX2:
-	case CPU_Am486DX4:
-	case CPU_Am5x86:
+		
+	case CPU_ENH_Am486DX:
 		if (!EAX) {
 			EAX = 1;
 			EBX = 0x68747541;
diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h
index 2a9996a06..f35ae54d7 100644
--- a/src/cpu/cpu.h
+++ b/src/cpu/cpu.h
@@ -50,18 +50,12 @@ enum {
     CPU_i486SX,		/* 486 class CPUs */
     CPU_Am486SX,
     CPU_Cx486S,
-    CPU_i486SX2,
-    CPU_Am486SX2,
     CPU_i486DX,
     CPU_Am486DX,
     CPU_Cx486DX,
-    CPU_i486DX2,
-    CPU_Am486DX2,
-    CPU_Cx486DX2,
-    CPU_iDX4,
-    CPU_Am486DX4,
-    CPU_Cx486DX4,
-    CPU_Am5x86,
+    CPU_i486SX_SLENH,
+    CPU_i486DX_SLENH,
+    CPU_ENH_Am486DX,
     CPU_Cx5x86,
     CPU_P24T,
     CPU_WINCHIP,	/* 586 class CPUs */
@@ -482,8 +476,8 @@ extern double   fpu_multi;
 extern int	cpu_cyrix_alignment;	/*Cyrix 5x86/6x86 only has data misalignment
 					  penalties when crossing 8-byte boundaries*/
 
-extern int	is8086,	is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4;
-extern int	is_am486, is_486_org, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
+extern int	is8086,	is286, is386, is486;
+extern int	is_am486, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
 extern int	hascache;
 extern int	isibm486;
 extern int	is_rapidcad;
diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c
index 407021c0f..f5da157b7 100644
--- a/src/cpu/cpu_table.c
+++ b/src/cpu/cpu_table.c
@@ -313,17 +313,29 @@ const cpu_family_t cpu_families[] = {
 		{"16",            CPU_i486SX,     fpus_486sx,  16000000, 1,  5000, 0x420,        0, 0, CPU_SUPPORTS_DYNAREC,  3, 3,3,3,  2},
 		{"20",            CPU_i486SX,     fpus_486sx,  20000000, 1,  5000, 0x420,        0, 0, CPU_SUPPORTS_DYNAREC,  4, 4,3,3,  3},
 		{"25",            CPU_i486SX,     fpus_486sx,  25000000, 1,  5000, 0x422,        0, 0, CPU_SUPPORTS_DYNAREC,  4, 4,3,3,  3},
-		{"33",            CPU_i486SX,     fpus_486sx,  33333333, 1,  5000, 0x42a,        0, 0, CPU_SUPPORTS_DYNAREC,  6, 6,3,3,  4},
+		{"33",            CPU_i486SX,     fpus_486sx,  33333333, 1,  5000, 0x422,        0, 0, CPU_SUPPORTS_DYNAREC,  6, 6,3,3,  4},
 		{"", 0}
 	}
-    }, {
+    },
+	{
+	.package = CPU_PKG_SOCKET1,
+	.manufacturer = "Intel",
+	.name = "i486SX (SL-Enhanced)",
+	.internal_name = "i486sx_slenh",
+	.cpus = (const CPU[]) {
+		{"25",            CPU_i486SX_SLENH,     fpus_486sx,  25000000, 1,  5000, 0x423,    0x423, 0, CPU_SUPPORTS_DYNAREC,  4, 4,3,3,  3},
+		{"33",            CPU_i486SX_SLENH,     fpus_486sx,  33333333, 1,  5000, 0x42a,    0x42a, 0, CPU_SUPPORTS_DYNAREC,  6, 6,3,3,  4},
+		{"", 0}
+	}
+    },    
+	{
 	.package = CPU_PKG_SOCKET1,
 	.manufacturer = "Intel",
 	.name = "i486SX2",
 	.internal_name = "i486sx2",
 	.cpus = (const CPU[]) {
-		{"50",           CPU_i486SX2,    fpus_486sx,  50000000, 2,  5000, 0x45b,        0, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  6},
-		{"66 (Q0569)",   CPU_i486SX2,    fpus_486sx,  66666666, 2,  5000, 0x45b,        0, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  8},
+		{"50",           CPU_i486SX_SLENH,    fpus_486sx,  50000000, 2,  5000, 0x45b,    0x45b, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  6},
+		{"66 (Q0569)",   CPU_i486SX_SLENH,    fpus_486sx,  66666666, 2,  5000, 0x45b,    0x45b, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  8},
 		{"", 0}
 	}
     }, {
@@ -333,49 +345,62 @@ const cpu_family_t cpu_families[] = {
 	.internal_name = "i486dx",
 	.cpus = (const CPU[]) {
 		{"25",            CPU_i486DX,  fpus_internal,  25000000, 1,  5000, 0x404,        0, 0, CPU_SUPPORTS_DYNAREC,  4, 4,3,3,  3},
-		{"33",            CPU_i486DX,  fpus_internal,  33333333, 1,  5000, 0x414,        0, 0, CPU_SUPPORTS_DYNAREC,  6, 6,3,3,  4},
+		{"33",            CPU_i486DX,  fpus_internal,  33333333, 1,  5000, 0x404,        0, 0, CPU_SUPPORTS_DYNAREC,  6, 6,3,3,  4},
 		{"50",            CPU_i486DX,  fpus_internal,  50000000, 1,  5000, 0x411,        0, 0, CPU_SUPPORTS_DYNAREC,  8, 8,4,4,  6},
 		{"", 0}
 	}
+    }, 
+     {
+	.package = CPU_PKG_SOCKET1,
+	.manufacturer = "Intel",
+	.name = "i486DX (SL-Enhanced)",
+	.internal_name = "i486dx_slenh",
+	.cpus = (const CPU[]) {
+		{"33",            CPU_i486DX_SLENH,  fpus_internal,  33333333, 1,  5000, 0x414,    0x414, 0, CPU_SUPPORTS_DYNAREC,  6, 6,3,3,  4},
+		{"50",            CPU_i486DX_SLENH,  fpus_internal,  50000000, 1,  5000, 0x414,    0x414, 0, CPU_SUPPORTS_DYNAREC,  8, 8,4,4,  6},
+		{"", 0}
+	}
     }, {
 	.package = CPU_PKG_SOCKET1,
 	.manufacturer = "Intel",
 	.name = "i486DX2",
 	.internal_name = "i486dx2",
 	.cpus = (const CPU[]) {
-		{"40",           CPU_i486DX2, fpus_internal,  40000000, 2,  5000, 0x430,    0x430, 0, CPU_SUPPORTS_DYNAREC,  7, 7,6,6,  5},
-		{"50",           CPU_i486DX2, fpus_internal,  50000000, 2,  5000, 0x433,    0x433, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  6},
-		{"66",           CPU_i486DX2, fpus_internal,  66666666, 2,  5000, 0x435,    0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6,  8},
+		{"40",           CPU_i486DX, fpus_internal,  40000000, 2,  5000, 0x430,        0, 0, CPU_SUPPORTS_DYNAREC,  7, 7,6,6,  5},
+		{"50",           CPU_i486DX, fpus_internal,  50000000, 2,  5000, 0x433,        0, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  6},
+		{"66",           CPU_i486DX, fpus_internal,  66666666, 2,  5000, 0x433,        0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6,  8},
 		{"", 0}
 	}
-    }, {
+    }, 
+ {
+	.package = CPU_PKG_SOCKET1,
+	.manufacturer = "Intel",
+	.name = "i486DX2 (SL-Enhanced)",
+	.internal_name = "i486dx2_slenh",
+	.cpus = (const CPU[]) {
+		{"40",           CPU_i486DX_SLENH, fpus_internal,  40000000, 2,  5000, 0x435,    0x435, 0, CPU_SUPPORTS_DYNAREC,  7, 7,6,6,  5},		
+		{"50",           CPU_i486DX_SLENH, fpus_internal,  50000000, 2,  5000, 0x435,    0x435, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  6},
+		{"66",           CPU_i486DX_SLENH, fpus_internal,  66666666, 2,  5000, 0x435,    0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6,  8},
+		{"", 0}
+	}
+    },     {
 	.package = CPU_PKG_SOCKET3_PC330,
 	.manufacturer = "Intel",
 	.name = "i486DX2",
 	.internal_name = "i486dx2_pc330",
 	.cpus = (const CPU[]) {
-		{"50",           CPU_i486DX2, fpus_internal,  50000000, 2,  5000, 0x470,    0x470, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  6},
-		{"66",           CPU_i486DX2, fpus_internal,  66666666, 2,  5000, 0x470,    0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6,  8},
+		{"50",           CPU_i486DX_SLENH, fpus_internal,  50000000, 2,  5000, 0x470,    0x470, 0, CPU_SUPPORTS_DYNAREC,  8, 8,6,6,  6},
+		{"66",           CPU_i486DX_SLENH, fpus_internal,  66666666, 2,  5000, 0x470,    0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6,  8},
 		{"", 0}
 	}
     }, {
-	.package = CPU_PKG_SOCKET3 | CPU_PKG_SOCKET3_PC330,
+	.package = CPU_PKG_SOCKET1 | CPU_PKG_SOCKET3_PC330, /*OEM versions are 3.3V, Retail versions are 3.3V with a 5V regulator for installation in older boards. hey are functionally identical*/
 	.manufacturer = "Intel",
 	.name = "iDX4",
 	.internal_name = "idx4",
 	.cpus = (const CPU[]) {
-		{"75",              CPU_iDX4,    fpus_internal,  75000000, 3.0, 5000,  0x480,  0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9,  9}, /*CPUID available on DX4, >= 75 MHz*/
-		{"100",             CPU_iDX4,    fpus_internal, 100000000, 3.0, 5000,  0x483,  0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
-		{"", 0}
-	}
-    }, {
-	.package = CPU_PKG_SOCKET1,
-	.manufacturer = "Intel",
-	.name = "iDX4 OverDrive",
-	.internal_name = "idx4_od",
-	.cpus = (const CPU[]) {
-		{"75",    CPU_iDX4,    fpus_internal,  75000000, 3,  5000, 0x1480,  0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9,  9}, /*Only added the DX4 OverDrive as the others would be redundant*/
-		{"100",   CPU_iDX4,    fpus_internal, 100000000, 3,  5000, 0x1480,  0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, 
+		{"75",              CPU_i486DX_SLENH,    fpus_internal,  75000000, 3.0, 5000,  0x480,  0x480, 0x0000, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9,  9}, 
+		{"100",             CPU_i486DX_SLENH,    fpus_internal, 100000000, 3.0, 5000,  0x483,  0x483, 0x0000, CPU_SUPPORTS_DYNAREC, 18,18, 9, 9, 12},
 		{"", 0}
 	}
     }, {
@@ -394,8 +419,8 @@ const cpu_family_t cpu_families[] = {
 	.name = "Am486SX",
 	.internal_name = "am486sx",
 	.cpus = (const CPU[]) {
-		{"33",   CPU_Am486SX,     fpus_486sx, 33333333, 1, 5000, 0x42a,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
-		{"40",   CPU_Am486SX,     fpus_486sx, 40000000, 1, 5000, 0x42a,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5}, 
+		{"33",   CPU_Am486SX,     fpus_486sx, 33333333, 1, 5000, 0x422,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
+		{"40",   CPU_Am486SX,     fpus_486sx, 40000000, 1, 5000, 0x422,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5}, 
 		{"", 0}
 	}
     }, {
@@ -404,8 +429,8 @@ const cpu_family_t cpu_families[] = {
 	.name = "Am486SX2",
 	.internal_name = "am486sx2",
 	.cpus = (const CPU[]) {
-		{"50",  CPU_Am486SX2,    fpus_486sx, 50000000, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
-		{"66",  CPU_Am486SX2,    fpus_486sx, 66666666, 2, 5000, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
+		{"50",  CPU_Am486SX,    fpus_486sx, 50000000, 2, 5000, 0x45b,     0, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6}, 
+		{"66",  CPU_Am486SX,    fpus_486sx, 66666666, 2, 5000, 0x45b,     0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, 
 		{"", 0}
 	}
     }, {
@@ -414,8 +439,8 @@ const cpu_family_t cpu_families[] = {
 	.name = "Am486DX",
 	.internal_name = "am486dx",
 	.cpus = (const CPU[]) {
-		{"33",   CPU_Am486DX,  fpus_internal, 33333333, 1, 5000, 0x430,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
-		{"40",   CPU_Am486DX,  fpus_internal, 40000000, 1, 5000, 0x430,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5},
+		{"33",   CPU_Am486DX,  fpus_internal, 33333333, 1, 5000, 0x412,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
+		{"40",   CPU_Am486DX,  fpus_internal, 40000000, 1, 5000, 0x412,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5},
 		{"", 0}
 	}
     }, {
@@ -424,9 +449,9 @@ const cpu_family_t cpu_families[] = {
 	.name = "Am486DX2",
 	.internal_name = "am486dx2",
 	.cpus = (const CPU[]) {
-		{"50",  CPU_Am486DX2, fpus_internal, 50000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6},
-		{"66",  CPU_Am486DX2, fpus_internal, 66666666, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
-		{"80",  CPU_Am486DX2, fpus_internal, 80000000, 2, 5000, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
+		{"50",  CPU_Am486DX, fpus_internal, 50000000, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6},
+		{"66",  CPU_Am486DX, fpus_internal, 66666666, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
+		{"80",  CPU_Am486DX, fpus_internal, 80000000, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
 		{"", 0}
 	}
     }, {
@@ -435,10 +460,32 @@ const cpu_family_t cpu_families[] = {
 	.name = "Am486DX4",
 	.internal_name = "am486dx4",
 	.cpus = (const CPU[]) {
-		{"75",  CPU_Am486DX4, fpus_internal,   75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
-		{"90",  CPU_Am486DX4, fpus_internal,   90000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
-		{"100", CPU_Am486DX4, fpus_internal,  100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
-		{"120", CPU_Am486DX4, fpus_internal,  120000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
+		{"75",  CPU_Am486DX, fpus_internal,   75000000, 3.0, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
+		{"90",  CPU_Am486DX, fpus_internal,   90000000, 3.0, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
+		{"100", CPU_Am486DX, fpus_internal,  100000000, 3.0, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
+		{"120", CPU_Am486DX, fpus_internal,  120000000, 3.0, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
+		{"", 0}
+	}
+    }, 
+     {
+	.package = CPU_PKG_SOCKET3,
+	.manufacturer = "AMD",
+	.name = "Am486DX2 (Enhanced)",
+	.internal_name = "enh_am486dx2",
+	.cpus = (const CPU[]) {
+		{"66",  CPU_ENH_Am486DX, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
+		{"80",  CPU_ENH_Am486DX, fpus_internal, 80000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
+		{"", 0}
+	}
+    }, {
+	.package = CPU_PKG_SOCKET3,
+	.manufacturer = "AMD",
+	.name = "Am486DX4 (Enhanced)",
+	.internal_name = "enh_am486dx4",
+	.cpus = (const CPU[]) {
+		{"75",  CPU_ENH_Am486DX, fpus_internal,   75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
+		{"100", CPU_ENH_Am486DX, fpus_internal,  100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
+		{"120", CPU_ENH_Am486DX, fpus_internal,  120000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
 		{"", 0}
 	}
     }, {
@@ -447,9 +494,9 @@ const cpu_family_t cpu_families[] = {
 	.name = "Am5x86",
 	.internal_name = "am5x86",
 	.cpus = (const CPU[]) {
-		{"P75",   CPU_Am5x86,   fpus_internal,  133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
-		{"P75+",  CPU_Am5x86,   fpus_internal,  150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
-		{"P90",   CPU_Am5x86,   fpus_internal,  160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ 
+		{"P75",   CPU_ENH_Am486DX,   fpus_internal,  133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
+		{"P75+",  CPU_ENH_Am486DX,   fpus_internal,  150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
+		{"P90",   CPU_ENH_Am486DX,   fpus_internal,  160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ 
 		{"", 0}
 	}
     }, {
@@ -479,9 +526,9 @@ const cpu_family_t cpu_families[] = {
 	.name = "Cx486DX2",
 	.internal_name = "cx486dx2",
 	.cpus = (const CPU[]) {
-		{"50",        CPU_Cx486DX2, fpus_internal,   50000000, 2.0, 5000,  0x430,      0, 0x081b, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6,  6},
-		{"66",        CPU_Cx486DX2, fpus_internal,   66666666, 2.0, 5000,  0x430,      0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6,  8},
-		{"80",        CPU_Cx486DX2, fpus_internal,   80000000, 2.0, 5000,  0x430,      0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
+		{"50",        CPU_Cx486DX, fpus_internal,   50000000, 2.0, 5000,  0x430,      0, 0x081b, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6,  6},
+		{"66",        CPU_Cx486DX, fpus_internal,   66666666, 2.0, 5000,  0x430,      0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6,  8},
+		{"80",        CPU_Cx486DX, fpus_internal,   80000000, 2.0, 5000,  0x430,      0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
 		{"", 0}
 	}
     }, {
@@ -490,8 +537,8 @@ const cpu_family_t cpu_families[] = {
 	.name = "Cx486DX4",
 	.internal_name = "cx486dx4",
 	.cpus = (const CPU[]) {
-		{"75",  CPU_Cx486DX4, fpus_internal,  75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9,  9},
-		{"100", CPU_Cx486DX4, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
+		{"75",  CPU_Cx486DX, fpus_internal,  75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9,  9},
+		{"100", CPU_Cx486DX, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
 		{"", 0}
 	}
     }, {
@@ -522,7 +569,7 @@ const cpu_family_t cpu_families[] = {
 	.name = "STPC-DX2",
 	.internal_name = "stpc_dx2",
 	.cpus = (const CPU[]) {
-		{"133",    CPU_Cx486DX2, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
+		{"133",    CPU_Cx486DX, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
 		{"", 0}
 	}
     }, {
diff --git a/src/cpu/x86.c b/src/cpu/x86.c
index f8e13764e..70ef37701 100644
--- a/src/cpu/x86.c
+++ b/src/cpu/x86.c
@@ -281,7 +281,7 @@ reset_common(int hard)
     smi_block = 0;
 
     if (hard) {
-	smbase = is_486_org ? 0x00060000 : 0x00030000;
+	smbase = 0x00030000;
 	ppi_reset();
     }
     in_sys = 0;
diff --git a/src/device/keyboard_at.c b/src/device/keyboard_at.c
index 600c61bb4..f6b9f7be0 100644
--- a/src/device/keyboard_at.c
+++ b/src/device/keyboard_at.c
@@ -1061,7 +1061,7 @@ write_output(atkbd_t *dev, uint8_t val)
 		/* Pin 0 selected. */
 		softresetx86(); /*Pulse reset!*/
 		cpu_set_edx();
-		smbase = is_486_org ? 0x00060000 : 0x00030000;
+		smbase = 0x00030000;
 	}
     }
     /* Mask off the A20 stuff because we use mem_a20_key directly for that. */
diff --git a/src/machine/machine.c b/src/machine/machine.c
index 045e81c30..e3869c970 100644
--- a/src/machine/machine.c
+++ b/src/machine/machine.c
@@ -81,7 +81,7 @@ machine_init_ex(int m)
 
 	/* Reset the memory state. */
 	mem_reset();
-	smbase = is_486_org ? 0x00060000 : 0x00030000;
+	smbase = 0x00030000;
 
 	lpt_init();
     }
diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c
index 4ed5f966b..13f76feb2 100644
--- a/src/machine/machine_table.c
+++ b/src/machine/machine_table.c
@@ -240,7 +240,7 @@ const machine_t machines[] = {
     { "[SiS 496] Lucky Star LS-486E",		"ls486e",		MACHINE_TYPE_486,		CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0,										MACHINE_PCI | MACHINE_IDE_DUAL,							 1024, 131072, 1024, 255,	       machine_at_ls486e_init, NULL			},
     { "[SiS 496] Micronics M4Li",		"m4li",			MACHINE_TYPE_486,		CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0,										MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL,				 1024, 131072, 1024, 127,		 machine_at_m4li_init, NULL			},
     { "[SiS 496] Rise Computer R418",		"r418",			MACHINE_TYPE_486,		CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0,										MACHINE_PCI | MACHINE_IDE_DUAL,							 1024, 261120, 1024, 255,		 machine_at_r418_init, NULL			},
-    { "[SiS 496] Soyo 4SA2",			"4sa2",			MACHINE_TYPE_486,		CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0,										MACHINE_PCI | MACHINE_IDE_DUAL,							 1024, 261120, 1024, 255,		 machine_at_4sa2_init, NULL			},
+    { "[SiS 496] Soyo 4SA2",			"4sa2",			MACHINE_TYPE_486,		CPU_PKG_SOCKET3, CPU_BLOCK(CPU_i486SX, CPU_i486DX, CPU_Am486SX, CPU_Am486DX), 0, 0, 0, 0, 0, 0,			MACHINE_PCI | MACHINE_IDE_DUAL,							 1024, 261120, 1024, 255,		 machine_at_4sa2_init, NULL			},
     { "[SiS 496] Zida Tomato 4DP",		"4dps",			MACHINE_TYPE_486,		CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0,										MACHINE_PCI | MACHINE_IDE_DUAL,							 1024, 261120, 1024, 255,		 machine_at_4dps_init, NULL			},
     { "[UMC 8881] A-Trend ATC-1415",		"atc1415",		MACHINE_TYPE_486,		CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0,										MACHINE_PCI | MACHINE_IDE_DUAL,							 1024,  65536, 1024, 255,	      machine_at_atc1415_init, NULL			},
     { "[UMC 8881] ECS Elite UM8810PAIO",	"ecs486",		MACHINE_TYPE_486,		CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0,										MACHINE_PCI | MACHINE_IDE_DUAL,							 1024, 131072, 1024, 255,	       machine_at_ecs486_init, NULL			},

From 27ddd856dff7c5ae629a8bb7f65adb4c6fdbe550 Mon Sep 17 00:00:00 2001
From: nerd73 <nerd7b@gmail.com>
Date: Thu, 15 Apr 2021 21:42:02 -0600
Subject: [PATCH 20/23] Remove some unnecessary parentheses

---
 src/cpu/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c
index ae71bae33..e06aea378 100644
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -375,7 +375,7 @@ cpu_set(void)
 
     /* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums,
        and the WinChip datasheet claims those are Pentium-compatible as well. */
-    is_pentium   = (cpu_isintel && (((cpu_s->cpu_type >= CPU_i486SX_SLENH)) && (cpu_s->cpu_type < CPU_PENTIUMPRO))) ||
+    is_pentium   = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX_SLENH) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) ||
 		   !strcmp(cpu_f->manufacturer, "IDT");
     is_k5        = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_ENH_Am486DX);
     is_k6        = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD");

From 791bae3560567e74ec8b240eb2900d205f83e747 Mon Sep 17 00:00:00 2001
From: nerd73 <nerd7b@gmail.com>
Date: Thu, 15 Apr 2021 23:28:07 -0600
Subject: [PATCH 21/23] Add the AMD Am486DXL and DXL2.

Has otherwise Intel-compatible SMM with an SMBase at 60000h.
---
 src/cpu/cpu.c            |  7 ++++---
 src/cpu/cpu.h            |  1 +
 src/cpu/cpu_table.c      | 22 ++++++++++++++++++++++
 src/cpu/x86.c            |  2 +-
 src/device/keyboard_at.c |  2 +-
 src/machine/machine.c    |  2 +-
 6 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c
index e06aea378..5415aab31 100644
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -110,7 +110,7 @@ int		isa_cycles,
 
  		is286, is386, is486 = 1,
 		cpu_isintel, cpu_iscyrix, hascache, isibm486, israpidcad, is_vpc,
-		is_am486, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
+		is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
 
 		timing_rr, timing_mr, timing_mrl, timing_rm, timing_rml,
 		timing_mm, timing_mml, timing_bt, timing_bnt,
@@ -369,14 +369,15 @@ cpu_set(void)
 		   (cpu_s->cpu_type == CPU_IBM486BL);
     is486        = (cpu_s->cpu_type >= CPU_RAPIDCAD);
     is_am486     = (cpu_s->cpu_type == CPU_ENH_Am486DX);
+    is_am486dxl  = (cpu_s->cpu_type == CPU_Am486DXL);
 
     cpu_isintel = !strcmp(cpu_f->manufacturer, "Intel");
     cpu_iscyrix = !strcmp(cpu_f->manufacturer, "Cyrix");
 
     /* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums,
-       and the WinChip datasheet claims those are Pentium-compatible as well. */
+       and the WinChip datasheet claims those are Pentium-compatible as well. AMD Am486DXL/DXL2 also has compatible SMM, or would if not for it's different SMBase*/
     is_pentium   = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX_SLENH) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) ||
-		   !strcmp(cpu_f->manufacturer, "IDT");
+		   !strcmp(cpu_f->manufacturer, "IDT") || (cpu_s->cpu_type == CPU_Am486DXL);
     is_k5        = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_ENH_Am486DX);
     is_k6        = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD");
     /* The Samuel 2 datasheet claims it's Celeron-compatible. */
diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h
index f35ae54d7..569b31875 100644
--- a/src/cpu/cpu.h
+++ b/src/cpu/cpu.h
@@ -52,6 +52,7 @@ enum {
     CPU_Cx486S,
     CPU_i486DX,
     CPU_Am486DX,
+    CPU_Am486DXL,
     CPU_Cx486DX,
     CPU_i486SX_SLENH,
     CPU_i486DX_SLENH,
diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c
index f5da157b7..cfba9080c 100644
--- a/src/cpu/cpu_table.c
+++ b/src/cpu/cpu_table.c
@@ -454,7 +454,29 @@ const cpu_family_t cpu_families[] = {
 		{"80",  CPU_Am486DX, fpus_internal, 80000000, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
 		{"", 0}
 	}
+    }, 
+ {
+	.package = CPU_PKG_SOCKET1,
+	.manufacturer = "AMD",
+	.name = "Am486DXL",
+	.internal_name = "am486dxl",
+	.cpus = (const CPU[]) {
+		{"33",   CPU_Am486DXL,  fpus_internal, 33333333, 1, 5000, 0x422,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
+		{"40",   CPU_Am486DXL,  fpus_internal, 40000000, 1, 5000, 0x422,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5},
+		{"", 0}
+	}
     }, {
+	.package = CPU_PKG_SOCKET1,
+	.manufacturer = "AMD",
+	.name = "Am486DXL2",
+	.internal_name = "am486dxl2",
+	.cpus = (const CPU[]) {
+		{"50",  CPU_Am486DXL, fpus_internal, 50000000, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6},
+		{"66",  CPU_Am486DXL, fpus_internal, 66666666, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
+		{"80",  CPU_Am486DXL, fpus_internal, 80000000, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
+		{"", 0}
+	}
+    },     {
 	.package = CPU_PKG_SOCKET3,
 	.manufacturer = "AMD",
 	.name = "Am486DX4",
diff --git a/src/cpu/x86.c b/src/cpu/x86.c
index 70ef37701..bb8d86cf9 100644
--- a/src/cpu/x86.c
+++ b/src/cpu/x86.c
@@ -281,7 +281,7 @@ reset_common(int hard)
     smi_block = 0;
 
     if (hard) {
-	smbase = 0x00030000;
+	smbase = isam486dxl ? 0x00060000 : 0x00030000;
 	ppi_reset();
     }
     in_sys = 0;
diff --git a/src/device/keyboard_at.c b/src/device/keyboard_at.c
index f6b9f7be0..33fff0d23 100644
--- a/src/device/keyboard_at.c
+++ b/src/device/keyboard_at.c
@@ -1061,7 +1061,7 @@ write_output(atkbd_t *dev, uint8_t val)
 		/* Pin 0 selected. */
 		softresetx86(); /*Pulse reset!*/
 		cpu_set_edx();
-		smbase = 0x00030000;
+		smbase = isam486dxl ? 0x00060000 : 0x00030000;
 	}
     }
     /* Mask off the A20 stuff because we use mem_a20_key directly for that. */
diff --git a/src/machine/machine.c b/src/machine/machine.c
index e3869c970..76cd8d27b 100644
--- a/src/machine/machine.c
+++ b/src/machine/machine.c
@@ -81,7 +81,7 @@ machine_init_ex(int m)
 
 	/* Reset the memory state. */
 	mem_reset();
-	smbase = 0x00030000;
+	smbase = isam486dxl ? 0x00060000 : 0x00030000;
 
 	lpt_init();
     }

From 17c5cc862e61b748cb4766454ec43e2d41361a49 Mon Sep 17 00:00:00 2001
From: nerd73 <nerd7b@gmail.com>
Date: Thu, 15 Apr 2021 23:30:52 -0600
Subject: [PATCH 22/23] fix cpu.h

---
 src/cpu/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h
index 569b31875..177712fa7 100644
--- a/src/cpu/cpu.h
+++ b/src/cpu/cpu.h
@@ -478,7 +478,7 @@ extern int	cpu_cyrix_alignment;	/*Cyrix 5x86/6x86 only has data misalignment
 					  penalties when crossing 8-byte boundaries*/
 
 extern int	is8086,	is286, is386, is486;
-extern int	is_am486, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
+extern int	is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
 extern int	hascache;
 extern int	isibm486;
 extern int	is_rapidcad;

From 5e89a9d77576208d6d06b8dd9eea793d0f712093 Mon Sep 17 00:00:00 2001
From: nerd73 <nerd7b@gmail.com>
Date: Thu, 15 Apr 2021 23:34:53 -0600
Subject: [PATCH 23/23] fix more compile issues

---
 src/cpu/x86.c            | 2 +-
 src/device/keyboard_at.c | 2 +-
 src/machine/machine.c    | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/cpu/x86.c b/src/cpu/x86.c
index bb8d86cf9..9ab8ce169 100644
--- a/src/cpu/x86.c
+++ b/src/cpu/x86.c
@@ -281,7 +281,7 @@ reset_common(int hard)
     smi_block = 0;
 
     if (hard) {
-	smbase = isam486dxl ? 0x00060000 : 0x00030000;
+	smbase = is_am486dxl ? 0x00060000 : 0x00030000;
 	ppi_reset();
     }
     in_sys = 0;
diff --git a/src/device/keyboard_at.c b/src/device/keyboard_at.c
index 33fff0d23..7c844ec15 100644
--- a/src/device/keyboard_at.c
+++ b/src/device/keyboard_at.c
@@ -1061,7 +1061,7 @@ write_output(atkbd_t *dev, uint8_t val)
 		/* Pin 0 selected. */
 		softresetx86(); /*Pulse reset!*/
 		cpu_set_edx();
-		smbase = isam486dxl ? 0x00060000 : 0x00030000;
+		smbase = is_am486dxl ? 0x00060000 : 0x00030000;
 	}
     }
     /* Mask off the A20 stuff because we use mem_a20_key directly for that. */
diff --git a/src/machine/machine.c b/src/machine/machine.c
index 76cd8d27b..685165f89 100644
--- a/src/machine/machine.c
+++ b/src/machine/machine.c
@@ -81,7 +81,7 @@ machine_init_ex(int m)
 
 	/* Reset the memory state. */
 	mem_reset();
-	smbase = isam486dxl ? 0x00060000 : 0x00030000;
+	smbase = is_am486dxl ? 0x00060000 : 0x00030000;
 
 	lpt_init();
     }