Even more tabs to spaces
This commit is contained in:
Jasmine Iwanek
@@ -1,18 +1,18 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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* This file is part of the 86Box distribution.
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*
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* Implementation of the ACC 3221-SP Super I/O Chip.
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* Implementation of the ACC 3221-SP Super I/O Chip.
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*
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*
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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*
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* Copyright 2019 Sarah Walker.
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* Copyright 2019 Sarah Walker.
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*/
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#include <stdio.h>
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#include <stdint.h>
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@@ -40,31 +40,31 @@ typedef struct acc3221_t {
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} acc3221_t;
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/* Configuration Register Index, BE (R/W):
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Bit Function
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7 PIRQ 5 polarity.
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Bit Function
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7 PIRQ 5 polarity.
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1 = active high, default
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0 = active low
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6 PIRQ 7 polarity.
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6 PIRQ 7 polarity.
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1 = active high, default
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0 = active low
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5 Primary Parallel Port Extended Mode
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5 Primary Parallel Port Extended Mode
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0 = Compatible mode, default
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1 = Extended/Bidirectional mode.
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4 Primary Parallel Port Disable
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4 Primary Parallel Port Disable
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1 = Disable, 0 = Enable
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Power Up Default is set by pin 120
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(3221-DP)/pin 96 (3221-SP)
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3 Primary Parallel Port Power Down
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3 Primary Parallel Port Power Down
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1 = Power Down, default = 0
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2** Secondary Parallel Port Extended
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2** Secondary Parallel Port Extended
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Mode
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0 = Compatible mode, default
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1 = Extended/Bidirectional mode.
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1** Secondary Parallel Port Disable
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1** Secondary Parallel Port Disable
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1 = Disable, 0 = Enable
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Power Up Default is set by pin 77
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(3221-DP)
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0** Secondary Parallel Port Power Down
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0** Secondary Parallel Port Power Down
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1 = Power Down
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0 = Enable, default
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Note: Power Up not applicable to 3221-EP. */
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@@ -72,41 +72,41 @@ typedef struct acc3221_t {
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#define REG_BE_LPT2_DISABLE (3 << 0) /* 3221-DP/EP only */
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/* Configuration Register Index, BF (R/W):
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Bit Function
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7-0 The 8 most significant address bits of
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Bit Function
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7-0 The 8 most significant address bits of
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the primary parallel port (A9-2)
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Default 9E (LPT2, at 278-27B) */
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/* Configuration Register Index, DA (R/W)**:
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Bit Function
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7-0 The 8 most significant address bits of
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Bit Function
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7-0 The 8 most significant address bits of
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the secondary parallel port (A9-2)
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Default DE (LPT1, at 378-37B) */
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/* Configuration Register Index, DB (R/W):
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Bit Function
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7 SIRQ4 polarity.
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Bit Function
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7 SIRQ4 polarity.
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1 = active high; default
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0 = active low
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6 SIRQ3 polarity.
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6 SIRQ3 polarity.
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1 = active high; default
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0 = active low
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5 SXTAL clock off. 1 = SCLK off,
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5 SXTAL clock off. 1 = SCLK off,
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0 = SCKL on, default
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4 Primary serial port disable
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4 Primary serial port disable
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1 = Disable, 0 = Enable
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Power Up default is set by pin 116
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(3221-DP)/pin 93 (3221-SP)
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3 Primary serial port power down
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3 Primary serial port power down
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1 = Power down, 0 = Enable
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Power Up default is set by pin 116
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(3221-DP)/pin 93 (3221-SP)
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2 Reserved
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1 Secondary serial port disable
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2 Reserved
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1 Secondary serial port disable
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1 = Disable, 0 = Enable
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Power Up default is set by pin 121
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(3221-DP)/pin 97 (3221-SP)
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0 Secondary serial port power down
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0 Secondary serial port power down
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1 = Power down, 0 = Enable
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Power Up default is set by pin 121
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(3221-DP)/pin 97 (3221-SP)
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@@ -115,57 +115,57 @@ typedef struct acc3221_t {
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#define REG_DB_SERIAL2_DISABLE (3 << 0)
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/* Configuration Register Index, DC (R/W):
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Bit Function
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7-1 The MSB of the Primary Serial Port
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Bit Function
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7-1 The MSB of the Primary Serial Port
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Address (bits A9-3).
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Default = 7F (COM1, at 3F8-3FF).
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0 When this bit is set to 1, bit A2 of
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0 When this bit is set to 1, bit A2 of
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primary parallel port is decoded.
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Default is 0. */
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/* Configuration Register Index, DD (R/W):
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Bit Function
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7-1 The MSB of the Secondary Serial Port
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Bit Function
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7-1 The MSB of the Secondary Serial Port
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Address (bits A9-3).
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Default = 5F (COM2, at 2F8-2FF).
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0** When this bit is set to 1, bit A2 of
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0** When this bit is set to 1, bit A2 of
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secondary parallel port is decoded.
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Default is 0. */
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/* Configuration Register Index, DE (R/W):
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Bit Function
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7-6 SIRQ3 source
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b7 b6
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0 0 Disabled, tri-stated
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0 1 Disabled, tri-stated**
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1 0 Primary serial port
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1 1 Secondary serial port,
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Bit Function
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7-6 SIRQ3 source
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b7 b6
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0 0 Disabled, tri-stated
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0 1 Disabled, tri-stated**
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1 0 Primary serial port
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1 1 Secondary serial port,
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default
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5-4 SIRQ4 source
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b5 b4
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0 0 Disabled, tri-stated
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0 1 Disabled, tri-stated**
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1 0 Primary serial port,
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5-4 SIRQ4 source
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b5 b4
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0 0 Disabled, tri-stated
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0 1 Disabled, tri-stated**
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1 0 Primary serial port,
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default
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1 1 Secondary serial port
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1 1 Secondary serial port
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3-2** PIRQ7 source
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b3 b2
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0 0 Diabled, tri-stated,
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3-2** PIRQ7 source
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b3 b2
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0 0 Diabled, tri-stated,
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default
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0 1 Primary serial port
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1 0 Primary parallel port
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1 1 Secondary parallel
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0 1 Primary serial port
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1 0 Primary parallel port
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1 1 Secondary parallel
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port
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Note: Bits 3-2 are reserved in 3221-SP.
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1-0 PIRQ5 source
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b1 b0
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0 0 Disabled, tri-stated
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0 1 Secondary serial port
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1 0 Primary parallel port,
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1-0 PIRQ5 source
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b1 b0
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0 0 Disabled, tri-stated
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0 1 Secondary serial port
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1 0 Primary parallel port,
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default
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1 1 Secondary parallel
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1 1 Secondary parallel
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port** */
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#define REG_DE_SIRQ3_SOURCE (3 << 6)
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#define REG_DE_SIRQ3_SERIAL1 (1 << 6)
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@@ -183,48 +183,48 @@ typedef struct acc3221_t {
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#define REG_DE_PIRQ5_LPT2 (3 << 0)
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/* Configuration Register Index, DF (R/W)**:
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Bit Function
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7-6 Reserved
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5 RTC interface disable
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Bit Function
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7-6 Reserved
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5 RTC interface disable
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1 = /RTCCS disabled
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0 = /RTCCS enabled, default
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4 Disable Modem Select
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4 Disable Modem Select
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1 = Moden CS disabled, default
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0 = Modem CS enabled
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3-2
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b3 b2
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1 1 Reserved
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1 0 Modem port address
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b3 b2
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1 1 Reserved
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1 0 Modem port address
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= 3E8-3EF (default)
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0 1 Modem port address:
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0 1 Modem port address:
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2F8-2FF
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0 0 Modem port address:
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0 0 Modem port address:
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3F8-3FF
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1-0
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b1 b0
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1 1 Reserved
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1 0 Mode 2, EISA Mode
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0 1 Mode 1, AT BUS,
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0 0 Mode 0, Two parallel
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b1 b0
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1 1 Reserved
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1 0 Mode 2, EISA Mode
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0 1 Mode 1, AT BUS,
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0 0 Mode 0, Two parallel
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ports, default */
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/* Configuration Register Index, FA (R/W)**:
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Bit Function
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7 General purpose I/O register, Bit 7
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6 General purpose I/O register, Bit 6
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5 General purpose I/O register, Bit 5
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4 General purpose I/O register, Bit 4
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3 General purpose I/O register, Bit 3
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2 General purpose I/O register, Bit 2
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1 General purpose I/O register, Bit 1
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0 General purpose I/O register, Bit 0 */
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Bit Function
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7 General purpose I/O register, Bit 7
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6 General purpose I/O register, Bit 6
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5 General purpose I/O register, Bit 5
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4 General purpose I/O register, Bit 4
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3 General purpose I/O register, Bit 3
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2 General purpose I/O register, Bit 2
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1 General purpose I/O register, Bit 1
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0 General purpose I/O register, Bit 0 */
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/* Configuration Register Index, FB (R/W)**:
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Bit Function
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7 Reserved
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6** 0/2 EXG (Read Only)
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Bit Function
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7 Reserved
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6** 0/2 EXG (Read Only)
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In mode 1 and mode 2
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operation, when the third
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floppy drive is installed, pin
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@@ -234,7 +234,7 @@ typedef struct acc3221_t {
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disable the third floppy drive.
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1 = Third floppy drive enabled
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0 = Third floppy drive disabled
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5** EXTFDD (Read Only)
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5** EXTFDD (Read Only)
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In mode 1 and mode 2
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operation, when the third
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floppy drive is installed and
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@@ -246,7 +246,7 @@ typedef struct acc3221_t {
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drive 2.
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1 = Third floppy drive as drive 0 (bootable)
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0 = Third floppy drive as drive 2
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4** MS
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4** MS
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In mode 1 and mode 2, t his bit is to
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control the output pin MS to support a
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special 3 1/2", 1.2M drive. When this
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@@ -254,45 +254,45 @@ typedef struct acc3221_t {
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a low signal. When this bit is set to
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low (0), the MS pin sends a high
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signal to support a 3 1/2", 1.2M drive.
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3 FDC, Clock disable
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3 FDC, Clock disable
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0 = enable, default
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1 = disable
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2 Reserved
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1 FDC disable
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2 Reserved
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1 FDC disable
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0 = enable, 1= disable
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Power Upd efault set by pin 117 (3221-
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DP)/pin 94 (3221-SP)
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0 FDC address
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0 FDC address
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0 = Primary, default
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1 = Secondary
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Note: Bits 6-4 are reserved in 3221-SP. */
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#define REG_FB_FDC_DISABLE (1 << 1)
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/* Configuration Register Index, FB (R/W)**:
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Bit Function
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7** Disable general chip select 1
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Bit Function
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7** Disable general chip select 1
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1 = disable, default
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0 = enable
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6** Disable general chip select 2
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6** Disable general chip select 2
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1 = disable, default
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0 = enable
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5** Enable SA2 decoding for general chip
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5** Enable SA2 decoding for general chip
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select 1
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1 = enable
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0 = disable, default
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4** Enable SA2 decoding for general chip
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4** Enable SA2 decoding for general chip
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select 2
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1 = enable
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0 = disable, default
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3 Reserved
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2 IDE XT selected
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3 Reserved
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2 IDE XT selected
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0 = IDE AT interface, default
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1 = IDE XT interface
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1 IDE disable, 1 = IDE disable
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1 IDE disable, 1 = IDE disable
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0 = IDE enable
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Power Up default set by pin 13 (3221-
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DP)/pin 13 (3221-SP)
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0 Secondary IDE
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0 Secondary IDE
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1 = secondary
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0 = primary, default
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Note: Bits 6-4 are reserved in 3221-SP. */
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