Applied all relevant PCem commits;
Extensively cleaned up and changed the CD-ROM code; Removed CD-ROM IOCTTL (it was causing performance and stability issues); Turned a lot of things into device_t's; Added the PS/1 Model 2011 XTA and standalone XTA hard disk controllers, ported from Varcem; Numerous FDC fixes for the PS/1 Model 2121; NVR changes ported from Varcem; The PCap code no longer requires libpcap to be compiled; Numerous fixes to various SCSI controllers; Updated NukedOPL to 1.8; Fixes to OpenAL initialization and closing, should give less Audio issues now; Revorked parts of the common (S)VGA code (also based on code from QEMU); Removed the Removable SCSI hard disks (they were a never finished experiment so there was no need to keep them there); Cleaned up the SCSI hard disk and Iomega ZIP code (but more cleanups of that are coming in the future); In some occasions (IDE hard disks in multiple sector mode and SCSI hard disks) the status bar icon is no longer updated, should improve performance a bit; Redid the way the tertiary and quaternary IDE controllers are configured (and they are now device_t's); Extensively reworked the IDE code and fixed quite a few bugs; Fixes to XT MFM, AT MFM, and AT ESDI code; Some changes to XTIDE and MCA ESDI code; Some fixes to the CD-ROM image handler.
This commit is contained in:
OBattler
@@ -8,7 +8,7 @@
|
||||
*
|
||||
* Implementation of the Intel 440FX PCISet chip.
|
||||
*
|
||||
* Version: @(#)m_at_440fx.c 1.0.11 2018/03/18
|
||||
* Version: @(#)m_at_440fx.c 1.0.12 2018/04/04
|
||||
*
|
||||
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
|
||||
* Miran Grca, <mgrca8@gmail.com>
|
||||
@@ -18,6 +18,7 @@
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <wchar.h>
|
||||
#include "../86box.h"
|
||||
@@ -33,207 +34,239 @@
|
||||
#include "machine.h"
|
||||
|
||||
|
||||
static uint8_t card_i440fx[256];
|
||||
|
||||
|
||||
static void i440fx_map(uint32_t addr, uint32_t size, int state)
|
||||
typedef struct
|
||||
{
|
||||
switch (state & 3)
|
||||
{
|
||||
case 0:
|
||||
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
|
||||
break;
|
||||
case 1:
|
||||
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
|
||||
break;
|
||||
case 2:
|
||||
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
|
||||
break;
|
||||
case 3:
|
||||
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
|
||||
break;
|
||||
}
|
||||
flushmmucache_nopc();
|
||||
}
|
||||
uint8_t regs[256];
|
||||
} i440fx_t;
|
||||
|
||||
|
||||
static void i440fx_write(int func, int addr, uint8_t val, void *priv)
|
||||
static void
|
||||
i440fx_map(uint32_t addr, uint32_t size, int state)
|
||||
{
|
||||
if (func)
|
||||
return;
|
||||
|
||||
if ((addr >= 0x10) && (addr < 0x4f))
|
||||
return;
|
||||
|
||||
switch (addr)
|
||||
{
|
||||
case 0x00: case 0x01: case 0x02: case 0x03:
|
||||
case 0x08: case 0x09: case 0x0a: case 0x0b:
|
||||
case 0x0c: case 0x0e:
|
||||
return;
|
||||
|
||||
case 0x04: /*Command register*/
|
||||
val &= 0x02;
|
||||
val |= 0x04;
|
||||
break;
|
||||
case 0x05:
|
||||
val = 0;
|
||||
break;
|
||||
|
||||
case 0x06: /*Status*/
|
||||
val = 0;
|
||||
break;
|
||||
case 0x07:
|
||||
val &= 0x80;
|
||||
val |= 0x02;
|
||||
break;
|
||||
|
||||
case 0x59: /*PAM0*/
|
||||
if ((card_i440fx[0x59] ^ val) & 0xf0)
|
||||
{
|
||||
i440fx_map(0xf0000, 0x10000, val >> 4);
|
||||
shadowbios = (val & 0x10);
|
||||
}
|
||||
break;
|
||||
case 0x5a: /*PAM1*/
|
||||
if ((card_i440fx[0x5a] ^ val) & 0x0f)
|
||||
i440fx_map(0xc0000, 0x04000, val & 0xf);
|
||||
if ((card_i440fx[0x5a] ^ val) & 0xf0)
|
||||
i440fx_map(0xc4000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5b: /*PAM2*/
|
||||
if ((card_i440fx[0x5b] ^ val) & 0x0f)
|
||||
i440fx_map(0xc8000, 0x04000, val & 0xf);
|
||||
if ((card_i440fx[0x5b] ^ val) & 0xf0)
|
||||
i440fx_map(0xcc000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5c: /*PAM3*/
|
||||
if ((card_i440fx[0x5c] ^ val) & 0x0f)
|
||||
i440fx_map(0xd0000, 0x04000, val & 0xf);
|
||||
if ((card_i440fx[0x5c] ^ val) & 0xf0)
|
||||
i440fx_map(0xd4000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5d: /*PAM4*/
|
||||
if ((card_i440fx[0x5d] ^ val) & 0x0f)
|
||||
i440fx_map(0xd8000, 0x04000, val & 0xf);
|
||||
if ((card_i440fx[0x5d] ^ val) & 0xf0)
|
||||
i440fx_map(0xdc000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5e: /*PAM5*/
|
||||
if ((card_i440fx[0x5e] ^ val) & 0x0f)
|
||||
i440fx_map(0xe0000, 0x04000, val & 0xf);
|
||||
if ((card_i440fx[0x5e] ^ val) & 0xf0)
|
||||
i440fx_map(0xe4000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5f: /*PAM6*/
|
||||
if ((card_i440fx[0x5f] ^ val) & 0x0f)
|
||||
i440fx_map(0xe8000, 0x04000, val & 0xf);
|
||||
if ((card_i440fx[0x5f] ^ val) & 0xf0)
|
||||
i440fx_map(0xec000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x72: /*SMRAM*/
|
||||
if ((card_i440fx[0x72] ^ val) & 0x48)
|
||||
i440fx_map(0xa0000, 0x20000, ((val & 0x48) == 0x48) ? 3 : 0);
|
||||
switch (state & 3) {
|
||||
case 0:
|
||||
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
|
||||
break;
|
||||
}
|
||||
|
||||
card_i440fx[addr] = val;
|
||||
case 1:
|
||||
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
|
||||
break;
|
||||
case 2:
|
||||
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
|
||||
break;
|
||||
case 3:
|
||||
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
|
||||
break;
|
||||
}
|
||||
flushmmucache_nopc();
|
||||
}
|
||||
|
||||
|
||||
static uint8_t i440fx_read(int func, int addr, void *priv)
|
||||
static void
|
||||
i440fx_write(int func, int addr, uint8_t val, void *priv)
|
||||
{
|
||||
if (func)
|
||||
return 0xff;
|
||||
i440fx_t *dev = (i440fx_t *) priv;
|
||||
|
||||
return card_i440fx[addr];
|
||||
if (func)
|
||||
return;
|
||||
|
||||
if ((addr >= 0x10) && (addr < 0x4f))
|
||||
return;
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: case 0x01: case 0x02: case 0x03:
|
||||
case 0x08: case 0x09: case 0x0a: case 0x0b:
|
||||
case 0x0c: case 0x0e:
|
||||
return;
|
||||
|
||||
case 0x04: /*Command register*/
|
||||
val &= 0x02;
|
||||
val |= 0x04;
|
||||
break;
|
||||
case 0x05:
|
||||
val = 0;
|
||||
break;
|
||||
|
||||
case 0x06: /*Status*/
|
||||
val = 0;
|
||||
break;
|
||||
case 0x07:
|
||||
val &= 0x80;
|
||||
val |= 0x02;
|
||||
break;
|
||||
|
||||
case 0x59: /*PAM0*/
|
||||
if ((dev->regs[0x59] ^ val) & 0xf0) {
|
||||
i440fx_map(0xf0000, 0x10000, val >> 4);
|
||||
shadowbios = (val & 0x10);
|
||||
}
|
||||
break;
|
||||
case 0x5a: /*PAM1*/
|
||||
if ((dev->regs[0x5a] ^ val) & 0x0f)
|
||||
i440fx_map(0xc0000, 0x04000, val & 0xf);
|
||||
if ((dev->regs[0x5a] ^ val) & 0xf0)
|
||||
i440fx_map(0xc4000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5b: /*PAM2*/
|
||||
if ((dev->regs[0x5b] ^ val) & 0x0f)
|
||||
i440fx_map(0xc8000, 0x04000, val & 0xf);
|
||||
if ((dev->regs[0x5b] ^ val) & 0xf0)
|
||||
i440fx_map(0xcc000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5c: /*PAM3*/
|
||||
if ((dev->regs[0x5c] ^ val) & 0x0f)
|
||||
i440fx_map(0xd0000, 0x04000, val & 0xf);
|
||||
if ((dev->regs[0x5c] ^ val) & 0xf0)
|
||||
i440fx_map(0xd4000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5d: /*PAM4*/
|
||||
if ((dev->regs[0x5d] ^ val) & 0x0f)
|
||||
i440fx_map(0xd8000, 0x04000, val & 0xf);
|
||||
if ((dev->regs[0x5d] ^ val) & 0xf0)
|
||||
i440fx_map(0xdc000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5e: /*PAM5*/
|
||||
if ((dev->regs[0x5e] ^ val) & 0x0f)
|
||||
i440fx_map(0xe0000, 0x04000, val & 0xf);
|
||||
if ((dev->regs[0x5e] ^ val) & 0xf0)
|
||||
i440fx_map(0xe4000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x5f: /*PAM6*/
|
||||
if ((dev->regs[0x5f] ^ val) & 0x0f)
|
||||
i440fx_map(0xe8000, 0x04000, val & 0xf);
|
||||
if ((dev->regs[0x5f] ^ val) & 0xf0)
|
||||
i440fx_map(0xec000, 0x04000, val >> 4);
|
||||
break;
|
||||
case 0x72: /*SMRAM*/
|
||||
if ((dev->regs[0x72] ^ val) & 0x48)
|
||||
i440fx_map(0xa0000, 0x20000, ((val & 0x48) == 0x48) ? 3 : 0);
|
||||
break;
|
||||
}
|
||||
|
||||
dev->regs[addr] = val;
|
||||
}
|
||||
|
||||
|
||||
static uint8_t
|
||||
i440fx_read(int func, int addr, void *priv)
|
||||
{
|
||||
i440fx_t *dev = (i440fx_t *) priv;
|
||||
|
||||
if (func)
|
||||
return 0xff;
|
||||
|
||||
return dev->regs[addr];
|
||||
}
|
||||
|
||||
|
||||
static void i440fx_reset(void)
|
||||
static void
|
||||
i440fx_reset(void *priv)
|
||||
{
|
||||
memset(card_i440fx, 0, 256);
|
||||
card_i440fx[0x00] = 0x86; card_i440fx[0x01] = 0x80; /*Intel*/
|
||||
card_i440fx[0x02] = 0x37; card_i440fx[0x03] = 0x12; /*82441FX*/
|
||||
card_i440fx[0x04] = 0x03; card_i440fx[0x05] = 0x01;
|
||||
card_i440fx[0x06] = 0x80; card_i440fx[0x07] = 0x00;
|
||||
card_i440fx[0x08] = 0x02; /*A0 stepping*/
|
||||
card_i440fx[0x09] = 0x00; card_i440fx[0x0a] = 0x00; card_i440fx[0x0b] = 0x06;
|
||||
card_i440fx[0x0d] = 0x00;
|
||||
card_i440fx[0x0f] = 0x00;
|
||||
card_i440fx[0x2c] = 0xf4;
|
||||
card_i440fx[0x2d] = 0x1a;
|
||||
card_i440fx[0x2e] = 0x00;
|
||||
card_i440fx[0x2f] = 0x11;
|
||||
card_i440fx[0x50] = 0x00;
|
||||
card_i440fx[0x51] = 0x01;
|
||||
card_i440fx[0x52] = card_i440fx[0x54] = card_i440fx[0x55] = card_i440fx[0x56] = 0x00;
|
||||
card_i440fx[0x53] = 0x80;
|
||||
card_i440fx[0x57] = 0x01;
|
||||
card_i440fx[0x58] = 0x10;
|
||||
card_i440fx[0x5a] = card_i440fx[0x5b] = card_i440fx[0x5c] = card_i440fx[0x5d] = card_i440fx[0x5e] = 0x11;
|
||||
card_i440fx[0x5f] = 0x31;
|
||||
card_i440fx[0x72] = 0x02;
|
||||
}
|
||||
|
||||
|
||||
static void i440fx_pci_reset(void)
|
||||
{
|
||||
i440fx_write(0, 0x59, 0x00, NULL);
|
||||
i440fx_write(0, 0x72, 0x02, NULL);
|
||||
i440fx_write(0, 0x59, 0x00, priv);
|
||||
i440fx_write(0, 0x72, 0x02, priv);
|
||||
}
|
||||
|
||||
|
||||
static void i440fx_init(void)
|
||||
static void
|
||||
i440fx_close(void *p)
|
||||
{
|
||||
pci_add_card(0, i440fx_read, i440fx_write, NULL);
|
||||
|
||||
i440fx_reset();
|
||||
i440fx_t *i440fx = (i440fx_t *)p;
|
||||
|
||||
pci_reset_handler.pci_master_reset = i440fx_pci_reset;
|
||||
free(i440fx);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
*i440fx_init(const device_t *info)
|
||||
{
|
||||
i440fx_t *i440fx = (i440fx_t *) malloc(sizeof(i440fx_t));
|
||||
memset(i440fx, 0, sizeof(i440fx_t));
|
||||
|
||||
i440fx->regs[0x00] = 0x86; i440fx->regs[0x01] = 0x80; /*Intel*/
|
||||
i440fx->regs[0x02] = 0x37; i440fx->regs[0x03] = 0x12; /*82441FX*/
|
||||
i440fx->regs[0x04] = 0x03; i440fx->regs[0x05] = 0x01;
|
||||
i440fx->regs[0x06] = 0x80; i440fx->regs[0x07] = 0x00;
|
||||
i440fx->regs[0x08] = 0x02; /*A0 stepping*/
|
||||
i440fx->regs[0x09] = 0x00; i440fx->regs[0x0a] = 0x00; i440fx->regs[0x0b] = 0x06;
|
||||
i440fx->regs[0x0d] = 0x00;
|
||||
i440fx->regs[0x0f] = 0x00;
|
||||
i440fx->regs[0x2c] = 0xf4;
|
||||
i440fx->regs[0x2d] = 0x1a;
|
||||
i440fx->regs[0x2e] = 0x00;
|
||||
i440fx->regs[0x2f] = 0x11;
|
||||
i440fx->regs[0x50] = 0x00;
|
||||
i440fx->regs[0x51] = 0x01;
|
||||
i440fx->regs[0x52] = i440fx->regs[0x54] = i440fx->regs[0x55] = i440fx->regs[0x56] = 0x00;
|
||||
i440fx->regs[0x53] = 0x80;
|
||||
i440fx->regs[0x57] = 0x01;
|
||||
i440fx->regs[0x58] = 0x10;
|
||||
i440fx->regs[0x5a] = i440fx->regs[0x5b] = i440fx->regs[0x5c] = i440fx->regs[0x5d] = 0x11;
|
||||
i440fx->regs[0x5e] = 0x11;
|
||||
i440fx->regs[0x5f] = 0x31;
|
||||
i440fx->regs[0x72] = 0x02;
|
||||
|
||||
pci_add_card(0, i440fx_read, i440fx_write, i440fx);
|
||||
|
||||
return i440fx;
|
||||
}
|
||||
|
||||
|
||||
const device_t i440fx_device =
|
||||
{
|
||||
"Intel 82441FX",
|
||||
DEVICE_PCI,
|
||||
0,
|
||||
i440fx_init,
|
||||
i440fx_close,
|
||||
i440fx_reset,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
void
|
||||
machine_at_i440fx_init(const machine_t *model)
|
||||
{
|
||||
machine_at_ps2_init(model);
|
||||
machine_at_common_init(model);
|
||||
device_add(&keyboard_ps2_pci_device);
|
||||
|
||||
memregs_init();
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
|
||||
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
||||
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
||||
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
||||
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
|
||||
i440fx_init();
|
||||
piix3_init(7);
|
||||
fdc37c665_init();
|
||||
memregs_init();
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
|
||||
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
||||
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
||||
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
||||
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
|
||||
device_add(&i440fx_device);
|
||||
device_add(&piix3_device);
|
||||
fdc37c665_init();
|
||||
|
||||
device_add(&intel_flash_bxt_device);
|
||||
device_add(&intel_flash_bxt_device);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
machine_at_s1668_init(const machine_t *model)
|
||||
{
|
||||
machine_at_common_init(model);
|
||||
device_add(&keyboard_ps2_ami_device);
|
||||
machine_at_common_init(model);
|
||||
device_add(&keyboard_ps2_ami_pci_device);
|
||||
|
||||
memregs_init();
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
|
||||
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
|
||||
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
||||
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
||||
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
||||
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
i440fx_init();
|
||||
piix3_init(7);
|
||||
fdc37c665_init();
|
||||
memregs_init();
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_register_slot(0x00, PCI_CARD_SPECIAL, 0, 0, 0, 0);
|
||||
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
|
||||
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
||||
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
||||
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
||||
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
device_add(&i440fx_device);
|
||||
device_add(&piix3_device);
|
||||
fdc37c665_init();
|
||||
|
||||
device_add(&intel_flash_bxt_device);
|
||||
device_add(&intel_flash_bxt_device);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user