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Current WIP ALi work.

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This commit is contained in:
OBattler
2021-07-04 18:16:35 +02:00
parent 4f6df76f10
commit a896953dd5
18 changed files with 2190 additions and 88 deletions
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4
src/chipset/CMakeLists.txt
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@@ -13,8 +13,8 @@
# Copyright 2020,2021 David Hrdlička.
#
add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c ali1531.c ali1543.c
headland.c intel_82335.c cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c
add_library(chipset OBJECT acc2168.c cs8230.c ali1217.c ali1429.c ali1489.c ali1531.c ali1541.c
ali1543.c headland.c intel_82335.c cs4031.c intel_420ex.c intel_4x0.c intel_sio.c intel_piix.c
../ioapic.c neat.c opti283.c opti291.c opti391.c opti495.c opti822.c opti895.c opti5x7.c
scamp.c scat.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c sis_5511.c sis_5571.c
via_vt82c49x.c via_vt82c505.c sis_85c310.c sis_85c4xx.c sis_85c496.c sis_85c50x.c

19
src/chipset/ali1531.c
View File

@@ -253,27 +253,10 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x60: /* DRB's */
case 0x62:
case 0x64:
case 0x66:
case 0x68:
case 0x6a:
case 0x6c:
case 0x6e:
case 0x60 ... 0x6f: /* DRB's */
dev->pci_conf[addr] = val;
spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1);
break;
case 0x61:
case 0x63:
case 0x65:
case 0x67:
case 0x69:
case 0x6b:
case 0x6d:
case 0x6f:
dev->pci_conf[addr] = val;
break;
case 0x70: case 0x71:
dev->pci_conf[addr] = val;

656
src/chipset/ali1541.c Normal file
View File

@@ -0,0 +1,656 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1541/2 CPU-to-PCI Bridge.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/chipset.h>
typedef struct ali1541_t
{
uint8_t pci_conf[256];
smram_t * smram;
void * agp_bridge;
} ali1541_t;
#ifdef ENABLE_ALI1541_LOG
int ali1541_do_log = ENABLE_ALI1541_LOG;
static void
ali1541_log(const char *fmt, ...)
{
va_list ap;
if (ali1541_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define ali1541_log(fmt, ...)
#endif
static void
ali1541_smram_recalc(uint8_t val, ali1541_t *dev)
{
smram_disable_all();
if (val & 1) {
switch (val & 0x0c) {
case 0x00:
ali1541_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02);
break;
case 0x04:
ali1541_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02);
break;
case 0x08:
ali1541_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
break;
}
}
flushmmucache_nopc();
}
static void
ali1541_shadow_recalc(int cur_reg, ali1541_t *dev)
{
int i, bit, r_reg, w_reg;
uint32_t base, flags = 0;
shadowbios = shadowbios_write = 0;
for (i = 0; i < 16; i++) {
base = 0x000c0000 + (i << 14);
bit = i & 7;
r_reg = 0x56 + (i >> 3);
w_reg = 0x58 + (i >> 3);
flags = (dev->pci_conf[r_reg] & (1 << bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
flags |= ((dev->pci_conf[w_reg] & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY);
if (base >= 0x000e0000) {
if (dev->pci_conf[r_reg] & (1 << bit))
shadowbios |= 1;
if (dev->pci_conf[w_reg] & (1 << bit))
shadowbios_write |= 1;
}
ali1541_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff,
(dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E');
mem_set_mem_state_both(base, 0x00004000, flags);
}
flushmmucache_nopc();
}
static void
ali1541_mask_bar(ali1541_t *dev)
{
uint32_t bar, mask;
switch (dev->pci_conf[0xbc] & 0x0f) {
case 0x00:
default:
mask = 0x00000000;
break;
case 0x01:
mask = 0xfff00000;
break;
case 0x02:
mask = 0xffe00000;
break;
case 0x03:
mask = 0xffc00000;
break;
case 0x04:
mask = 0xff800000;
break;
case 0x06:
mask = 0xff000000;
break;
case 0x07:
mask = 0xfe000000;
break;
case 0x08:
mask = 0xfc000000;
break;
case 0x09:
mask = 0xf8000000;
break;
case 0x0a:
mask = 0xf0000000;
break;
}
bar = ((dev->pci_conf[0x13] << 24) | (dev->pci_conf[0x12] << 16)) & mask;
dev->pci_conf[0x12] = (bar >> 16) & 0xff;
dev->pci_conf[0x13] = (bar >> 24) & 0xff;
}
static void
ali1541_write(int func, int addr, uint8_t val, void *priv)
{
ali1541_t *dev = (ali1541_t *)priv;
switch (addr) {
case 0x04:
dev->pci_conf[addr] = val;
break;
case 0x05:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0xf8);
break;
case 0x0d:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x12:
dev->pci_conf[0x12] = (val & 0xc0);
ali1541_mask_bar(dev);
break;
case 0x13:
dev->pci_conf[0x13] = val;
ali1541_mask_bar(dev);
break;
case 0x2c: /* Subsystem Vendor ID */
case 0x2d:
case 0x2e:
case 0x2f:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val;
break;
case 0x34:
if (dev->pci_conf[0x90] & 0x02)
dev->pci_conf[addr] = val;
break;
case 0x40:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x41:
dev->pci_conf[addr] = val & 0x7f;
break;
case 0x42: /* L2 Cache */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = !!(val & 1);
cpu_update_waitstates();
break;
case 0x43: /* PLCTL-Pipe Line Control */
dev->pci_conf[addr] = val & 0xf7;
break;
case 0x44:
dev->pci_conf[addr] = val;
break;
case 0x45:
dev->pci_conf[addr] = val;
break;
case 0x46:
dev->pci_conf[addr] = val & 0xf0;
break;
case 0x47:
dev->pci_conf[addr] = val;
break;
case 0x48:
dev->pci_conf[addr] = val;
break;
case 0x49:
dev->pci_conf[addr] = val;
break;
case 0x4a:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x4b:
dev->pci_conf[addr] = val;
break;
case 0x4c:
dev->pci_conf[addr] = val;
break;
case 0x4d:
dev->pci_conf[addr] = val;
break;
case 0x4e:
dev->pci_conf[addr] = val;
break;
case 0x4f:
dev->pci_conf[addr] = val;
break;
case 0x50:
dev->pci_conf[addr] = val & 0x71;
break;
case 0x51:
dev->pci_conf[addr] = val;
break;
case 0x52:
dev->pci_conf[addr] = val;
break;
case 0x53:
dev->pci_conf[addr] = val;
break;
case 0x54:
dev->pci_conf[addr] = val & 0x3c;
if (mem_size > 0xe00000)
mem_set_mem_state_both(0xe00000, 0x100000, (val & 0x20) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
if (mem_size > 0xf00000)
mem_set_mem_state_both(0xf00000, 0x100000, (val & 0x10) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
flushmmucache_nopc();
break;
case 0x55: /* SMRAM */
dev->pci_conf[addr] = val & 0x1f;
ali1541_smram_recalc(val, dev);
break;
case 0x56 ... 0x59: /* Shadow RAM */
dev->pci_conf[addr] = val;
ali1541_shadow_recalc(val, dev);
break;
case 0x5a: case 0x5b:
dev->pci_conf[addr] = val;
break;
case 0x5c:
dev->pci_conf[addr] = val;
break;
case 0x5d:
dev->pci_conf[addr] = val & 0x17;
break;
case 0x5e:
dev->pci_conf[addr] = val;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0xc1;
break;
case 0x60 ... 0x6f: /* DRB's */
dev->pci_conf[addr] = val;
spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1);
break;
case 0x70:
dev->pci_conf[addr] = val;
break;
case 0x71:
dev->pci_conf[addr] = val;
break;
case 0x72:
dev->pci_conf[addr] = val & 0xc7;
break;
case 0x73:
dev->pci_conf[addr] = val & 0x1f;
break;
case 0x84: case 0x85:
dev->pci_conf[addr] = val;
break;
case 0x86:
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x87: /* H2PO */
dev->pci_conf[addr] = val;
/* Find where the Shut-down Special cycle is initiated. */
// if (!(val & 0x20))
// outb(0x92, 0x01);
break;
case 0x88:
dev->pci_conf[addr] = val;
break;
case 0x89:
dev->pci_conf[addr] = val;
break;
case 0x8a:
dev->pci_conf[addr] = val;
break;
case 0x8b:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x8c:
dev->pci_conf[addr] = val;
break;
case 0x8d:
dev->pci_conf[addr] = val;
break;
case 0x8e:
dev->pci_conf[addr] = val;
break;
case 0x8f:
dev->pci_conf[addr] = val;
break;
case 0x90:
dev->pci_conf[addr] = val;
pci_bridge_set_ctl(dev->agp_bridge, val);
break;
case 0x91:
dev->pci_conf[addr] = val;
break;
case 0xb4:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val & 0x03;
break;
case 0xb5:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val & 0x02;
break;
case 0xb7:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val;
break;
case 0xb8:
dev->pci_conf[addr] = val & 0x03;
break;
case 0xb9:
dev->pci_conf[addr] = val & 0x03;
break;
case 0xbb:
dev->pci_conf[addr] = val;
break;
case 0xbc:
dev->pci_conf[addr] = val & 0x0f;
ali1541_mask_bar(dev);
break;
case 0xbd:
dev->pci_conf[addr] = val & 0xf0;
break;
case 0xbe: case 0xbf:
dev->pci_conf[addr] = val;
break;
case 0xc0:
dev->pci_conf[addr] = val & 0x90;
break;
case 0xc1: case 0xc2:
case 0xc3:
dev->pci_conf[addr] = val;
break;
case 0xc8: case 0xc9:
dev->pci_conf[addr] = val;
break;
case 0xd1:
dev->pci_conf[addr] = val & 0xf1;
break;
case 0xd2: case 0xd3:
dev->pci_conf[addr] = val;
break;
case 0xe0: case 0xe1:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val;
break;
case 0xe2:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0x3f;
break;
case 0xe3:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0xfe;
break;
case 0xe4:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0x03;
break;
case 0xe5:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val;
break;
case 0xe6:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0xc0;
break;
case 0xe7:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val;
break;
case 0xe8: case 0xe9:
if (dev->pci_conf[0x90] & 0x04)
dev->pci_conf[addr] = val;
break;
case 0xea:
dev->pci_conf[addr] = val & 0xcf;
break;
case 0xeb:
dev->pci_conf[addr] = val & 0xcf;
break;
case 0xec:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0xed:
dev->pci_conf[addr] = val;
break;
case 0xee:
dev->pci_conf[addr] = val & 0x3e;
break;
case 0xef:
dev->pci_conf[addr] = val;
break;
case 0xf3:
dev->pci_conf[addr] = val & 0x08;
break;
case 0xf5:
dev->pci_conf[addr] = val;
break;
case 0xf6:
dev->pci_conf[addr] = val;
break;
case 0xf7:
dev->pci_conf[addr] = val & 0x43;
break;
}
}
static uint8_t
ali1541_read(int func, int addr, void *priv)
{
ali1541_t *dev = (ali1541_t *)priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
return ret;
}
static void
ali1541_reset(void *priv)
{
ali1541_t *dev = (ali1541_t *)priv;
int i;
/* Default Registers */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x41;
dev->pci_conf[0x03] = 0x15;
dev->pci_conf[0x04] = 0x06;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x10;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x08] = 0x00;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x0c] = 0x00;
dev->pci_conf[0x0d] = 0x20;
dev->pci_conf[0x0e] = 0x00;
dev->pci_conf[0x0f] = 0x00;
dev->pci_conf[0x2c] = 0xb9;
dev->pci_conf[0x2d] = 0x10;
dev->pci_conf[0x2e] = 0x41;
dev->pci_conf[0x2f] = 0x15;
dev->pci_conf[0x34] = 0xb0;
dev->pci_conf[0x89] = 0x20;
dev->pci_conf[0x8a] = 0x20;
dev->pci_conf[0x91] = 0x13;
dev->pci_conf[0xb0] = 0x02;
dev->pci_conf[0xb1] = 0xe0;
dev->pci_conf[0xb2] = 0x10;
dev->pci_conf[0xb4] = 0x03;
dev->pci_conf[0xb5] = 0x02;
dev->pci_conf[0xb7] = 0x1c;
dev->pci_conf[0xc8] = 0xbf;
dev->pci_conf[0xc9] = 0x0a;
dev->pci_conf[0xe0] = 0x01;
cpu_cache_int_enabled = 1;
ali1541_write(0, 0x42, 0x00, dev);
ali1541_write(0, 0x54, 0x00, dev);
ali1541_write(0, 0x55, 0x00, dev);
for (i = 0; i < 4; i++)
ali1541_write(0, 0x56 + i, 0x00, dev);
ali1541_write(0, 0x60 + i, 0x07, dev);
ali1541_write(0, 0x61 + i, 0x40, dev);
for (i = 0; i < 14; i += 2) {
ali1541_write(0, 0x62 + i, 0x00, dev);
ali1541_write(0, 0x63 + i, 0x00, dev);
}
}
static void
ali1541_close(void *priv)
{
ali1541_t *dev = (ali1541_t *)priv;
smram_del(dev->smram);
free(dev);
}
static void *
ali1541_init(const device_t *info)
{
ali1541_t *dev = (ali1541_t *)malloc(sizeof(ali1541_t));
memset(dev, 0, sizeof(ali1541_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1541_read, ali1541_write, dev);
dev->smram = smram_add();
ali1541_reset(dev);
dev->agp_bridge = device_add(&ali5243_agp_device);
return dev;
}
const device_t ali1541_device = {
"ALi M1541 CPU-to-PCI Bridge",
DEVICE_PCI,
0,
ali1541_init,
ali1541_close,
ali1541_reset,
{NULL},
NULL,
NULL,
NULL
};

257
src/chipset/ali1543.c
View File

@@ -34,15 +34,13 @@
#include <86box/fdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/smbus_piix4.h>
#include <86box/smbus.h>
#include <86box/usb.h>
#include <86box/acpi.h>
@@ -55,7 +53,7 @@ typedef struct ali1543_t
uint8_t pci_conf[256], pmu_conf[256], usb_conf[256], ide_conf[256],
sio_regs[256], device_regs[8][256], sio_index, in_configuration_mode,
pci_slot, ide_slot, usb_slot, pmu_slot, usb_dev_enable, ide_dev_enable,
pmu_dev_enable;
pmu_dev_enable, type;
apm_t * apm;
acpi_t * acpi;
@@ -65,7 +63,7 @@ typedef struct ali1543_t
port_92_t * port_92;
serial_t * uart[2];
sff8038i_t * ide_controller[2];
smbus_piix4_t * smbus;
smbus_ali7101_t * smbus;
usb_t * usb;
} ali1543_t;
@@ -120,8 +118,6 @@ static void
ali1533_write(int func, int addr, uint8_t val, void *priv)
{
ali1543_t *dev = (ali1543_t *)priv;
int irq;
ali1543_log("M1533: dev->pci_conf[%02x] = %02x\n", addr, val);
if (func > 0)
@@ -129,8 +125,15 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
switch (addr) {
case 0x04: /* Command Register */
if (!(dev->pci_conf[0x5f] & 0x08))
dev->pci_conf[0x04] = val;
if (dev->type == 1) {
if (dev->pci_conf[0x5f] & 0x08)
dev->pci_conf[0x04] = val & 0x0f;
else
dev->pci_conf[0x04] = val;
} else {
if (!(dev->pci_conf[0x5f] & 0x08))
dev->pci_conf[0x04] = val;
}
break;
case 0x05: /* Command Register */
if (!(dev->pci_conf[0x5f] & 0x08))
@@ -222,11 +225,13 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x4d: /* MBIRQ0(SIRQI#), MBIRQ1(SIRQII#) Interrupt to ISA IRQ routing table */
dev->pci_conf[addr] = val;
if (dev->type == 0) {
dev->pci_conf[addr] = val;
ali1543_log("SIRQI = IRQ %i; SIRQII = IRQ %i\n", ali1533_irq_routing[(val >> 4) & 0x0f], ali1533_irq_routing[val & 0x0f]);
// pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]);
// pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
ali1543_log("SIRQI = IRQ %i; SIRQII = IRQ %i\n", ali1533_irq_routing[(val >> 4) & 0x0f], ali1533_irq_routing[val & 0x0f]);
// pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]);
// pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
}
break;
/* I/O cycle posted-write first port definition */
@@ -242,7 +247,10 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val;
break;
case 0x53:
dev->pci_conf[addr] = val & 0xcf;
if (dev->type == 1)
dev->pci_conf[addr] = val;
else
dev->pci_conf[addr] = val & 0xcf;
/* This actually enables/disables the USB *device* rather than the interface itself. */
dev->usb_dev_enable = !(val & 0x40);
break;
@@ -254,7 +262,10 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val;
break;
case 0x57:
dev->pci_conf[addr] = val & 0xc7;
if (dev->type == 1)
dev->pci_conf[addr] = val & 0xf0;
else
dev->pci_conf[addr] = val & 0xe0;
break;
/* IDE interface control
@@ -277,7 +288,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->ide_slot = 0x0d; /* A24 = slot 13 */
break;
}
ali1543_log("IDE slot = %02X (A%0i)\n", dev->ide_slot, dev->ide_slot + 11 - 5);
ali1543_log("IDE slot = %02X (A%0i)\n", dev->ide_slot - 5, dev->ide_slot + 11);
pclog("IDE slot = %02X (A%0i)\n", dev->ide_slot - 5, dev->ide_slot + 11);
ali5229_ide_irq_handler(dev);
break;
@@ -303,7 +315,10 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x5e:
dev->pci_conf[addr] = val & 0xe0;
if (dev->type == 1)
dev->pci_conf[addr] = val & 0xe1;
else
dev->pci_conf[addr] = val & 0xe0;
break;
case 0x5f:
@@ -343,7 +358,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->pmu_slot = 0x04; /* A15 = slot 04 */
break;
}
ali1543_log("PMU slot = %02X (A%0i)\n", dev->pmu_slot, dev->pmu_slot + 11 - 5);
ali1543_log("PMU slot = %02X (A%0i)\n", dev->pmu_slot - 5, dev->pmu_slot + 11);
pclog("PMU slot = %02X (A%0i)\n", dev->pmu_slot - 5, dev->pmu_slot + 11);
switch (val & 0x03) {
case 0x00:
dev->usb_slot = 0x14; /* A31 = slot 20 */
@@ -358,7 +374,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->usb_slot = 0x01; /* A12 = slot 01 */
break;
}
ali1543_log("USB slot = %02X (A%0i)\n", dev->usb_slot, dev->usb_slot + 11 - 5);
ali1543_log("USB slot = %02X (A%0i)\n", dev->usb_slot - 5, dev->usb_slot + 11);
pclog("USB slot = %02X (A%0i)\n", dev->usb_slot - 5, dev->usb_slot + 11);
break;
case 0x73: /* DDMA Base Address */
@@ -382,9 +399,15 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x76: /* PMU IRQ Routing - we cheat and use MIRQ5 */
dev->pci_conf[addr] = val & 0x1f;
if (dev->type == 1)
dev->pci_conf[addr] = val & 0x9f;
else
dev->pci_conf[addr] = val & 0x1f;
acpi_set_mirq_is_level(dev->acpi, !!(val & 0x10));
pci_set_mirq_routing(PCI_MIRQ5, ali1533_irq_routing[val & 0x0f]);
if ((dev->type == 1) && (val & 0x80))
pci_set_mirq_routing(PCI_MIRQ5, PCI_IRQ_DISABLED);
else
pci_set_mirq_routing(PCI_MIRQ5, ali1533_irq_routing[val & 0x0f]);
/* TODO: Tell ACPI to use MIRQ5 */
break;
@@ -392,10 +415,24 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0x1f;
pci_set_mirq_routing(PCI_MIRQ6, ali1533_irq_routing[val & 0x0f]);
break;
case 0x78:
if (dev->type == 1) {
pclog("PCI78 = %02X\n", val);
dev->pci_conf[addr] = val & 0x33;
}
break;
case 0x7c ... 0xff:
if ((dev->type == 1) && !dev->pmu_dev_enable) {
dev->pmu_dev_enable = 1;
ali7101_write(func, addr, val, priv);
dev->pmu_dev_enable = 0;
}
break;
}
}
static uint8_t
ali1533_read(int func, int addr, void *priv)
{
@@ -411,6 +448,11 @@ ali1533_read(int func, int addr, void *priv)
ret |= (keyboard_at_get_mouse_scan() << 2);
else if (addr == 0x58)
ret = (ret & 0xbf) | (dev->ide_dev_enable ? 0x40 : 0x00);
else if ((dev->type == 1) && ((addr >= 0x7c) && (addr <= 0xff)) && !dev->pmu_dev_enable) {
dev->pmu_dev_enable = 1;
ret = ali7101_read(func, addr, priv);
dev->pmu_dev_enable = 0;
}
}
}
@@ -506,6 +548,7 @@ ali5229_ide_irq_handler(ali1543_t *dev)
static void
ali5229_ide_handler(ali1543_t *dev)
ali5229_ide_handler(ali1543_t *dev)
{
uint32_t ch = 0;
@@ -617,7 +660,14 @@ ali5229_chip_reset(ali1543_t *dev)
dev->ide_conf[0x67] = 0x01;
dev->ide_conf[0x78] = 0x21;
ali5229_write(0, 0x04, 0x01, dev);
if (dev->type == 1) {
dev->ide_conf[0x08] = 0xc1;
dev->ide_conf[0x4b] = 0x4a;
dev->ide_conf[0x4e] = 0xba;
dev->ide_conf[0x4f] = 0x1a;
}
ali5229_write(0, 0x04, 0x00 /*0x01*/, dev);
ali5229_write(0, 0x10, 0xf1, dev);
ali5229_write(0, 0x11, 0x01, dev);
ali5229_write(0, 0x14, 0xf5, dev);
@@ -672,10 +722,12 @@ ali5229_write(int func, int addr, uint8_t val, void *priv)
case 0x09: /* Control */
ali1543_log("IDE09: %02X\n", val);
#ifdef M1543_C
val &= ~(dev->ide_conf[0x43]);
val |= (dev->ide_conf[addr] & dev->ide_conf[0x43]);
#endif
if (dev->type == 1) {
val &= ~(dev->ide_conf[0x43]);
val |= (dev->ide_conf[addr] & dev->ide_conf[0x43]);
}
if (dev->ide_conf[0x4d] & 0x80)
dev->ide_conf[addr] = (dev->ide_conf[addr] & 0xfa) | (val & 0x05);
else
@@ -710,18 +762,23 @@ ali5229_write(int func, int addr, uint8_t val, void *priv)
break;
/* The machines don't touch anything beyond that point so we avoid any programming */
#ifdef M1543_C
case 0x43:
dev->ide_conf[addr] = val & 0x7f;
if (dev->type == 1)
dev->ide_conf[addr] = val & 0x7f;
break;
case 0x4b:
if (dev->type == 1)
dev->ide_conf[addr] = val;
break;
#endif
case 0x4d:
dev->ide_conf[addr] = val & 0x80;
break;
case 0x4f:
dev->ide_conf[addr] = val & 0x3f;
if (dev->type == 0)
dev->ide_conf[addr] = val & 0x3f;
break;
case 0x50: /* Configuration */
@@ -830,8 +887,13 @@ ali5237_write(int func, int addr, uint8_t val, void *priv)
case 0x0c: /* Cache Line Size */
case 0x0d: /* Latency Timer */
case 0x3c: /* Interrupt Line Register */
case 0x40 ... 0x43: /* Test Mode Register */
dev->usb_conf[addr] = val;
case 0x42: /* Test Mode Register */
dev->usb_conf[addr] = val & 0x10;
break;
case 0x43:
if (dev->type == 1)
dev->usb_conf[addr] = val & 0x04;
break;
/* USB Base I/O */
@@ -888,7 +950,10 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
ali1543_log("PMU04: %02X\n", val);
dev->pmu_conf[addr] = val & 0x01;
acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1);
smbus_piix4_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
if (dev->type == 1)
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
else
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
break;
/* PMU Base I/O */
@@ -899,6 +964,7 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
else if (addr == 0x11)
dev->pmu_conf[addr] = val;
pclog("New ACPI base address: %08X\n", (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0));
acpi_update_io_mapping(dev->acpi, (dev->pmu_conf[0x11] << 8) | (dev->pmu_conf[0x10] & 0xc0), dev->pmu_conf[0x04] & 1);
}
break;
@@ -906,12 +972,21 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
/* SMBus Base I/O */
case 0x14: case 0x15:
if (!(dev->pmu_conf[0x5b] & 0x04)) {
if (addr == 0x14)
dev->pmu_conf[addr] = (val & 0xe0) | 1;
else if (addr == 0x15)
if (addr == 0x14) {
if (dev->type == 1)
dev->pmu_conf[addr] = (val & 0xc0) | 1;
else
dev->pmu_conf[addr] = (val & 0xe0) | 1;
} else if (addr == 0x15)
dev->pmu_conf[addr] = val;
smbus_piix4_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
if (dev->type == 1) {
pclog("New SMBUS base address: %08X\n", (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0));
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
} else {
pclog("New SMBUS base address: %08X\n", (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0));
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1));
}
}
break;
@@ -977,6 +1052,16 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
dev->pmu_conf[addr] &= ~(val & 1);
break;
case 0x50: case 0x51:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0x52: case 0x53:
if (dev->type == 1)
dev->pmu_conf[addr] &= ~val;
break;
case 0x54: /* Standby timer */
dev->pmu_conf[addr] = val;
break;
@@ -988,7 +1073,10 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x5b: /* ACPI/SMB Base I/O Control */
dev->pmu_conf[addr] = val & 0x7f;
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x87;
else
dev->pmu_conf[addr] = val & 0x7f;
break;
case 0x60:
@@ -1022,7 +1110,10 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
dev->pmu_conf[addr] = val & 0xbf;
break;
case 0x6f:
dev->pmu_conf[addr] = val & 0x1f;
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x1e;
else
dev->pmu_conf[addr] = val & 0x1f;
break;
case 0x70:
@@ -1065,11 +1156,17 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x7a:
dev->pmu_conf[addr] = val & 0x02;
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x07;
else
dev->pmu_conf[addr] = val & 0x02;
break;
case 0x7b:
dev->pmu_conf[addr] = val & 0x7f;
if (dev->type == 1)
dev->pmu_conf[addr] = val;
else
dev->pmu_conf[addr] = val & 0x7f;
break;
case 0x7c ... 0x7f:
@@ -1080,12 +1177,34 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
dev->pmu_conf[addr] = val & 0xf0;
break;
case 0x82:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x01;
break;
case 0x84 ... 0x87:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0x88 ... 0x8b:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0x8c: case 0x8d:
dev->pmu_conf[addr] = val & 0x0f;
break;
case 0x90:
dev->pmu_conf[addr] = val & 0x01;
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x0f;
else
dev->pmu_conf[addr] = val & 0x01;
break;
case 0x91:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x02;
break;
case 0x94:
@@ -1095,6 +1214,11 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
dev->pmu_conf[addr] = val;
break;
case 0x98: case 0x99:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0xa4: case 0xa5:
dev->pmu_conf[addr] = val;
break;
@@ -1115,6 +1239,11 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
dev->pmu_conf[addr] = val & 0x0f;
break;
case 0xb8: case 0xb9:
if (dev->type == 1)
dev->pmu_conf[addr] = val;
break;
case 0xbc:
outb(0x70, val);
break;
@@ -1160,6 +1289,15 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
dev->pmu_conf[addr] = val;
break;
case 0xcc:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x1f;
break;
case 0xcd:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x33;
break;
case 0xd4:
dev->pmu_conf[addr] = val & 0x01;
break;
@@ -1167,10 +1305,17 @@ ali7101_write(int func, int addr, uint8_t val, void *priv)
case 0xd8:
dev->pmu_conf[addr] = val & 0xfd;
break;
case 0xd9:
if (dev->type == 1)
dev->pmu_conf[addr] = val & 0x3f;
break;
case 0xe0:
dev->pmu_conf[addr] = val & 0x03;
smbus_piix4_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
if (dev->type == 1)
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xc0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
else
smbus_ali7101_remap(dev->smbus, (dev->pmu_conf[0x15] << 8) | (dev->pmu_conf[0x14] & 0xe0), (dev->pmu_conf[0xe0] & 1) && (dev->pmu_conf[0x04] & 1) && (!(dev->pci_conf[0x5f] & 4)));
break;
case 0xe1:
@@ -1382,7 +1527,7 @@ ali1543_reset(void *priv)
ali5229_chip_reset(dev);
/* M5237 */
memset(dev->usb_conf, 0x00, sizeof(dev->pmu_conf));
memset(dev->usb_conf, 0x00, sizeof(dev->usb_conf));
dev->usb_conf[0x00] = 0xb9;
dev->usb_conf[0x01] = 0x10;
dev->usb_conf[0x02] = 0x37;
@@ -1444,6 +1589,8 @@ ali1543_reset(void *priv)
dev->pci_conf[0x03] = 0x15;
dev->pci_conf[0x04] = 0x0f;
dev->pci_conf[0x07] = 0x02;
if (dev->type == 1)
dev->pci_conf[0x08] = 0xc0;
dev->pci_conf[0x0a] = 0x01;
dev->pci_conf[0x0b] = 0x06;
@@ -1534,9 +1681,6 @@ ali1543_init(const device_t *info)
dev->acpi = device_add(&acpi_ali_device);
dev->nvr = device_add(&piix4_nvr_device);
/* APM */
// dev->apm = device_add(&apm_pci_device);
/* DMA */
dma_alias_set();
@@ -1563,7 +1707,7 @@ ali1543_init(const device_t *info)
dev->uart[1] = device_add_inst(&ns16550_device, 2);
/* Standard SMBus */
dev->smbus = device_add(&piix4_smbus_device);
dev->smbus = device_add(&ali7101_smbus_device);
/* Super I/O Configuration Mechanism */
dev->in_configuration_mode = 0;
@@ -1571,6 +1715,8 @@ ali1543_init(const device_t *info)
/* USB */
dev->usb = device_add(&usb_device);
dev->type = info->local;
pci_enable_mirq(0);
pci_enable_mirq(1);
pci_enable_mirq(2);
@@ -1597,3 +1743,16 @@ const device_t ali1543_device = {
NULL,
NULL
};
const device_t ali1543c_device = {
"ALi M1543C Desktop South Bridge",
DEVICE_PCI,
1,
ali1543_init,
ali1543_close,
ali1543_reset,
{ NULL },
NULL,
NULL,
NULL
};

757
src/chipset/ali1621.c Normal file
View File

@@ -0,0 +1,757 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ALi M1621/2 CPU-to-PCI Bridge.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/smram.h>
#include <86box/spd.h>
#include <86box/chipset.h>
typedef struct ali1621_t
{
uint8_t pci_conf[256];
smram_t * smram;
void * agp_bridge;
} ali1621_t;
#ifdef ENABLE_ALI1621_LOG
int ali1621_do_log = ENABLE_ALI1621_LOG;
static void
ali1621_log(const char *fmt, ...)
{
va_list ap;
if (ali1621_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define ali1621_log(fmt, ...)
#endif
static void
ali1621_smram_recalc(uint8_t val, ali1621_t *dev)
{
smram_disable_all();
if (val & 1) {
switch (val & 0x0c) {
case 0x00:
ali1621_log("SMRAM: D0000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xd0000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xd0000, 0x10000, 0x02);
break;
case 0x04:
ali1621_log("SMRAM: A0000 -> A0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0xa0000, 0xa0000, 0x20000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0xa0000, 0x20000, 0x02);
break;
case 0x08:
ali1621_log("SMRAM: 30000 -> B0000 (%i)\n", val & 2);
smram_enable(dev->smram, 0x30000, 0xb0000, 0x10000, val & 2, 1);
if (val & 0x10)
mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
break;
}
}
flushmmucache_nopc();
}
static void
ali1621_shadow_recalc(int cur_reg, ali1621_t *dev)
{
int i, bit, r_reg, w_reg;
uint32_t base, flags = 0;
shadowbios = shadowbios_write = 0;
for (i = 0; i < 16; i++) {
base = 0x000c0000 + (i << 14);
bit = i & 7;
r_reg = 0x56 + (i >> 3);
w_reg = 0x58 + (i >> 3);
flags = (dev->pci_conf[r_reg] & (1 << bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
flags |= ((dev->pci_conf[w_reg] & (1 << bit)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY);
if (base >= 0x000e0000) {
if (dev->pci_conf[r_reg] & (1 << bit))
shadowbios |= 1;
if (dev->pci_conf[w_reg] & (1 << bit))
shadowbios_write |= 1;
}
ali1621_log("%08X-%08X shadow: R%c, W%c\n", base, base + 0x00003fff,
(dev->pci_conf[r_reg] & (1 << bit)) ? 'I' : 'E', (dev->pci_conf[w_reg] & (1 << bit)) ? 'I' : 'E');
mem_set_mem_state_both(base, 0x00004000, flags);
}
flushmmucache_nopc();
}
static void
ali1621_mask_bar(ali1621_t *dev)
{
uint32_t bar, mask;
switch (dev->pci_conf[0xbc] & 0x0f) {
case 0x00:
default:
mask = 0x00000000;
break;
case 0x01:
mask = 0xfff00000;
break;
case 0x02:
mask = 0xffe00000;
break;
case 0x03:
mask = 0xffc00000;
break;
case 0x04:
mask = 0xff800000;
break;
case 0x06:
mask = 0xff000000;
break;
case 0x07:
mask = 0xfe000000;
break;
case 0x08:
mask = 0xfc000000;
break;
case 0x09:
mask = 0xf8000000;
break;
case 0x0a:
mask = 0xf0000000;
break;
}
bar = ((dev->pci_conf[0x13] << 24) | (dev->pci_conf[0x12] << 16)) & mask;
dev->pci_conf[0x12] = (bar >> 16) & 0xff;
dev->pci_conf[0x13] = (bar >> 24) & 0xff;
}
static void
ali1621_write(int func, int addr, uint8_t val, void *priv)
{
ali1621_t *dev = (ali1621_t *)priv;
switch (addr) {
case 0x04:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x05:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0xf0);
break;
case 0x0d:
dev->pci_conf[addr] = val & 0xf8;
break;
case 0x12:
dev->pci_conf[0x12] = (val & 0xc0);
ali1621_mask_bar(dev);
break;
case 0x13:
dev->pci_conf[0x13] = val;
ali1621_mask_bar(dev);
break;
case 0x34:
dev->pci_conf[addr] = val;
break;
case 0x40:
dev->pci_conf[addr] = val;
break;
case 0x41:
dev->pci_conf[addr] = val;
break;
case 0x42:
dev->pci_conf[addr] = val;
break;
case 0x43:
dev->pci_conf[addr] = val;
break;
case 0x44:
dev->pci_conf[addr] = val;
break;
case 0x45:
dev->pci_conf[addr] = val;
break;
case 0x46:
dev->pci_conf[addr] = val;
break;
case 0x47:
dev->pci_conf[addr] = val;
break;
case 0x48:
dev->pci_conf[addr] = val;
break;
case 0x49:
dev->pci_conf[addr] = val;
break;
case 0x4a:
dev->pci_conf[addr] = val;
break;
case 0x4b:
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x4c:
dev->pci_conf[addr] = val;
break;
case 0x4d:
dev->pci_conf[addr] = val;
break;
case 0x4e:
dev->pci_conf[addr] = val;
break;
case 0x4f:
dev->pci_conf[addr] = val;
break;
case 0x50:
dev->pci_conf[addr] = val & 0xef;
break;
case 0x51:
dev->pci_conf[addr] = val;
break;
case 0x52:
dev->pci_conf[addr] = val & 0x9f;
break;
case 0x53:
dev->pci_conf[addr] = val;
break;
case 0x54:
dev->pci_conf[addr] = val & 0xb4;
break;
case 0x55:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x56:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x57:
dev->pci_conf[addr] = val & 0x08;
break;
case 0x58:
dev->pci_conf[addr] = val;
break;
case 0x59:
dev->pci_conf[addr] = val;
break;
case 0x5a:
dev->pci_conf[addr] = val;
break;
case 0x5c:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x60:
dev->pci_conf[addr] = val;
break;
case 0x61:
dev->pci_conf[addr] = val;
break;
case 0x62:
dev->pci_conf[addr] = val;
break;
case 0x63:
dev->pci_conf[addr] = val;
break;
case 0x64:
dev->pci_conf[addr] = val & 0xb7;
break;
case 0x65:
dev->pci_conf[addr] = val & 0x01;
break;
case 0x66:
dev->pci_conf[addr] &= ~(val & 0x33);
break;
case 0x67:
dev->pci_conf[addr] = val;
break;
case 0x68:
dev->pci_conf[addr] = val;
break;
case 0x69:
dev->pci_conf[addr] = val;
break;
case 0x6c ... case 0x7b:
/* Bits 22:20 = DRAM Row size:
- 000: 4 MB;
- 001: 8 MB;
- 010: 16 MB;
- 011: 32 MB;
- 100: 64 MB;
- 101: 128 MB;
- 110: 256 MB;
- 111: Reserved. */
dev->pci_conf[addr] = val;
break;
case 0x7c ... 0x7f:
dev->pci_conf[addr] = val;
break;
case 0x80:
dev->pci_conf[addr] = val;
break;
case 0x81:
dev->pci_conf[addr] = val & 0xdf;
break;
case 0x82:
dev->pci_conf[addr] = val & 0xf7;
break;
case 0x54:
dev->pci_conf[addr] = val & 0x3c;
if (mem_size > 0xe00000)
mem_set_mem_state_both(0xe00000, 0x100000, (val & 0x20) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
if (mem_size > 0xf00000)
mem_set_mem_state_both(0xf00000, 0x100000, (val & 0x10) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
mem_set_mem_state_both(0xa0000, 0x20000, (val & 8) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY));
mem_set_mem_state_both(0x80000, 0x20000, (val & 4) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL));
flushmmucache_nopc();
break;
case 0x55: /* SMRAM */
dev->pci_conf[addr] = val & 0x1f;
ali1621_smram_recalc(val, dev);
break;
case 0x56 ... 0x59: /* Shadow RAM */
dev->pci_conf[addr] = val;
ali1621_shadow_recalc(val, dev);
break;
case 0x5a: case 0x5b:
dev->pci_conf[addr] = val;
break;
case 0x5c:
dev->pci_conf[addr] = val;
break;
case 0x5d:
dev->pci_conf[addr] = val & 0x17;
break;
case 0x5e:
dev->pci_conf[addr] = val;
break;
case 0x5f:
dev->pci_conf[addr] = val & 0xc1;
break;
case 0x60 ... 0x6f: /* DRB's */
dev->pci_conf[addr] = val;
spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1);
break;
case 0x70:
dev->pci_conf[addr] = val;
break;
case 0x71:
dev->pci_conf[addr] = val;
break;
case 0x72:
dev->pci_conf[addr] = val & 0xc7;
break;
case 0x73:
dev->pci_conf[addr] = val & 0x1f;
break;
case 0x84: case 0x85:
dev->pci_conf[addr] = val;
break;
case 0x86:
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x87: /* H2PO */
dev->pci_conf[addr] = val;
/* Find where the Shut-down Special cycle is initiated. */
// if (!(val & 0x20))
// outb(0x92, 0x01);
break;
case 0x88:
dev->pci_conf[addr] = val;
break;
case 0x89:
dev->pci_conf[addr] = val;
break;
case 0x8a:
dev->pci_conf[addr] = val;
break;
case 0x8b:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x8c:
dev->pci_conf[addr] = val;
break;
case 0x8d:
dev->pci_conf[addr] = val;
break;
case 0x8e:
dev->pci_conf[addr] = val;
break;
case 0x8f:
dev->pci_conf[addr] = val;
break;
case 0x90:
dev->pci_conf[addr] = val;
pci_bridge_set_ctl(dev->agp_bridge, val);
break;
case 0x91:
dev->pci_conf[addr] = val;
break;
case 0xb4:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val & 0x03;
break;
case 0xb5:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val & 0x02;
break;
case 0xb7:
if (dev->pci_conf[0x90] & 0x01)
dev->pci_conf[addr] = val;
break;
case 0xb8:
dev->pci_conf[addr] = val & 0x03;
break;
case 0xb9:
dev->pci_conf[addr] = val & 0x03;
break;
case 0xbb:
dev->pci_conf[addr] = val;
break;
case 0xbc:
dev->pci_conf[addr] = val & 0x0f;
ali1621_mask_bar(dev);
break;
case 0xbd:
dev->pci_conf[addr] = val & 0xf0;
break;
case 0xbe: case 0xbf:
dev->pci_conf[addr] = val;
break;
case 0xc0:
dev->pci_conf[addr] = val & 0x90;
break;
case 0xc1: case 0xc2:
case 0xc3:
dev->pci_conf[addr] = val;
break;
case 0xc8: case 0xc9:
dev->pci_conf[addr] = val;
break;
case 0xd1:
dev->pci_conf[addr] = val & 0xf1;
break;
case 0xd2: case 0xd3:
dev->pci_conf[addr] = val;
break;
case 0xe0: case 0xe1:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val;
break;
case 0xe2:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0x3f;
break;
case 0xe3:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0xfe;
break;
case 0xe4:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0x03;
break;
case 0xe5:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val;
break;
case 0xe6:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val & 0xc0;
break;
case 0xe7:
if (dev->pci_conf[0x90] & 0x20)
dev->pci_conf[addr] = val;
break;
case 0xe8: case 0xe9:
if (dev->pci_conf[0x90] & 0x04)
dev->pci_conf[addr] = val;
break;
case 0xea:
dev->pci_conf[addr] = val & 0xcf;
break;
case 0xeb:
dev->pci_conf[addr] = val & 0xcf;
break;
case 0xec:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0xed:
dev->pci_conf[addr] = val;
break;
case 0xee:
dev->pci_conf[addr] = val & 0x3e;
break;
case 0xef:
dev->pci_conf[addr] = val;
break;
case 0xf3:
dev->pci_conf[addr] = val & 0x08;
break;
case 0xf5:
dev->pci_conf[addr] = val;
break;
case 0xf6:
dev->pci_conf[addr] = val;
break;
case 0xf7:
dev->pci_conf[addr] = val & 0x43;
break;
}
}
static uint8_t
ali1621_read(int func, int addr, void *priv)
{
ali1621_t *dev = (ali1621_t *)priv;
uint8_t ret = 0xff;
ret = dev->pci_conf[addr];
return ret;
}
static void
ali1621_reset(void *priv)
{
ali1621_t *dev = (ali1621_t *)priv;
int i;
/* Default Registers */
dev->pci_conf[0x00] = 0xb9;
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x21;
dev->pci_conf[0x03] = 0x16;
dev->pci_conf[0x04] = 0x06;
dev->pci_conf[0x05] = 0x00;
dev->pci_conf[0x06] = 0x10;
dev->pci_conf[0x07] = 0x04;
dev->pci_conf[0x08] = 0x01;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x10] = 0x08;
dev->pci_conf[0x34] = 0xb0;
dev->pci_conf[0x40] = 0x0c;
dev->pci_conf[0x41] = 0x0c;
dev->pci_conf[0x4c] = 0x04;
dev->pci_conf[0x4d] = 0x04;
dev->pci_conf[0x4e] = 0x7f;
dev->pci_conf[0x4f] = 0x7f;
dev->pci_conf[0x50] = 0x0c;
dev->pci_conf[0x53] = 0x02;
dev->pci_conf[0x5a] = 0x02;
dev->pci_conf[0x63] = 0x02;
dev->pci_conf[0x6c] = dev->pci_conf[0x70] = dev->pci_conf[0x74] = dev->pci_conf[0x78] = 0xff;
dev->pci_conf[0x6d] = dev->pci_conf[0x71] = dev->pci_conf[0x75] = dev->pci_conf[0x79] = 0xff;
dev->pci_conf[0x6e] = dev->pci_conf[0x72] = dev->pci_conf[0x76] = dev->pci_conf[0x7a] = 0x00;
dev->pci_conf[0x6f] = dev->pci_conf[0x73] = dev->pci_conf[0x77] = dev->pci_conf[0x7b] = 0xe0;
dev->pci_conf[0x6f] |= 0x06;
dev->pci_conf[0x7c] = 0x11;
dev->pci_conf[0x7d] = 0xc4;
dev->pci_conf[0x7e] = 0xc7;
dev->pci_conf[0x80] = 0x01;
dev->pci_conf[0x81] = 0xc0;
dev->pci_conf[0x89] = 0x20;
dev->pci_conf[0x8a] = 0x20;
dev->pci_conf[0x91] = 0x13;
dev->pci_conf[0xb0] = 0x02;
dev->pci_conf[0xb1] = 0xe0;
dev->pci_conf[0xb2] = 0x10;
dev->pci_conf[0xb4] = 0x03;
dev->pci_conf[0xb5] = 0x02;
dev->pci_conf[0xb7] = 0x1c;
dev->pci_conf[0xc8] = 0xbf;
dev->pci_conf[0xc9] = 0x0a;
dev->pci_conf[0xe0] = 0x01;
cpu_cache_int_enabled = 1;
ali1621_write(0, 0x42, 0x00, dev);
ali1621_write(0, 0x54, 0x00, dev);
ali1621_write(0, 0x55, 0x00, dev);
for (i = 0; i < 4; i++)
ali1621_write(0, 0x56 + i, 0x00, dev);
ali1621_write(0, 0x60 + i, 0x07, dev);
ali1621_write(0, 0x61 + i, 0x40, dev);
for (i = 0; i < 14; i += 2) {
ali1621_write(0, 0x62 + i, 0x00, dev);
ali1621_write(0, 0x63 + i, 0x00, dev);
}
}
static void
ali1621_close(void *priv)
{
ali1621_t *dev = (ali1621_t *)priv;
smram_del(dev->smram);
free(dev);
}
static void *
ali1621_init(const device_t *info)
{
ali1621_t *dev = (ali1621_t *)malloc(sizeof(ali1621_t));
memset(dev, 0, sizeof(ali1621_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1621_read, ali1621_write, dev);
dev->smram = smram_add();
ali1621_reset(dev);
dev->agp_bridge = device_add(&ali5243_agp_device);
return dev;
}
const device_t ali1621_device = {
"ALi M1621 CPU-to-PCI Bridge",
DEVICE_PCI,
0,
ali1621_init,
ali1621_close,
ali1621_reset,
{NULL},
NULL,
NULL,
NULL
};

2
src/chipset/intel_piix.c
View File

@@ -45,7 +45,7 @@
#include <86box/hdc_ide_sff8038i.h>
#include <86box/usb.h>
#include <86box/machine.h>
#include <86box/smbus_piix4.h>
#include <86box/smbus.h>
#include <86box/chipset.h>

2
src/chipset/via_pipc.c
View File

@@ -45,7 +45,7 @@
#include <86box/hdc_ide_sff8038i.h>
#include <86box/usb.h>
#include <86box/machine.h>
#include <86box/smbus_piix4.h>
#include <86box/smbus.h>
#include <86box/chipset.h>
#include <86box/sio.h>
#include <86box/hwm.h>

4
src/device/CMakeLists.txt
View File

@@ -16,8 +16,8 @@
add_library(dev OBJECT bugger.c hwm.c hwm_lm75.c hwm_lm78.c hwm_gl518sm.c
hwm_vt82c686.c ibm_5161.c isamem.c isartc.c ../lpt.c pci_bridge.c
postcard.c serial.c vpc2007.c clock_ics9xxx.c isapnp.c i2c.c i2c_gpio.c
smbus_piix4.c keyboard.c keyboard_xt.c keyboard_at.c mouse.c mouse_bus.c
mouse_serial.c mouse_ps2.c phoenix_486_jumper.c)
smbus_piix4.c smbus_ali7101.c keyboard.c keyboard_xt.c keyboard_at.c
mouse.c mouse_bus.c mouse_serial.c mouse_ps2.c phoenix_486_jumper.c)
if(LASERXT)
target_compile_definitions(dev PRIVATE USE_LASERXT)

157
src/device/pci_bridge.c
View File

@@ -33,6 +33,7 @@
#define PCI_BRIDGE_DEC_21150 0x10110022
#define AGP_BRIDGE_ALI_M5243 0x10b95243
#define AGP_BRIDGE_INTEL_440LX 0x80867181
#define AGP_BRIDGE_INTEL_440BX 0x80867191
#define AGP_BRIDGE_INTEL_440GX 0x808671a1
@@ -41,15 +42,16 @@
#define AGP_BRIDGE_VIA_691 0x11068691
#define AGP_BRIDGE_VIA_8601 0x11068601
#define AGP_BRIDGE_ALI(x) (((x) >> 16) == 0x10b9)
#define AGP_BRIDGE_INTEL(x) (((x) >> 16) == 0x8086)
#define AGP_BRIDGE_VIA(x) (((x) >> 16) == 0x1106)
#define AGP_BRIDGE(x) ((x) >= AGP_BRIDGE_VIA_597)
#define AGP_BRIDGE(x) ((x) >= AGP_BRIDGE_ALI_M5243)
typedef struct
{
uint32_t local;
uint8_t type;
uint8_t type, ctl;
uint8_t regs[256];
uint8_t bus_index;
@@ -77,6 +79,15 @@ pci_bridge_log(const char *fmt, ...)
#endif
void
pci_bridge_set_ctl(void *priv, uint8_t ctl)
{
pci_bridge_t *dev = (pci_bridge_t *) priv;
dev->ctl = ctl;
}
static void
pci_bridge_write(int func, int addr, uint8_t val, void *priv)
{
@@ -94,21 +105,24 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x11: case 0x12: case 0x13: case 0x14:
case 0x15: case 0x16: case 0x17: case 0x1e:
case 0x34: case 0x3d: case 0x67: case 0xdc:
case 0xdd: case 0xde: case 0xdf: case 0xe0:
case 0xe1: case 0xe2: case 0xe3:
case 0xdd: case 0xde: case 0xdf:
return;
case 0x04:
if (AGP_BRIDGE_INTEL(dev->local)) {
if (dev->local == AGP_BRIDGE_INTEL_440BX)
val &= 0x1f;
} else
} else if (AGP_BRIDGE_ALI(dev->local))
val |= 0x02;
else
val &= 0x67;
break;
case 0x05:
if (AGP_BRIDGE_INTEL(dev->local))
val &= 0x01;
else if (AGP_BRIDGE_ALI(dev->local))
val &= 0x01;
else
val &= 0x03;
break;
@@ -116,6 +130,8 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x07:
if (dev->local == AGP_BRIDGE_INTEL_440LX)
dev->regs[addr] &= ~(val & 0x40);
else if (AGP_BRIDGE_ALI(dev->local))
dev->regs[addr] &= ~(val & 0xf8);
return;
case 0x0c: case 0x18:
@@ -129,6 +145,8 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
return;
else if (AGP_BRIDGE_INTEL(dev->local))
val &= 0xf8;
else if (AGP_BRIDGE_ALI(dev->local))
val &= 0xf8;
break;
case 0x19:
@@ -144,7 +162,8 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
else if ((dev->local == AGP_BRIDGE_INTEL_440BX) ||
(dev->local == AGP_BRIDGE_INTEL_440GX))
dev->regs[addr] &= ~(val & 0xf0);
}
} else if (AGP_BRIDGE_ALI(dev->local))
dev->regs[addr] &= ~(val & 0xf0);
return;
case 0x1c: case 0x1d: case 0x20: case 0x22:
@@ -152,6 +171,11 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
val &= 0xf0;
break;
case 0x3c:
if (!(dev->ctl & 0x80))
return;
break;
case 0x3e:
if (AGP_BRIDGE_VIA(dev->local))
val &= 0x0c;
@@ -170,7 +194,9 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
if (dev->local == AGP_BRIDGE_INTEL_440LX) {
dev->regs[addr] = ((dev->regs[addr] & 0x04) | (val & 0x02)) & ~(val & 0x04);
return;
} else if (AGP_BRIDGE(dev->local))
} else if (AGP_BRIDGE_ALI(dev->local))
val &= 0x06;
else if (AGP_BRIDGE(dev->local))
return;
else if (dev->local == PCI_BRIDGE_DEC_21150)
val &= 0x0f;
@@ -207,6 +233,94 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
if (dev->local == PCI_BRIDGE_DEC_21150)
val &= 0x3f;
break;
case 0x86:
if (AGP_BRIDGE_ALI(dev->local))
val &= 0x3f;
break;
case 0x87:
if (AGP_BRIDGE_ALI(dev->local))
val &= 0x60;
break;
case 0x88:
if (AGP_BRIDGE_ALI(dev->local))
val &= 0x8c;
break;
case 0x8b:
if (AGP_BRIDGE_ALI(dev->local))
val &= 0x0f;
break;
case 0x8c:
if (AGP_BRIDGE_ALI(dev->local))
val &= 0x83;
break;
case 0x8d:
if (AGP_BRIDGE_ALI(dev->local))
return;
break;
case 0xe0: case 0xe1:
if (AGP_BRIDGE_ALI(dev->local)) {
if (!(dev->ctl & 0x20))
return;
} else
return;
break;
case 0xe2:
if (AGP_BRIDGE_ALI(dev->local)) {
if (dev->ctl & 0x20)
val &= 0x3f;
else
return;
} else
return;
break;
case 0xe3:
if (AGP_BRIDGE_ALI(dev->local)) {
if (dev->ctl & 0x20)
val &= 0xfe;
else
return;
} else
return;
break;
case 0xe4:
if (AGP_BRIDGE_ALI(dev->local)) {
if (dev->ctl & 0x20)
val &= 0x03;
else
return;
}
break;
case 0xe5:
if (AGP_BRIDGE_ALI(dev->local)) {
if (!(dev->ctl & 0x20))
return;
}
break;
case 0xe6:
if (AGP_BRIDGE_ALI(dev->local)) {
if (dev->ctl & 0x20)
val &= 0xc0;
else
return;
}
break;
case 0xe7:
if (AGP_BRIDGE_ALI(dev->local)) {
if (!(dev->ctl & 0x20))
return;
}
break;
}
dev->regs[addr] = val;
@@ -251,6 +365,21 @@ pci_bridge_reset(void *priv)
dev->regs[0x07] = 0x02;
break;
case AGP_BRIDGE_ALI_M5243:
dev->regs[0x04] = 0x06;
dev->regs[0x07] = 0x04;
dev->regs[0x0d] = 0x20;
dev->regs[0x19] = 0x01;
dev->regs[0x1b] = 0x20;
dev->regs[0x34] = 0xe0;
dev->regs[0x89] = 0x20;
dev->regs[0x8a] = 0xa0;
dev->regs[0x8e] = 0x20;
dev->regs[0x8f] = 0x20;
dev->regs[0xe0] = 0x01;
pci_remap_bus(dev->bus_index, 0x01);
break;
case AGP_BRIDGE_INTEL_440LX:
dev->regs[0x06] = 0xa0;
dev->regs[0x07] = 0x02;
@@ -362,6 +491,20 @@ const device_t dec21150_device =
};
/* AGP bridges */
const device_t ali5243_agp_device =
{
"ALi M5243 AGP Bridge",
DEVICE_PCI,
AGP_BRIDGE_ALI_M5243,
pci_bridge_init,
NULL,
pci_bridge_reset,
{ NULL },
NULL,
NULL,
NULL
};
const device_t i440lx_agp_device =
{
"Intel 82443LX/EX AGP Bridge",

312
src/device/smbus_ali7101.c Normal file
View File

@@ -0,0 +1,312 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a generic ALi M7101-compatible SMBus host
* controller.
*
* Authors: RichardG, <richardg867@gmail.com>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020,2021 RichardG.
* Copyright 2021 Miran Grca.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/i2c.h>
#include <86box/smbus.h>
#ifdef ENABLE_SMBUS_ALI7101_LOG
int smbus_ali7101_do_log = ENABLE_SMBUS_ALI7101_LOG;
static void
smbus_ali7101_log(const char *fmt, ...)
{
va_list ap;
if (smbus_ali7101_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define smbus_ali7101_log(fmt, ...)
#endif
static uint8_t
smbus_ali7101_read(uint16_t addr, void *priv)
{
smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
uint8_t ret = 0x00;
switch (addr - dev->io_base) {
case 0x00:
ret = dev->stat;
break;
case 0x02:
dev->index = 0; /* reading from this resets the block data index */
ret = dev->ctl;
break;
case 0x03:
ret = dev->addr;
break;
case 0x04:
ret = dev->data0;
break;
case 0x05:
ret = dev->data1;
break;
case 0x06:
ret = dev->data[dev->index++];
if (dev->index >= SMBUS_ALI7101_BLOCK_DATA_SIZE)
dev->index = 0;
break;
case 0x07:
ret = dev->cmd;
break;
}
smbus_ali7101_log("SMBus ALI7101: read(%02X) = %02x\n", addr, ret);
return ret;
}
static void
smbus_ali7101_write(uint16_t addr, uint8_t val, void *priv)
{
smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
uint8_t smbus_addr, cmd, read, prev_stat;
uint16_t timer_bytes = 0;
smbus_ali7101_log("SMBus ALI7101: write(%02X, %02X)\n", addr, val);
prev_stat = dev->next_stat;
dev->next_stat = 0x04;
switch (addr - dev->io_base) {
case 0x00:
dev->stat &= ~(val & 0xe2);
/* Make sure IDLE is set if we're not busy or errored. */
if (dev->stat == 0x00)
dev->stat = 0x04;
break;
case 0x01:
dev->ctl = val & 0xfc;
if (val & 0x04) { /* cancel an in-progress command if KILL is set */
if (prev_stat) { /* cancel only if a command is in progress */
timer_disable(&dev->response_timer);
dev->stat = 0x80; /* raise FAILED */
}
} else if (val & 0x08) { /* T_OUT_CMD */
if (prev_stat) { /* cancel only if a command is in progress */
timer_disable(&dev->response_timer);
dev->stat = 0x20; /* raise DEVICE_ERR */
}
}
break;
case 0x02:
/* dispatch command if START is set */
timer_bytes++; /* address */
smbus_addr = (dev->addr >> 1);
read = dev->addr & 0x01;
cmd = (dev->ctl >> 4) & 0x7;
smbus_ali7101_log("SMBus ALI7101: addr=%02X read=%d protocol=%X cmd=%02X data0=%02X data1=%02X\n", smbus_addr, read, cmd, dev->cmd, dev->data0, dev->data1);
/* Raise DEV_ERR if no device is at this address, or if the device returned NAK when starting the transfer. */
if (!i2c_start(i2c_smbus, smbus_addr, read)) {
dev->next_stat = 0x20;
break;
}
dev->next_stat = 0x10; /* raise INTER (command completed) by default */
/* Decode the command protocol. */
switch (cmd) {
case 0x0: /* quick R/W */
break;
case 0x1: /* byte R/W */
if (read) /* byte read */
dev->data0 = i2c_read(i2c_smbus, smbus_addr);
else /* byte write */
i2c_write(i2c_smbus, smbus_addr, dev->data0);
timer_bytes++;
break;
case 0x2: /* byte data R/W */
/* command write */
i2c_write(i2c_smbus, smbus_addr, dev->cmd);
timer_bytes++;
if (read) /* byte read */
dev->data0 = i2c_read(i2c_smbus, smbus_addr);
else /* byte write */
i2c_write(i2c_smbus, smbus_addr, dev->data0);
timer_bytes++;
break;
case 0x3: /* word data R/W */
/* command write */
i2c_write(i2c_smbus, smbus_addr, dev->cmd);
timer_bytes++;
if (read) { /* word read */
dev->data0 = i2c_read(i2c_smbus, smbus_addr);
dev->data1 = i2c_read(i2c_smbus, smbus_addr);
} else { /* word write */
i2c_write(i2c_smbus, smbus_addr, dev->data0);
i2c_write(i2c_smbus, smbus_addr, dev->data1);
}
timer_bytes += 2;
break;
case 0x4: /* block R/W */
timer_bytes++; /* count the SMBus length byte now */
/* fall-through */
default: /* unknown */
dev->next_stat = 0x20; /* raise DEV_ERR */
timer_bytes = 0;
break;
}
/* Finish transfer. */
i2c_stop(i2c_smbus, smbus_addr);
break;
case 0x03:
dev->addr = val;
break;
case 0x04:
dev->data0 = val;
break;
case 0x05:
dev->data1 = val;
break;
case 0x06:
dev->data[dev->index++] = val;
if (dev->index >= SMBUS_ALI7101_BLOCK_DATA_SIZE)
dev->index = 0;
break;
case 0x07:
dev->cmd = val;
break;
}
if (dev->next_stat != 0x04) { /* schedule dispatch of any pending status register update */
dev->stat = 0x08; /* raise HOST_BUSY while waiting */
timer_disable(&dev->response_timer);
/* delay = ((half clock for start + half clock for stop) + (bytes * (8 bits + ack))) * 60us period measured on real VIA 686B */
timer_set_delay_u64(&dev->response_timer, (1 + (timer_bytes * 9)) * 60 * TIMER_USEC);
}
}
static void
smbus_ali7101_response(void *priv)
{
smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
/* Dispatch the status register update. */
dev->stat = dev->next_stat;
}
void
smbus_ali7101_remap(smbus_ali7101_t *dev, uint16_t new_io_base, uint8_t enable)
{
if (dev->io_base)
io_removehandler(dev->io_base, 0x10, smbus_ali7101_read, NULL, NULL, smbus_ali7101_write, NULL, NULL, dev);
dev->io_base = new_io_base;
smbus_ali7101_log("SMBus ALI7101: remap to %04Xh (%sabled)\n", dev->io_base, enable ? "en" : "dis");
if (enable && dev->io_base)
io_sethandler(dev->io_base, 0x10, smbus_ali7101_read, NULL, NULL, smbus_ali7101_write, NULL, NULL, dev);
}
static void
smbus_ali7101_reset(void *priv)
{
smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
timer_disable(&dev->response_timer);
dev->stat = 0x04;
}
static void *
smbus_ali7101_init(const device_t *info)
{
smbus_ali7101_t *dev = (smbus_ali7101_t *) malloc(sizeof(smbus_ali7101_t));
memset(dev, 0, sizeof(smbus_ali7101_t));
dev->local = info->local;
dev->stat = 0x04;
/* We save the I2C bus handle on dev but use i2c_smbus for all operations because
dev and therefore dev->i2c will be invalidated if a device triggers a hard reset. */
i2c_smbus = dev->i2c = i2c_addbus("smbus_ali7101");
timer_add(&dev->response_timer, smbus_ali7101_response, dev, 0);
return dev;
}
static void
smbus_ali7101_close(void *priv)
{
smbus_ali7101_t *dev = (smbus_ali7101_t *) priv;
if (i2c_smbus == dev->i2c)
i2c_smbus = NULL;
i2c_removebus(dev->i2c);
free(dev);
}
const device_t ali7101_smbus_device = {
"ALi M7101-compatible SMBus Host Controller",
DEVICE_AT,
0,
smbus_ali7101_init, smbus_ali7101_close, smbus_ali7101_reset,
{ NULL }, NULL, NULL,
NULL
};

2
src/device/smbus_piix4.c
View File

@@ -26,7 +26,7 @@
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/i2c.h>
#include <86box/smbus_piix4.h>
#include <86box/smbus.h>
#ifdef ENABLE_SMBUS_PIIX4_LOG

2
src/include/86box/chipset.h
View File

@@ -26,7 +26,9 @@ extern const device_t ali1217_device;
extern const device_t ali1429_device;
extern const device_t ali1489_device;
extern const device_t ali1531_device;
extern const device_t ali1541_device;
extern const device_t ali1543_device;
extern const device_t ali1543c_device;
#if defined(DEV_BRANCH) && defined(USE_M6117)
extern const device_t ali6117d_device;
#endif

3
src/include/86box/machine.h
View File

@@ -497,6 +497,9 @@ extern int machine_at_m560_init(const machine_t *);
extern int machine_at_ms5164_init(const machine_t *);
/* m_at_sockets7.c */
extern int machine_at_m579_init(const machine_t *);
extern int machine_at_ga_5aa_init(const machine_t *);
extern int machine_at_ax59pro_init(const machine_t *);
extern int machine_at_mvp3_init(const machine_t *);
extern int machine_at_ficva503a_init(const machine_t *);

7
src/include/86box/pci.h
View File

@@ -45,10 +45,6 @@
#define PCI_MIRQ1 1
#define PCI_MIRQ2 2
#define PCI_MIRQ3 3
#define PCI_MIRQ4 4
#define PCI_MIRQ5 5
#define PCI_MIRQ6 6
#define PCI_MIRQ7 7
#define PCI_IRQ_DISABLED -1
@@ -123,10 +119,13 @@ extern void trc_init(void);
extern uint8_t trc_read(uint16_t port, void *priv);
extern void trc_write(uint16_t port, uint8_t val, void *priv);
extern void pci_bridge_set_ctl(void *priv, uint8_t ctl);
#ifdef EMU_DEVICE_H
extern const device_t dec21150_device;
extern const device_t ali5243_agp_device;
extern const device_t i440lx_agp_device;
extern const device_t i440bx_agp_device;
extern const device_t i440gx_agp_device;

18
src/include/86box/smbus_piix4.h → src/include/86box/smbus.h
View File

@@ -6,7 +6,7 @@
*
* This file is part of the 86Box distribution.
*
* Definitions for the generic PIIX4-compatible SMBus host controller.
* Definitions for the SMBus host controllers.
*
*
*
@@ -21,6 +21,9 @@
#define SMBUS_PIIX4_BLOCK_DATA_SIZE 32
#define SMBUS_PIIX4_BLOCK_DATA_MASK (SMBUS_PIIX4_BLOCK_DATA_SIZE - 1)
#define SMBUS_ALI7101_BLOCK_DATA_SIZE 32
#define SMBUS_ALI7101_BLOCK_DATA_MASK (SMBUS_ALI7101_BLOCK_DATA_SIZE - 1)
enum {
SMBUS_PIIX4 = 0,
@@ -37,13 +40,26 @@ typedef struct {
void *i2c;
} smbus_piix4_t;
typedef struct {
uint32_t local;
uint16_t io_base;
uint8_t stat, next_stat, ctl, cmd, addr,
data0, data1,
index, data[SMBUS_ALI7101_BLOCK_DATA_SIZE];
pc_timer_t response_timer;
void *i2c;
} smbus_ali7101_t;
extern void smbus_piix4_remap(smbus_piix4_t *dev, uint16_t new_io_base, uint8_t enable);
extern void smbus_ali7101_remap(smbus_ali7101_t *dev, uint16_t new_io_base, uint8_t enable);
#ifdef EMU_DEVICE_H
extern const device_t piix4_smbus_device;
extern const device_t via_smbus_device;
extern const device_t ali7101_smbus_device;
#endif

66
src/machine/m_at_sockets7.c
View File

@@ -42,6 +42,72 @@
#include <86box/machine.h>
int
machine_at_m579_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/m579/MS6260S_Socket7_ALi_M1542_AMI.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x14, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&ali1541_device);
device_add(&ali1543c_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
int
machine_at_ga_5aa_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ga-5aa/GA-5AA.F7b",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x03, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&ali1541_device);
device_add(&ali1543c_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 128);
return ret;
}
int
machine_at_ax59pro_init(const machine_t *model)
{

6
src/machine/machine_table.c
View File

@@ -667,6 +667,12 @@ const machine_t machines[] = {
{ "[ALi ALADDiN IV] MSI MS-5164", "ms5164", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 2100, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 262144, 8192, 255, machine_at_ms5164_init, NULL },
/* Super Socket 7 machines */
/* ALi ALADDiN V */
/* Is the exact same as the Matsonic MS6260S. Has the ALi M1543C southbridge
with on-chip KBC. */
{ "[ALi ALADDiN V] PC Chips M579", "m579", MACHINE_TYPE_SOCKETS7, CPU_PKG_SOCKET5_7, 0, 66666667, 124242424, 2000, 3200, 1.5, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 1024,2097152, 8192, 255, machine_at_m579_init, NULL },
{ "[ALi ALADDiN V] Gigabyte GA-5AA", "ga-5aa", MACHINE_TYPE_SOCKETS7, CPU_PKG_SOCKET5_7, 0, 66666667, 124242424, 2000, 3200, 1.5, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 1024,2097152, 8192, 255, machine_at_ga_5aa_init, NULL },
/* Apollo MVP3 */
/* Has the VIA VT82C586B southbridge with on-chip KBC identical to the VIA
VT82C42N. */

4
src/win/Makefile.mingw
View File

@@ -601,7 +601,7 @@ CPUOBJ := cpu.o cpu_table.o fpu.o x86.o \
CHIPSETOBJ := acc2168.o \
cs4031.o cs8230.o \
ali1217.o ali1429.o ali1489.o ali1531.o ali1543.o \
ali1217.o ali1429.o ali1489.o ali1531.o ali1541.o ali1543.o \
gc100.o headland.o \
intel_82335.o intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o \
@@ -633,7 +633,7 @@ MCHOBJ := machine.o machine_table.o \
ifeq ($(NEW_KBC), y)
DEVOBJ := bugger.o hwm.o hwm_lm75.o hwm_lm78.o hwm_gl518sm.o hwm_vt82c686.o ibm_5161.o isamem.o isartc.o \
lpt.o pci_bridge.o postcard.o serial.o vpc2007.o clock_ics9xxx.o isapnp.o \
i2c.o i2c_gpio.o smbus_piix4.o \
i2c.o i2c_gpio.o smbus_ali7101.o smbus_piix4.o \
keyboard.o \
keyboard_xt.o kbc_at.o kbd_at.o \
mouse.o \