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Implement DRB locking for VIA Apollo chipsets

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This commit is contained in:
RichardG867
2020-06-26 22:05:32 -03:00
parent 0b871b56c0
commit aea5461255
2 changed files with 23 additions and 6 deletions
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21
src/mem/spd.c
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@@ -407,10 +407,14 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
void
spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
{
uint8_t row, dimm;
uint8_t row, dimm, drb, apollo = 0;
uint16_t size, vslots[SPD_MAX_SLOTS];
spd_log("DRB write begin\n");
/* Special case for VIA Apollo Pro family, which jumps from 5F to 56. */
if (reg_max < reg_min) {
apollo = reg_max;
reg_max = reg_min + 8;
}
/* No SPD: split SIMMs into pairs as if they were "DIMM"s. */
if (!spd_present) {
@@ -437,11 +441,16 @@ spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit
size = (vslots[dimm] >> 1);
}
/* Populate DRB register, adding the previous DRB's value.
/* Determine the DRB register to write. */
drb = reg_min + row;
if ((apollo) && ((drb & 0xf) < 0x8))
drb = apollo + (drb & 0xf);
/* Write DRB register, adding the previous DRB's value.
This will intentionally overflow on 440GX with 2 GB. */
regs[reg_min + row] = ((row > 0) ? regs[reg_min + row - 1] : 0);
regs[drb] = ((row > 0) ? regs[drb - 1] : 0);
if (size)
regs[reg_min + row] += (size / drb_unit);
spd_log("DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[reg_min + row]);
regs[drb] += (size / drb_unit);
spd_log("DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[drb]);
}
}