diff --git a/src/codegen_new/x86_ops_shift.h b/src/codegen_new/x86_ops_shift.h
deleted file mode 100644
index 106a5701a..000000000
--- a/src/codegen_new/x86_ops_shift.h
+++ /dev/null
@@ -1,607 +0,0 @@
-#define OP_SHIFT_b(c, ea32) \
- { \
- uint8_t temp_orig = temp; \
- if (!c) return 0; \
- flags_rebuild(); \
- switch (rmdat & 0x38) \
- { \
- case 0x00: /*ROL b, c*/ \
- temp = (temp << (c & 7)) | (temp >> (8-(c & 7))); \
- seteab(temp); if (cpu_state.abrt) return 1; \
- set_flags_rotate(FLAGS_ROL8, temp); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x08: /*ROR b,CL*/ \
- temp = (temp >> (c & 7)) | (temp << (8-(c & 7))); \
- seteab(temp); if (cpu_state.abrt) return 1; \
- set_flags_rotate(FLAGS_ROR8, temp); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x10: /*RCL b,CL*/ \
- temp2 = cpu_state.flags & C_FLAG; \
- if (is486) CLOCK_CYCLES_ALWAYS(c); \
- while (c > 0) \
- { \
- tempc = temp2 ? 1 : 0; \
- temp2 = temp & 0x80; \
- temp = (temp << 1) | tempc; \
- c--; \
- } \
- seteab(temp); if (cpu_state.abrt) return 1; \
- cpu_state.flags &= ~(C_FLAG | V_FLAG); \
- if (temp2) cpu_state.flags |= C_FLAG; \
- if ((cpu_state.flags & C_FLAG) ^ (temp >> 7)) cpu_state.flags |= V_FLAG; \
- CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
- PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x18: /*RCR b,CL*/ \
- temp2 = cpu_state.flags & C_FLAG; \
- if (is486) CLOCK_CYCLES_ALWAYS(c); \
- while (c > 0) \
- { \
- tempc = temp2 ? 0x80 : 0; \
- temp2 = temp & 1; \
- temp = (temp >> 1) | tempc; \
- c--; \
- } \
- seteab(temp); if (cpu_state.abrt) return 1; \
- cpu_state.flags &= ~(C_FLAG | V_FLAG); \
- if (temp2) cpu_state.flags |= C_FLAG; \
- if ((temp ^ (temp >> 1)) & 0x40) cpu_state.flags |= V_FLAG; \
- CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
- PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x20: case 0x30: /*SHL b,CL*/ \
- seteab(temp << c); if (cpu_state.abrt) return 1; \
- set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x28: /*SHR b,CL*/ \
- seteab(temp >> c); if (cpu_state.abrt) return 1; \
- set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x38: /*SAR b,CL*/ \
- temp = (int8_t)temp >> c; \
- seteab(temp); if (cpu_state.abrt) return 1; \
- set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- } \
- }
-
-#define OP_SHIFT_w(c, ea32) \
- { \
- uint16_t temp_orig = temp; \
- if (!c) return 0; \
- flags_rebuild(); \
- switch (rmdat & 0x38) \
- { \
- case 0x00: /*ROL w, c*/ \
- temp = (temp << (c & 15)) | (temp >> (16-(c & 15))); \
- seteaw(temp); if (cpu_state.abrt) return 1; \
- set_flags_rotate(FLAGS_ROL16, temp); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x08: /*ROR w,CL*/ \
- temp = (temp >> (c & 15)) | (temp << (16-(c & 15))); \
- seteaw(temp); if (cpu_state.abrt) return 1; \
- set_flags_rotate(FLAGS_ROR16, temp); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x10: /*RCL w, c*/ \
- temp2 = cpu_state.flags & C_FLAG; \
- if (is486) CLOCK_CYCLES_ALWAYS(c); \
- while (c > 0) \
- { \
- tempc = temp2 ? 1 : 0; \
- temp2 = temp & 0x8000; \
- temp = (temp << 1) | tempc; \
- c--; \
- } \
- seteaw(temp); if (cpu_state.abrt) return 1; \
- cpu_state.flags &= ~(C_FLAG | V_FLAG); \
- if (temp2) cpu_state.flags |= C_FLAG; \
- if ((cpu_state.flags & C_FLAG) ^ (temp >> 15)) cpu_state.flags |= V_FLAG; \
- CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
- PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x18: /*RCR w, c*/ \
- temp2 = cpu_state.flags & C_FLAG; \
- if (is486) CLOCK_CYCLES_ALWAYS(c); \
- while (c > 0) \
- { \
- tempc = temp2 ? 0x8000 : 0; \
- temp2 = temp & 1; \
- temp = (temp >> 1) | tempc; \
- c--; \
- } \
- seteaw(temp); if (cpu_state.abrt) return 1; \
- cpu_state.flags &= ~(C_FLAG | V_FLAG); \
- if (temp2) cpu_state.flags |= C_FLAG; \
- if ((temp ^ (temp >> 1)) & 0x4000) cpu_state.flags |= V_FLAG; \
- CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
- PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x20: case 0x30: /*SHL w, c*/ \
- seteaw(temp << c); if (cpu_state.abrt) return 1; \
- set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x28: /*SHR w, c*/ \
- seteaw(temp >> c); if (cpu_state.abrt) return 1; \
- set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x38: /*SAR w, c*/ \
- temp = (int16_t)temp >> c; \
- seteaw(temp); if (cpu_state.abrt) return 1; \
- set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- } \
- }
-
-#define OP_SHIFT_l(c, ea32) \
- { \
- uint32_t temp_orig = temp; \
- if (!c) return 0; \
- flags_rebuild(); \
- switch (rmdat & 0x38) \
- { \
- case 0x00: /*ROL l, c*/ \
- temp = (temp << c) | (temp >> (32-c)); \
- seteal(temp); if (cpu_state.abrt) return 1; \
- set_flags_rotate(FLAGS_ROL32, temp); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x08: /*ROR l,CL*/ \
- temp = (temp >> c) | (temp << (32-c)); \
- seteal(temp); if (cpu_state.abrt) return 1; \
- set_flags_rotate(FLAGS_ROR32, temp); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
- break; \
- case 0x10: /*RCL l, c*/ \
- temp2 = CF_SET(); \
- if (is486) CLOCK_CYCLES_ALWAYS(c); \
- while (c > 0) \
- { \
- tempc = temp2 ? 1 : 0; \
- temp2 = temp & 0x80000000; \
- temp = (temp << 1) | tempc; \
- c--; \
- } \
- seteal(temp); if (cpu_state.abrt) return 1; \
- cpu_state.flags &= ~(C_FLAG | V_FLAG); \
- if (temp2) cpu_state.flags |= C_FLAG; \
- if ((cpu_state.flags & C_FLAG) ^ (temp >> 31)) cpu_state.flags |= V_FLAG; \
- CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
- PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
- break; \
- case 0x18: /*RCR l, c*/ \
- temp2 = cpu_state.flags & C_FLAG; \
- if (is486) CLOCK_CYCLES_ALWAYS(c); \
- while (c > 0) \
- { \
- tempc = temp2 ? 0x80000000 : 0; \
- temp2 = temp & 1; \
- temp = (temp >> 1) | tempc; \
- c--; \
- } \
- seteal(temp); if (cpu_state.abrt) return 1; \
- cpu_state.flags &= ~(C_FLAG | V_FLAG); \
- if (temp2) cpu_state.flags |= C_FLAG; \
- if ((temp ^ (temp >> 1)) & 0x40000000) cpu_state.flags |= V_FLAG; \
- CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
- PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
- break; \
- case 0x20: case 0x30: /*SHL l, c*/ \
- seteal(temp << c); if (cpu_state.abrt) return 1; \
- set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
- break; \
- case 0x28: /*SHR l, c*/ \
- seteal(temp >> c); if (cpu_state.abrt) return 1; \
- set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
- break; \
- case 0x38: /*SAR l, c*/ \
- temp = (int32_t)temp >> c; \
- seteal(temp); if (cpu_state.abrt) return 1; \
- set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
- CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
- PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
- break; \
- } \
- }
-
-static int opC0_a16(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint8_t temp, temp2 = 0;
-
- fetch_ea_16(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
- PREFETCH_PREFIX();
- temp = geteab(); if (cpu_state.abrt) return 1;
- OP_SHIFT_b(c, 0);
- return 0;
-}
-static int opC0_a32(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint8_t temp, temp2 = 0;
-
- fetch_ea_32(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
- PREFETCH_PREFIX();
- temp = geteab(); if (cpu_state.abrt) return 1;
- OP_SHIFT_b(c, 1);
- return 0;
-}
-static int opC1_w_a16(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint16_t temp, temp2 = 0;
-
- fetch_ea_16(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
- PREFETCH_PREFIX();
- temp = geteaw(); if (cpu_state.abrt) return 1;
- OP_SHIFT_w(c, 0);
- return 0;
-}
-static int opC1_w_a32(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint16_t temp, temp2 = 0;
-
- fetch_ea_32(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
- PREFETCH_PREFIX();
- temp = geteaw(); if (cpu_state.abrt) return 1;
- OP_SHIFT_w(c, 1);
- return 0;
-}
-static int opC1_l_a16(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint32_t temp, temp2 = 0;
-
- fetch_ea_16(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
- PREFETCH_PREFIX();
- temp = geteal(); if (cpu_state.abrt) return 1;
- OP_SHIFT_l(c, 0);
- return 0;
-}
-static int opC1_l_a32(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint32_t temp, temp2 = 0;
-
- fetch_ea_32(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = readmemb(cs, cpu_state.pc) & 31; cpu_state.pc++;
- PREFETCH_PREFIX();
- temp = geteal(); if (cpu_state.abrt) return 1;
- OP_SHIFT_l(c, 1);
- return 0;
-}
-
-static int opD0_a16(uint32_t fetchdat)
-{
- int c = 1;
- int tempc;
- uint8_t temp, temp2 = 0;
-
- fetch_ea_16(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- temp = geteab(); if (cpu_state.abrt) return 1;
- OP_SHIFT_b(c, 0);
- return 0;
-}
-static int opD0_a32(uint32_t fetchdat)
-{
- int c = 1;
- int tempc;
- uint8_t temp, temp2 = 0;
-
- fetch_ea_32(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- temp = geteab(); if (cpu_state.abrt) return 1;
- OP_SHIFT_b(c, 1);
- return 0;
-}
-static int opD1_w_a16(uint32_t fetchdat)
-{
- int c = 1;
- int tempc;
- uint16_t temp, temp2 = 0;
-
- fetch_ea_16(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- temp = geteaw(); if (cpu_state.abrt) return 1;
- OP_SHIFT_w(c, 0);
- return 0;
-}
-static int opD1_w_a32(uint32_t fetchdat)
-{
- int c = 1;
- int tempc;
- uint16_t temp, temp2 = 0;
-
- fetch_ea_32(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- temp = geteaw(); if (cpu_state.abrt) return 1;
- OP_SHIFT_w(c, 1);
- return 0;
-}
-static int opD1_l_a16(uint32_t fetchdat)
-{
- int c = 1;
- int tempc;
- uint32_t temp, temp2 = 0;
-
- fetch_ea_16(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- temp = geteal(); if (cpu_state.abrt) return 1;
- OP_SHIFT_l(c, 0);
- return 0;
-}
-static int opD1_l_a32(uint32_t fetchdat)
-{
- int c = 1;
- int tempc;
- uint32_t temp, temp2 = 0;
-
- fetch_ea_32(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- temp = geteal(); if (cpu_state.abrt) return 1;
- OP_SHIFT_l(c, 1);
- return 0;
-}
-
-static int opD2_a16(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint8_t temp, temp2 = 0;
-
- fetch_ea_16(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = CL & 31;
- temp = geteab(); if (cpu_state.abrt) return 1;
- OP_SHIFT_b(c, 0);
- return 0;
-}
-static int opD2_a32(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint8_t temp, temp2 = 0;
-
- fetch_ea_32(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = CL & 31;
- temp = geteab(); if (cpu_state.abrt) return 1;
- OP_SHIFT_b(c, 1);
- return 0;
-}
-static int opD3_w_a16(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint16_t temp, temp2 = 0;
-
- fetch_ea_16(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = CL & 31;
- temp = geteaw(); if (cpu_state.abrt) return 1;
- OP_SHIFT_w(c, 0);
- return 0;
-}
-static int opD3_w_a32(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint16_t temp, temp2 = 0;
-
- fetch_ea_32(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = CL & 31;
- temp = geteaw(); if (cpu_state.abrt) return 1;
- OP_SHIFT_w(c, 1);
- return 0;
-}
-static int opD3_l_a16(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint32_t temp, temp2 = 0;
-
- fetch_ea_16(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = CL & 31;
- temp = geteal(); if (cpu_state.abrt) return 1;
- OP_SHIFT_l(c, 0);
- return 0;
-}
-static int opD3_l_a32(uint32_t fetchdat)
-{
- int c;
- int tempc;
- uint32_t temp, temp2 = 0;
-
- fetch_ea_32(fetchdat);
- if (cpu_mod != 3)
- SEG_CHECK_WRITE(cpu_state.ea_seg);
- c = CL & 31;
- temp = geteal(); if (cpu_state.abrt) return 1;
- OP_SHIFT_l(c, 1);
- return 0;
-}
-
-
-#define SHLD_w() \
- if (count) \
- { \
- int tempc; \
- uint32_t templ; \
- uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
- tempc = ((tempw << (count - 1)) & (1 << 15)) ? 1 : 0; \
- templ = (tempw << 16) | cpu_state.regs[cpu_reg].w; \
- if (count <= 16) tempw = templ >> (16 - count); \
- else tempw = (templ << count) >> 16; \
- seteaw(tempw); if (cpu_state.abrt) return 1; \
- setznp16(tempw); \
- flags_rebuild(); \
- if (tempc) cpu_state.flags |= C_FLAG; \
- }
-
-#define SHLD_l() \
- if (count) \
- { \
- int tempc; \
- uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
- tempc = ((templ << (count - 1)) & (1 << 31)) ? 1 : 0; \
- templ = (templ << count) | (cpu_state.regs[cpu_reg].l >> (32 - count)); \
- seteal(templ); if (cpu_state.abrt) return 1; \
- setznp32(templ); \
- flags_rebuild(); \
- if (tempc) cpu_state.flags |= C_FLAG; \
- }
-
-
-#define SHRD_w() \
- if (count) \
- { \
- int tempc; \
- uint32_t templ; \
- uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
- tempc = (tempw >> (count - 1)) & 1; \
- templ = tempw | (cpu_state.regs[cpu_reg].w << 16); \
- tempw = templ >> count; \
- seteaw(tempw); if (cpu_state.abrt) return 1; \
- setznp16(tempw); \
- flags_rebuild(); \
- if (tempc) cpu_state.flags |= C_FLAG; \
- }
-
-#define SHRD_l() \
- if (count) \
- { \
- int tempc; \
- uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
- tempc = (templ >> (count - 1)) & 1; \
- templ = (templ >> count) | (cpu_state.regs[cpu_reg].l << (32 - count)); \
- seteal(templ); if (cpu_state.abrt) return 1; \
- setznp32(templ); \
- flags_rebuild(); \
- if (tempc) cpu_state.flags |= C_FLAG; \
- }
-
-#define opSHxD(operation) \
- static int op ## operation ## _i_a16(uint32_t fetchdat) \
- { \
- int count; \
- \
- fetch_ea_16(fetchdat); \
- if (cpu_mod != 3) \
- SEG_CHECK_WRITE(cpu_state.ea_seg); \
- count = getbyte() & 31; \
- operation(); \
- \
- CLOCK_CYCLES(3); \
- PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
- return 0; \
- } \
- static int op ## operation ## _CL_a16(uint32_t fetchdat) \
- { \
- int count; \
- \
- fetch_ea_16(fetchdat); \
- if (cpu_mod != 3) \
- SEG_CHECK_WRITE(cpu_state.ea_seg); \
- count = CL & 31; \
- operation(); \
- \
- CLOCK_CYCLES(3); \
- PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
- return 0; \
- } \
- static int op ## operation ## _i_a32(uint32_t fetchdat) \
- { \
- int count; \
- \
- fetch_ea_32(fetchdat); \
- if (cpu_mod != 3) \
- SEG_CHECK_WRITE(cpu_state.ea_seg); \
- count = getbyte() & 31; \
- operation(); \
- \
- CLOCK_CYCLES(3); \
- PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
- return 0; \
- } \
- static int op ## operation ## _CL_a32(uint32_t fetchdat) \
- { \
- int count; \
- \
- fetch_ea_32(fetchdat); \
- if (cpu_mod != 3) \
- SEG_CHECK_WRITE(cpu_state.ea_seg); \
- count = CL & 31; \
- operation(); \
- \
- CLOCK_CYCLES(3); \
- PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
- return 0; \
- }
-
-opSHxD(SHLD_w)
-opSHxD(SHLD_l)
-opSHxD(SHRD_w)
-opSHxD(SHRD_l)
diff --git a/src/codegen_new/x86seg.c b/src/codegen_new/x86seg.c
deleted file mode 100644
index 29d1bfc97..000000000
--- a/src/codegen_new/x86seg.c
+++ /dev/null
@@ -1,2600 +0,0 @@
-/*
- * 86Box A hypervisor and IBM PC system emulator that specializes in
- * running old operating systems and software designed for IBM
- * PC systems and compatibles from 1981 through fairly recent
- * system designs based on the PCI bus.
- *
- * This file is part of the 86Box distribution.
- *
- * x86 CPU segment emulation.
- *
- *
- *
- * Authors: Sarah Walker,
- * Miran Grca,
- *
- * Copyright 2008-2018 Sarah Walker.
- * Copyright 2016-2018 Miran Grca.
- */
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#define HAVE_STDARG_H
-#include <86box/86box.h>
-#include "cpu.h"
-#include <86box/device.h>
-#include <86box/timer.h>
-#include <86box/machine.h>
-#include <86box/mem.h>
-#include <86box/nvr.h>
-#include "x86.h"
-#include "x86_flags.h"
-#include "386_common.h"
-
-
-extern FILE *stdlog; /* file to log output to */
-
-
-/*Controls whether the accessed bit in a descriptor is set when CS is loaded.*/
-#define CS_ACCESSED
-
-/*Controls whether the accessed bit in a descriptor is set when a data or stack
- selector is loaded.*/
-#define SEL_ACCESSED
-int stimes = 0;
-int dtimes = 0;
-int btimes = 0;
-
-uint32_t abrt_error;
-int cgate16, cgate32;
-
-#define breaknullsegs 0
-
-int intgatesize;
-
-void taskswitch286(uint16_t seg, uint16_t *segdat, int is32);
-void taskswitch386(uint16_t seg, uint16_t *segdat);
-
-void pmodeint(int num, int soft);
-/*NOT PRESENT is INT 0B
- GPF is INT 0D*/
-
-
-#ifdef ENABLE_X86SEG_LOG
-int x86seg_do_log = ENABLE_X86SEG_LOG;
-
-
-static void
-x86seg_log(const char *fmt, ...)
-{
- va_list ap;
-
- if (x86seg_do_log) {
- va_start(ap, fmt);
- pclog_ex(fmt, ap);
- va_end(ap);
- }
-}
-#else
-#define x86seg_log(fmt, ...)
-#endif
-
-
-void x86abort(const char *fmt, ...)
-{
- va_list ap;
-
- va_start(ap, fmt);
- pclog_ex(fmt, ap);
- va_end(ap);
-
- nvr_save();
-#ifdef ENABLE_808X_LOG
- dumpregs(1);
-#endif
- fflush(stdlog);
- exit(-1);
-}
-
-uint8_t opcode2;
-
-static void seg_reset(x86seg *s)
-{
- s->access = (0 << 5) | 2 | 0x80;
- s->ar_high = 0x10;
- s->limit = 0xFFFF;
- s->limit_low = 0;
- s->limit_high = 0xffff;
- if (s == &cpu_state.seg_cs)
- {
- /* TODO - When the PC is reset, initialization of the CS descriptor must be like the annotated line below:
- s->base = AT ? (cpu_16bitbus ? 0xFF0000 : 0xFFFF0000) : 0xFFFF0; */
- s->base = AT ? 0xF0000 : 0xFFFF0;
- s->seg = AT ? 0xF000 : 0xFFFF;
- }
- else
- {
- s->base = 0;
- s->seg = 0;
- }
-}
-
-void x86seg_reset()
-{
- seg_reset(&cpu_state.seg_cs);
- seg_reset(&cpu_state.seg_ds);
- seg_reset(&cpu_state.seg_es);
- seg_reset(&cpu_state.seg_fs);
- seg_reset(&cpu_state.seg_gs);
- seg_reset(&cpu_state.seg_ss);
-}
-
-void x86_doabrt(int x86_abrt)
-{
- cpu_state.pc = cpu_state.oldpc;
- cpu_state.seg_cs.access = (oldcpl << 5) | 0x80;
-
- if (msw & 1)
- pmodeint(x86_abrt, 0);
- else
- {
- uint32_t addr = (x86_abrt << 2) + idt.base;
- if (stack32)
- {
- writememw(ss,ESP-2,cpu_state.flags);
- writememw(ss,ESP-4,CS);
- writememw(ss,ESP-6,cpu_state.pc);
- ESP-=6;
- }
- else
- {
- writememw(ss,((SP-2)&0xFFFF),cpu_state.flags);
- writememw(ss,((SP-4)&0xFFFF),CS);
- writememw(ss,((SP-6)&0xFFFF),cpu_state.pc);
- SP-=6;
- }
-
- cpu_state.flags &= ~I_FLAG;
- cpu_state.flags &= ~T_FLAG;
- cpu_state.pc=readmemw(0,addr);
- loadcs(readmemw(0,addr+2));
- return;
- }
-
- if (cpu_state.abrt || x86_was_reset) return;
-
- if (intgatesize == 16)
- {
- if (stack32)
- {
- writememw(ss, ESP-2, abrt_error);
- ESP-=2;
- }
- else
- {
- writememw(ss, ((SP-2)&0xFFFF), abrt_error);
- SP-=2;
- }
- }
- else
- {
- if (stack32)
- {
- writememl(ss, ESP-4, abrt_error);
- ESP-=4;
- }
- else
- {
- writememl(ss, ((SP-4)&0xFFFF), abrt_error);
- SP-=4;
- }
- }
-}
-void x86gpf(char *s, uint16_t error)
-{
- cpu_state.abrt = ABRT_GPF;
- abrt_error = error;
-}
-void x86ss(char *s, uint16_t error)
-{
- cpu_state.abrt = ABRT_SS;
- abrt_error = error;
-}
-void x86ts(char *s, uint16_t error)
-{
- cpu_state.abrt = ABRT_TS;
- abrt_error = error;
-}
-void x86np(char *s, uint16_t error)
-{
- cpu_state.abrt = ABRT_NP;
- abrt_error = error;
-}
-
-
-static void set_stack32(int s)
-{
- stack32 = s;
- if (stack32)
- cpu_cur_status |= CPU_STATUS_STACK32;
- else
- cpu_cur_status &= ~CPU_STATUS_STACK32;
-}
-
-static void set_use32(int u)
-{
- if (u)
- {
- use32 = 0x300;
- cpu_cur_status |= CPU_STATUS_USE32;
- }
- else
- {
- use32 = 0;
- cpu_cur_status &= ~CPU_STATUS_USE32;
- }
-}
-
-void do_seg_load(x86seg *s, uint16_t *segdat)
-{
- s->limit = segdat[0] | ((segdat[3] & 0xF) << 16);
- if (segdat[3] & 0x80)
- s->limit = (s->limit << 12) | 0xFFF;
- s->base = segdat[1] | ((segdat[2] & 0xFF) << 16);
- if (is386)
- s->base |= ((segdat[3] >> 8) << 24);
- s->access = segdat[2] >> 8;
- s->ar_high = segdat[3] & 0xff;
-
- if ((segdat[2] & 0x1800) != 0x1000 || !(segdat[2] & (1 << 10))) /*expand-down*/
- {
- s->limit_high = s->limit;
- s->limit_low = 0;
- }
- else
- {
- s->limit_high = (segdat[3] & 0x40) ? 0xffffffff : 0xffff;
- s->limit_low = s->limit + 1;
- }
-
- if (s == &cpu_state.seg_ds)
- {
- if (s->base == 0 && s->limit_low == 0 && s->limit_high == 0xffffffff)
- cpu_cur_status &= ~CPU_STATUS_NOTFLATDS;
- else
- cpu_cur_status |= CPU_STATUS_NOTFLATDS;
- }
- if (s == &cpu_state.seg_ss)
- {
- if (s->base == 0 && s->limit_low == 0 && s->limit_high == 0xffffffff)
- cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
- else
- cpu_cur_status |= CPU_STATUS_NOTFLATSS;
- }
-}
-
-static void do_seg_v86_init(x86seg *s)
-{
- s->access = (3 << 5) | 2 | 0x80;
- s->ar_high = 0x10;
- s->limit = 0xffff;
- s->limit_low = 0;
- s->limit_high = 0xffff;
-}
-
-static void check_seg_valid(x86seg *s)
-{
- int dpl = (s->access >> 5) & 3;
- int valid = 1;
-
- if (s->seg & 4)
- {
- if ((s->seg & ~7) >= ldt.limit)
- {
- valid = 0;
- }
- }
- else
- {
- if ((s->seg & ~7) >= gdt.limit)
- {
- valid = 0;
- }
- }
-
- switch (s->access & 0x1f)
- {
- case 0x10: case 0x11: case 0x12: case 0x13: /*Data segments*/
- case 0x14: case 0x15: case 0x16: case 0x17:
- case 0x1A: case 0x1B: /*Readable non-conforming code*/
- if ((s->seg & 3) > dpl || (CPL) > dpl)
- {
- valid = 0;
- break;
- }
- break;
-
- case 0x1E: case 0x1F: /*Readable conforming code*/
- break;
-
- default:
- valid = 0;
- break;
- }
-
- if (!valid)
- loadseg(0, s);
-}
-
-int loadseg(uint16_t seg, x86seg *s)
-{
- uint16_t segdat[4];
- uint32_t addr;
- int dpl;
-
- if (msw&1 && !(cpu_state.eflags&VM_FLAG))
- {
- if (!(seg&~3))
- {
- if (s==&cpu_state.seg_ss)
- {
- x86ss(NULL,0);
- return 1;
- }
- s->seg=0;
- s->access = 0x80;
- s->ar_high = 0x10;
- s->base=-1;
- if (s == &cpu_state.seg_ds)
- cpu_cur_status |= CPU_STATUS_NOTFLATDS;
- return 0;
- }
- addr=seg&~7;
- if (seg&4)
- {
- if ((addr+7)>ldt.limit)
- {
- x86gpf("loadseg(): Bigger than LDT limit",seg&~3);
- return 1;
- }
- addr+=ldt.base;
- }
- else
- {
- if ((addr+7)>gdt.limit)
- {
- x86gpf("loadseg(): Bigger than GDT limit",seg&~3);
- return 1;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(0,addr+2);
- segdat[2]=readmemw(0,addr+4);
- segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return 1;
- dpl=(segdat[2]>>13)&3;
- if (s==&cpu_state.seg_ss)
- {
- if (!(seg&~3))
- {
- x86gpf("loadseg(): Zero stack segment",seg&~3);
- return 1;
- }
- if ((seg&3)!=CPL)
- {
- x86gpf("loadseg(): Stack segment RPL != CPL",seg&~3);
- return 1;
- }
- if (dpl!=CPL)
- {
- x86gpf("loadseg(): Stack segment DPL != CPL",seg&~3);
- return 1;
- }
- switch ((segdat[2]>>8)&0x1F)
- {
- case 0x12: case 0x13: case 0x16: case 0x17: /*r/w*/
- break;
- default:
- x86gpf("loadseg(): Unknown stack segment type",seg&~3);
- return 1;
- }
- if (!(segdat[2]&0x8000))
- {
- x86ss(NULL,seg&~3);
- return 1;
- }
- set_stack32((segdat[3] & 0x40) ? 1 : 0);
- }
- else if (s!=&cpu_state.seg_cs)
- {
- x86seg_log("Seg data %04X %04X %04X %04X\n", segdat[0], segdat[1], segdat[2], segdat[3]);
- x86seg_log("Seg type %03X\n",segdat[2]&0x1F00);
- switch ((segdat[2]>>8)&0x1F)
- {
- case 0x10: case 0x11: case 0x12: case 0x13: /*Data segments*/
- case 0x14: case 0x15: case 0x16: case 0x17:
- case 0x1A: case 0x1B: /*Readable non-conforming code*/
- if ((seg&3)>dpl)
- {
- x86gpf("loadseg(): Normal segment RPL > DPL",seg&~3);
- return 1;
- }
- if ((CPL)>dpl)
- {
- x86gpf("loadseg(): Normal segment DPL < CPL",seg&~3);
- return 1;
- }
- break;
- case 0x1E: case 0x1F: /*Readable conforming code*/
- break;
- default:
- x86gpf("loadseg(): Unknown normal segment type",seg&~3);
- return 1;
- }
- }
-
- if (!(segdat[2] & 0x8000))
- {
- x86np("Load data seg not present", seg & 0xfffc);
- return 1;
- }
- s->seg = seg;
- do_seg_load(s, segdat);
-
-#ifndef CS_ACCESSED
- if (s != &_cs)
- {
-#endif
-#ifdef SEL_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
-#ifndef CS_ACCESSED
- }
-#endif
- s->checked = 0;
-#ifdef USE_DYNAREC
- if (s == &cpu_state.seg_ds)
- codegen_flat_ds = 0;
- if (s == &cpu_state.seg_ss)
- codegen_flat_ss = 0;
-#endif
- }
- else
- {
- s->access = (3 << 5) | 2 | 0x80;
- s->ar_high = 0x10;
- s->base = seg << 4;
- s->seg = seg;
- s->checked = 1;
-#ifdef USE_DYNAREC
- if (s == &cpu_state.seg_ds)
- codegen_flat_ds = 0;
- if (s == &cpu_state.seg_ss)
- codegen_flat_ss = 0;
-#endif
- if (s == &cpu_state.seg_ss && (cpu_state.eflags & VM_FLAG))
- set_stack32(0);
- }
-
- if (s == &cpu_state.seg_ds)
- {
- if (s->base == 0 && s->limit_low == 0 && s->limit_high == 0xffffffff)
- cpu_cur_status &= ~CPU_STATUS_NOTFLATDS;
- else
- cpu_cur_status |= CPU_STATUS_NOTFLATDS;
- }
- if (s == &cpu_state.seg_ss)
- {
- if (s->base == 0 && s->limit_low == 0 && s->limit_high == 0xffffffff)
- cpu_cur_status &= ~CPU_STATUS_NOTFLATSS;
- else
- cpu_cur_status |= CPU_STATUS_NOTFLATSS;
- }
-
- return cpu_state.abrt;
-}
-
-#define DPL ((segdat[2]>>13)&3)
-#define DPL2 ((segdat2[2]>>13)&3)
-#define DPL3 ((segdat3[2]>>13)&3)
-
-void loadcs(uint16_t seg)
-{
- uint16_t segdat[4];
- uint32_t addr;
- x86seg_log("Load CS %04X\n",seg);
- if (msw&1 && !(cpu_state.eflags&VM_FLAG))
- {
- if (!(seg&~3))
- {
- x86gpf(NULL,0);
- return;
- }
- addr=seg&~7;
- if (seg&4)
- {
- if (addr>=ldt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(0,addr+2);
- segdat[2]=readmemw(0,addr+4);
- segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
- if (segdat[2]&0x1000) /*Normal code segment*/
- {
- if (!(segdat[2]&0x400)) /*Not conforming*/
- {
- if ((seg&3)>CPL)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- if (CPL != DPL)
- {
- x86gpf("loadcs(): CPL != DPL",seg&~3);
- return;
- }
- }
- if (CPL < DPL)
- {
- x86gpf("loadcs(): CPL < DPL",seg&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- x86np("Load CS not present", seg & 0xfffc);
- return;
- }
- set_use32(segdat[3] & 0x40);
- CS=(seg&~3)|CPL;
- do_seg_load(&cpu_state.seg_cs, segdat);
- use32=(segdat[3]&0x40)?0x300:0;
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
- }
- else /*System segment*/
- {
- if (!(segdat[2]&0x8000))
- {
- x86np("Load CS system seg not present\n", seg & 0xfffc);
- return;
- }
- switch (segdat[2]&0xF00)
- {
- default:
- x86gpf(NULL,seg&~3);
- return;
- }
- }
- }
- else
- {
- cpu_state.seg_cs.base=seg<<4;
- cpu_state.seg_cs.limit=0xFFFF;
- cpu_state.seg_cs.limit_low = 0;
- cpu_state.seg_cs.limit_high = 0xffff;
- CS=seg & 0xFFFF;
- if (cpu_state.eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2 | 0x80;
- else cpu_state.seg_cs.access=(0<<5) | 2 | 0x80;
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- }
-}
-
-void loadcsjmp(uint16_t seg, uint32_t old_pc)
-{
- uint16_t segdat[4];
- uint32_t addr;
- uint16_t type,seg2;
- uint32_t newpc;
- if (msw&1 && !(cpu_state.eflags&VM_FLAG))
- {
- if (!(seg&~3))
- {
- x86gpf(NULL,0);
- return;
- }
- addr=seg&~7;
- if (seg&4)
- {
- if (addr>=ldt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(0,addr+2);
- segdat[2]=readmemw(0,addr+4);
- segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
- x86seg_log("%04X %04X %04X %04X\n",segdat[0],segdat[1],segdat[2],segdat[3]);
- if (segdat[2]&0x1000) /*Normal code segment*/
- {
- if (!(segdat[2]&0x400)) /*Not conforming*/
- {
- if ((seg&3)>CPL)
- {
- x86gpf("loadcsjmp(): segment PL > CPL",seg&~3);
- return;
- }
- if (CPL != DPL)
- {
- x86gpf("loadcsjmp(): CPL != DPL",seg&~3);
- return;
- }
- }
- if (CPL < DPL)
- {
- x86gpf("loadcsjmp(): CPL < DPL",seg&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- x86np("Load CS JMP not present\n", seg & 0xfffc);
- return;
- }
- set_use32(segdat[3]&0x40);
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
-
- CS = (seg & ~3) | CPL;
- segdat[2] = (segdat[2] & ~(3 << (5+8))) | (CPL << (5+8));
-
- do_seg_load(&cpu_state.seg_cs, segdat);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- cycles -= timing_jmp_pm;
- }
- else /*System segment*/
- {
- if (!(segdat[2]&0x8000))
- {
- x86np("Load CS JMP system selector not present\n", seg & 0xfffc);
- return;
- }
- type=segdat[2]&0xF00;
- newpc=segdat[0];
- if (type&0x800) newpc|=segdat[3]<<16;
- switch (type)
- {
- case 0x400: /*Call gate*/
- case 0xC00:
- cgate32=(type&0x800);
- cgate16=!cgate32;
- cpu_state.oldpc = cpu_state.pc;
- if ((DPL < CPL) || (DPL < (seg&3)))
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- if (DPL < CPL)
- {
- x86gpf("loadcsjmp(): ex DPL < CPL",seg&~3);
- return;
- }
- if ((DPL < (seg&3)))
- {
- x86gpf("loadcsjmp(): ex (DPL < (seg&3))",seg&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- x86np("Load CS JMP call gate not present\n", seg & 0xfffc);
- return;
- }
- seg2=segdat[1];
-
- if (!(seg2&~3))
- {
- x86gpf(NULL,0);
- return;
- }
- addr=seg2&~7;
- if (seg2&4)
- {
- if (addr>=ldt.limit)
- {
- x86gpf(NULL,seg2&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86gpf(NULL,seg2&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(0,addr+2);
- segdat[2]=readmemw(0,addr+4);
- segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
-
- if (DPL > CPL)
- {
- x86gpf("loadcsjmp(): ex DPL > CPL",seg2&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- x86np("Load CS JMP from call gate not present\n", seg2 & 0xfffc);
- return;
- }
-
-
- switch (segdat[2]&0x1F00)
- {
- case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming code*/
- if (DPL > CPL)
- {
- x86gpf(NULL,seg2&~3);
- return;
- }
- /*FALLTHROUGH*/
- case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
- CS=seg2;
- do_seg_load(&cpu_state.seg_cs, segdat);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- set_use32(segdat[3]&0x40);
- cpu_state.pc=newpc;
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
- break;
-
- default:
- x86gpf(NULL,seg2&~3);
- return;
- }
- cycles -= timing_jmp_pm_gate;
- break;
-
-
- case 0x100: /*286 Task gate*/
- case 0x900: /*386 Task gate*/
- cpu_state.pc = old_pc;
- optype=JMP;
- cpl_override=1;
- taskswitch286(seg,segdat,segdat[2]&0x800);
- cpu_state.flags &= ~NT_FLAG;
- cpl_override=0;
- return;
-
- default:
- x86gpf(NULL,0);
- return;
- }
- }
- }
- else
- {
- cpu_state.seg_cs.base=seg<<4;
- cpu_state.seg_cs.limit=0xFFFF;
- cpu_state.seg_cs.limit_low = 0;
- cpu_state.seg_cs.limit_high = 0xffff;
- CS=seg;
- if (cpu_state.eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2 | 0x80;
- else cpu_state.seg_cs.access=(0<<5) | 2 | 0x80;
- cpu_state.seg_cs.ar_high = 0x10;
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- cycles -= timing_jmp_rm;
- }
-}
-
-void PUSHW(uint16_t v)
-{
- if (stack32)
- {
- writememw(ss,ESP-2,v);
- if (cpu_state.abrt) return;
- ESP-=2;
- }
- else
- {
- writememw(ss,((SP-2)&0xFFFF),v);
- if (cpu_state.abrt) return;
- SP-=2;
- }
-}
-void PUSHL(uint32_t v)
-{
- if (stack32)
- {
- writememl(ss,ESP-4,v);
- if (cpu_state.abrt) return;
- ESP-=4;
- }
- else
- {
- writememl(ss,((SP-4)&0xFFFF),v);
- if (cpu_state.abrt) return;
- SP-=4;
- }
-}
-uint16_t POPW()
-{
- uint16_t tempw;
- if (stack32)
- {
- tempw=readmemw(ss,ESP);
- if (cpu_state.abrt) return 0;
- ESP+=2;
- }
- else
- {
- tempw=readmemw(ss,SP);
- if (cpu_state.abrt) return 0;
- SP+=2;
- }
- return tempw;
-}
-uint32_t POPL()
-{
- uint32_t templ;
- if (stack32)
- {
- templ=readmeml(ss,ESP);
- if (cpu_state.abrt) return 0;
- ESP+=4;
- }
- else
- {
- templ=readmeml(ss,SP);
- if (cpu_state.abrt) return 0;
- SP+=4;
- }
- return templ;
-}
-
-void loadcscall(uint16_t seg, uint32_t old_pc)
-{
- uint16_t seg2;
- uint16_t segdat[4],segdat2[4],newss;
- uint32_t addr,oldssbase=ss, oaddr;
- uint32_t newpc;
- int count;
- uint32_t oldss,oldsp,newsp, oldsp2;
- int type;
- uint16_t tempw;
-
- if (msw&1 && !(cpu_state.eflags&VM_FLAG))
- {
- x86seg_log("Protected mode CS load! %04X\n", seg);
- if (!(seg&~3))
- {
- x86gpf(NULL,0);
- return;
- }
- addr=seg&~7;
- if (seg&4)
- {
- if (addr>=ldt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(0,addr+2);
- segdat[2]=readmemw(0,addr+4);
- segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
- type=segdat[2]&0xF00;
- newpc=segdat[0];
- if (type&0x800) newpc|=segdat[3]<<16;
-
- x86seg_log("Code seg call - %04X - %04X %04X %04X\n",seg,segdat[0],segdat[1],segdat[2]);
- if (segdat[2]&0x1000)
- {
- if (!(segdat[2]&0x400)) /*Not conforming*/
- {
- if ((seg&3)>CPL)
- {
- x86gpf("loadcscall(): segment > CPL",seg&~3);
- return;
- }
- if (CPL != DPL)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- }
- if (CPL < DPL)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- x86np("Load CS call not present", seg & 0xfffc);
- return;
- }
- set_use32(segdat[3]&0x40);
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
-
- /*Conforming segments don't change CPL, so preserve existing CPL*/
- if (segdat[2]&0x400)
- {
- seg = (seg & ~3) | CPL;
- segdat[2] = (segdat[2] & ~(3 << (5+8))) | (CPL << (5+8));
- }
- else /*On non-conforming segments, set RPL = CPL*/
- seg = (seg & ~3) | CPL;
- CS=seg;
- do_seg_load(&cpu_state.seg_cs, segdat);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
-#ifdef ENABLE_X86SEG_LOG
- x86seg_log("Complete\n");
-#endif
- cycles -= timing_call_pm;
- }
- else
- {
- type=segdat[2]&0xF00;
- x86seg_log("Type %03X\n",type);
- switch (type)
- {
- case 0x400: /*Call gate*/
- case 0xC00: /*386 Call gate*/
- x86seg_log("Callgate %08X\n", cpu_state.pc);
- cgate32=(type&0x800);
- cgate16=!cgate32;
- count=segdat[2]&31;
- if (DPL < CPL)
- {
- x86gpf("loadcscall(): ex DPL < CPL",seg&~3);
- return;
- }
- if ((DPL < (seg&3)))
- {
- x86gpf("loadcscall(): ex (DPL < (seg&3))",seg&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- x86seg_log("Call gate not present %04X\n",seg);
- x86np("Call gate not present\n", seg & 0xfffc);
- return;
- }
- seg2=segdat[1];
-
- x86seg_log("New address : %04X:%08X\n", seg2, newpc);
-
- if (!(seg2&~3))
- {
- x86gpf(NULL,0);
- return;
- }
- addr=seg2&~7;
- if (seg2&4)
- {
- if (addr>=ldt.limit)
- {
- x86gpf(NULL,seg2&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86gpf(NULL,seg2&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(0,addr+2);
- segdat[2]=readmemw(0,addr+4);
- segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
-
- x86seg_log("Code seg2 call - %04X - %04X %04X %04X\n",seg2,segdat[0],segdat[1],segdat[2]);
-
- if (DPL > CPL)
- {
- x86gpf("loadcscall(): ex DPL > CPL",seg2&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- x86seg_log("Call gate CS not present %04X\n",seg2);
- x86np("Call gate CS not present", seg2 & 0xfffc);
- return;
- }
-
-
- switch (segdat[2]&0x1F00)
- {
- case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming code*/
- if (DPL < CPL)
- {
- uint16_t oldcs = CS;
- oaddr = addr;
- /*Load new stack*/
- oldss=SS;
- oldsp=oldsp2=ESP;
- cpl_override=1;
- if (tr.access&8)
- {
- addr = 4 + tr.base + (DPL * 8);
- newss=readmemw(0,addr+4);
- newsp=readmeml(0,addr);
- }
- else
- {
- addr = 2 + tr.base + (DPL * 4);
- newss=readmemw(0,addr+2);
- newsp=readmemw(0,addr);
- }
- cpl_override=0;
- if (cpu_state.abrt) return;
- x86seg_log("New stack %04X:%08X\n",newss,newsp);
- if (!(newss&~3))
- {
- x86ts(NULL,newss&~3);
- return;
- }
- addr=newss&~7;
- if (newss&4)
- {
- if ((addr+7)>ldt.limit)
- {
- x86abort("Bigger than LDT limit %04X %08X %04X CSC SS\n",newss,addr,ldt.limit);
- x86ts(NULL,newss&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if ((addr+7)>gdt.limit)
- {
- x86abort("Bigger than GDT limit %04X %04X CSC\n",newss,gdt.limit);
- x86ts(NULL,newss&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- x86seg_log("Read stack seg\n");
- segdat2[0]=readmemw(0,addr);
- segdat2[1]=readmemw(0,addr+2);
- segdat2[2]=readmemw(0,addr+4);
- segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
- x86seg_log("Read stack seg done!\n");
- if (((newss & 3) != DPL) || (DPL2 != DPL))
- {
- x86ts(NULL,newss&~3);
- return;
- }
- if ((segdat2[2]&0x1A00)!=0x1200)
- {
- x86ts(NULL,newss&~3);
- return;
- }
- if (!(segdat2[2]&0x8000))
- {
- x86ss("Call gate loading SS not present\n", newss & 0xfffc);
- return;
- }
- if (!stack32) oldsp &= 0xFFFF;
- SS=newss;
- set_stack32((segdat2[3] & 0x40) ? 1 : 0);
- if (stack32) ESP=newsp;
- else SP=newsp;
-
- do_seg_load(&cpu_state.seg_ss, segdat2);
-
- x86seg_log("Set access 1\n");
-
-#ifdef SEL_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat2[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
-
- CS=seg2;
- do_seg_load(&cpu_state.seg_cs, segdat);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- set_use32(segdat[3]&0x40);
- cpu_state.pc=newpc;
-
- x86seg_log("Set access 2\n");
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, oaddr+4, segdat[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
-
- x86seg_log("Type %04X\n",type);
- if (type==0xC00)
- {
- PUSHL(oldss);
- PUSHL(oldsp2);
- if (cpu_state.abrt)
- {
- SS = oldss;
- ESP = oldsp2;
- CS = oldcs;
- return;
- }
- if (count)
- {
- while (count)
- {
- count--;
- PUSHL(readmeml(oldssbase,oldsp+(count*4)));
- if (cpu_state.abrt)
- {
- SS = oldss;
- ESP = oldsp2;
- CS = oldcs;
- return;
- }
- }
- }
- }
- else
- {
- x86seg_log("Stack %04X\n",SP);
- PUSHW(oldss);
- x86seg_log("Write SS to %04X:%04X\n",SS,SP);
- PUSHW(oldsp2);
- if (cpu_state.abrt)
- {
- SS = oldss;
- ESP = oldsp2;
- CS = oldcs;
- return;
- }
- x86seg_log("Write SP to %04X:%04X\n",SS,SP);
- if (count)
- {
- while (count)
- {
- count--;
- tempw=readmemw(oldssbase,(oldsp&0xFFFF)+(count*2));
- x86seg_log("PUSH %04X\n",tempw);
- PUSHW(tempw);
- if (cpu_state.abrt)
- {
- SS = oldss;
- ESP = oldsp2;
- CS = oldcs;
- return;
- }
- }
- }
- }
- cycles -= timing_call_pm_gate_inner;
- break;
- }
- else if (DPL > CPL)
- {
- x86gpf(NULL,seg2&~3);
- return;
- }
- /*FALLTHROUGH*/
- case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
- CS=seg2;
- do_seg_load(&cpu_state.seg_cs, segdat);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- set_use32(segdat[3]&0x40);
- cpu_state.pc=newpc;
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
- cycles -= timing_call_pm_gate;
- break;
-
- default:
- x86gpf(NULL,seg2&~3);
- return;
- }
- break;
-
- case 0x100: /*286 Task gate*/
- case 0x900: /*386 Task gate*/
- cpu_state.pc = old_pc;
- cpl_override=1;
- taskswitch286(seg,segdat,segdat[2]&0x800);
- cpl_override=0;
- break;
-
- default:
- x86gpf(NULL,seg&~3);
- return;
- }
- }
- }
- else
- {
- cpu_state.seg_cs.base=seg<<4;
- cpu_state.seg_cs.limit=0xFFFF;
- cpu_state.seg_cs.limit_low = 0;
- cpu_state.seg_cs.limit_high = 0xffff;
- CS=seg;
- if (cpu_state.eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2 | 0x80;
- else cpu_state.seg_cs.access=(0<<5) | 2 | 0x80;
- cpu_state.seg_cs.ar_high = 0x10;
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- }
-}
-
-void pmoderetf(int is32, uint16_t off)
-{
- uint32_t newpc;
- uint32_t newsp;
- uint32_t addr, oaddr;
- uint16_t segdat[4],segdat2[4],seg,newss;
- uint32_t oldsp=ESP;
- x86seg_log("RETF %i %04X:%04X %08X %04X\n",is32,CS,cpu_state.pc,cr0,cpu_state.eflags);
- if (is32)
- {
- newpc=POPL();
- seg=POPL(); if (cpu_state.abrt) return;
- }
- else
- {
- x86seg_log("PC read from %04X:%04X\n",SS,SP);
- newpc=POPW();
- x86seg_log("CS read from %04X:%04X\n",SS,SP);
- seg=POPW(); if (cpu_state.abrt) return;
- }
- x86seg_log("Return to %04X:%08X\n",seg,newpc);
- if ((seg&3)=ldt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(0,addr+2);
- segdat[2]=readmemw(0,addr+4);
- segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP=oldsp; return; }
- oaddr = addr;
-
- x86seg_log("CPL %i RPL %i %i\n",CPL,seg&3,is32);
-
- if (stack32) ESP+=off;
- else SP+=off;
-
- if (CPL==(seg&3))
- {
- x86seg_log("RETF CPL = RPL %04X\n", segdat[2]);
- switch (segdat[2]&0x1F00)
- {
- case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming*/
- if (CPL != DPL)
- {
- ESP=oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- break;
- case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
- if (CPL < DPL)
- {
- ESP=oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- break;
- default:
- x86gpf(NULL,seg&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- ESP=oldsp;
- x86np("RETF CS not present\n", seg & 0xfffc);
- return;
- }
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
-
- cpu_state.pc=newpc;
- if (segdat[2] & 0x400)
- segdat[2] = (segdat[2] & ~(3 << (5+8))) | ((seg & 3) << (5+8));
- CS = seg;
- do_seg_load(&cpu_state.seg_cs, segdat);
- cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~(3 << 5)) | ((CS & 3) << 5);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- set_use32(segdat[3] & 0x40);
-
- cycles -= timing_retf_pm;
- }
- else
- {
- switch (segdat[2]&0x1F00)
- {
- case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming*/
- if ((seg&3) != DPL)
- {
- ESP=oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- x86seg_log("RETF non-conforming, %i %i\n",seg&3, DPL);
- break;
- case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
- if ((seg&3) < DPL)
- {
- ESP=oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- x86seg_log("RETF conforming, %i %i\n",seg&3, DPL);
- break;
- default:
- ESP=oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- ESP=oldsp;
- x86np("RETF CS not present\n", seg & 0xfffc);
- return;
- }
- if (is32)
- {
- newsp=POPL();
- newss=POPL(); if (cpu_state.abrt) return;
- }
- else
- {
- x86seg_log("SP read from %04X:%04X\n",SS,SP);
- newsp=POPW();
- x86seg_log("SS read from %04X:%04X\n",SS,SP);
- newss=POPW(); if (cpu_state.abrt) return;
- }
- x86seg_log("Read new stack : %04X:%04X (%08X)\n", newss, newsp, ldt.base);
- if (!(newss&~3))
- {
- ESP=oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- addr=newss&~7;
- if (newss&4)
- {
- if (addr>=ldt.limit)
- {
- ESP=oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- ESP=oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat2[0]=readmemw(0,addr);
- segdat2[1]=readmemw(0,addr+2);
- segdat2[2]=readmemw(0,addr+4);
- segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP=oldsp; return; }
- x86seg_log("Segment data %04X %04X %04X %04X\n", segdat2[0], segdat2[1], segdat2[2], segdat2[3]);
- if ((newss & 3) != (seg & 3))
- {
- ESP=oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- if ((segdat2[2]&0x1A00)!=0x1200)
- {
- ESP=oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- if (!(segdat2[2]&0x8000))
- {
- ESP=oldsp;
- x86np("RETF loading SS not present\n", newss & 0xfffc);
- return;
- }
- if (DPL2 != (seg & 3))
- {
- ESP=oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- SS=newss;
- set_stack32((segdat2[3] & 0x40) ? 1 : 0);
- if (stack32) ESP=newsp;
- else SP=newsp;
- do_seg_load(&cpu_state.seg_ss, segdat2);
-
-#ifdef SEL_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat2[2] | 0x100); /*Set accessed bit*/
-
-#ifdef CS_ACCESSED
- writememw(0, oaddr+4, segdat[2] | 0x100); /*Set accessed bit*/
-#endif
- cpl_override = 0;
-#endif
- /*Conforming segments don't change CPL, so CPL = RPL*/
- if (segdat[2]&0x400)
- segdat[2] = (segdat[2] & ~(3 << (5+8))) | ((seg & 3) << (5+8));
-
- cpu_state.pc=newpc;
- CS=seg;
- do_seg_load(&cpu_state.seg_cs, segdat);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- set_use32(segdat[3] & 0x40);
-
- if (stack32) ESP+=off;
- else SP+=off;
-
- check_seg_valid(&cpu_state.seg_ds);
- check_seg_valid(&cpu_state.seg_es);
- check_seg_valid(&cpu_state.seg_fs);
- check_seg_valid(&cpu_state.seg_gs);
- cycles -= timing_retf_pm_outer;
- }
-}
-
-void pmodeint(int num, int soft)
-{
- uint16_t segdat[4],segdat2[4],segdat3[4];
- uint32_t addr, oaddr;
- uint16_t newss;
- uint32_t oldss,oldsp;
- int type;
- uint32_t newsp;
- uint16_t seg = 0;
- int new_cpl;
-
- if (cpu_state.eflags&VM_FLAG && IOPL!=3 && soft)
- {
- x86seg_log("V86 banned int\n");
- x86gpf(NULL,0);
- return;
- }
- addr=(num<<3);
- if (addr>=idt.limit)
- {
- if (num==8)
- {
- /*Triple fault - reset!*/
- softresetx86();
- cpu_set_edx();
- }
- else if (num==0xD)
- {
- pmodeint(8,0);
- }
- else
- {
- x86gpf(NULL,(num*8)+2+((soft)?0:1));
- }
- x86seg_log("addr >= IDT.limit\n");
- return;
- }
- addr+=idt.base;
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(2,addr);
- segdat[2]=readmemw(4,addr);
- segdat[3]=readmemw(6,addr); cpl_override=0;
- if (cpu_state.abrt) {
- x86seg_log("Abrt reading from %08X\n",addr);
- return;
- }
- oaddr = addr;
-
- x86seg_log("Addr %08X seg %04X %04X %04X %04X\n",addr,segdat[0],segdat[1],segdat[2],segdat[3]);
- if (!(segdat[2]&0x1F00))
- {
- x86gpf(NULL,(num*8)+2);
- return;
- }
- if (DPL=0x800)?32:16;
- if (!(segdat[2]&0x8000))
- {
- x86np("Int gate not present\n", (num << 3) | 2);
- return;
- }
- seg=segdat[1];
- new_cpl = seg & 3;
-
- addr=seg&~7;
- if (seg&4)
- {
- if (addr>=ldt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat2[0]=readmemw(0,addr);
- segdat2[1]=readmemw(0,addr+2);
- segdat2[2]=readmemw(0,addr+4);
- segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
- oaddr = addr;
-
- if (DPL2 > CPL)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- switch (segdat2[2]&0x1F00)
- {
- case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming*/
- if (DPL2=ldt.limit)
- {
- x86ss(NULL,newss&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86ss(NULL,newss&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat3[0]=readmemw(0,addr);
- segdat3[1]=readmemw(0,addr+2);
- segdat3[2]=readmemw(0,addr+4);
- segdat3[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
- if (((newss & 3) != DPL2) || (DPL3 != DPL2))
- {
- x86ss(NULL,newss&~3);
- return;
- }
- if ((segdat3[2]&0x1A00)!=0x1200)
- {
- x86ss(NULL,newss&~3);
- return;
- }
- if (!(segdat3[2]&0x8000))
- {
- x86np("Int gate loading SS not present\n", newss & 0xfffc);
- return;
- }
- SS=newss;
- set_stack32((segdat3[3] & 0x40) ? 1 : 0);
- if (stack32) ESP=newsp;
- else SP=newsp;
- do_seg_load(&cpu_state.seg_ss, segdat3);
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat3[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
-
- x86seg_log("New stack %04X:%08X\n",SS,ESP);
- cpl_override=1;
- if (type>=0x800)
- {
- if (cpu_state.eflags & VM_FLAG)
- {
- PUSHL(GS);
- PUSHL(FS);
- PUSHL(DS);
- PUSHL(ES); if (cpu_state.abrt) return;
- loadseg(0,&cpu_state.seg_ds);
- loadseg(0,&cpu_state.seg_es);
- loadseg(0,&cpu_state.seg_fs);
- loadseg(0,&cpu_state.seg_gs);
- }
- PUSHL(oldss);
- PUSHL(oldsp);
- PUSHL(cpu_state.flags | (cpu_state.eflags << 16));
- PUSHL(CS);
- PUSHL(cpu_state.pc); if (cpu_state.abrt) return;
- }
- else
- {
- PUSHW(oldss);
- PUSHW(oldsp);
- PUSHW(cpu_state.flags);
- PUSHW(CS);
- PUSHW(cpu_state.pc); if (cpu_state.abrt) return;
- }
- cpl_override=0;
- cpu_state.seg_cs.access=0 | 0x80;
- cycles -= timing_int_pm_outer - timing_int_pm;
- break;
- }
- else if (DPL2!=CPL)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- /*FALLTHROUGH*/
- case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
- if (!(segdat2[2]&0x8000))
- {
- x86np("Int gate CS not present\n", segdat[1] & 0xfffc);
- return;
- }
- if ((cpu_state.eflags & VM_FLAG) && DPL20x800)
- {
- PUSHL(cpu_state.flags | (cpu_state.eflags << 16));
- PUSHL(CS);
- PUSHL(cpu_state.pc); if (cpu_state.abrt) return;
- }
- else
- {
- PUSHW(cpu_state.flags);
- PUSHW(CS);
- PUSHW(cpu_state.pc); if (cpu_state.abrt) return;
- }
- new_cpl = CS & 3;
- break;
- default:
- x86gpf(NULL,seg&~3);
- return;
- }
- do_seg_load(&cpu_state.seg_cs, segdat2);
- CS = (seg & ~3) | new_cpl;
- cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~(3 << 5)) | (new_cpl << 5);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- if (type>0x800) cpu_state.pc=segdat[0]|(segdat[3]<<16);
- else cpu_state.pc=segdat[0];
- set_use32(segdat2[3]&0x40);
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, oaddr+4, segdat2[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
-
- cpu_state.eflags &= ~VM_FLAG;
- cpu_cur_status &= ~CPU_STATUS_V86;
- if (!(type&0x100))
- cpu_state.flags &= ~I_FLAG;
- cpu_state.flags &= ~(T_FLAG|NT_FLAG);
- cycles -= timing_int_pm;
- break;
-
- case 0x500: /*Task gate*/
- seg=segdat[1];
- addr=seg&~7;
- if (seg&4)
- {
- if (addr>=ldt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat2[0]=readmemw(0,addr);
- segdat2[1]=readmemw(0,addr+2);
- segdat2[2]=readmemw(0,addr+4);
- segdat2[3]=readmemw(0,addr+6);
- cpl_override=0; if (cpu_state.abrt) return;
- if (!(segdat2[2]&0x8000))
- {
- x86np("Int task gate not present\n", segdat[1] & 0xfffc);
- return;
- }
- optype=OPTYPE_INT;
- cpl_override=1;
- taskswitch286(seg,segdat2,segdat2[2]&0x800);
- cpl_override=0;
- break;
-
- default:
- x86gpf(NULL,seg&~3);
- return;
- }
-}
-
-void pmodeiret(int is32)
-{
- uint32_t newsp;
- uint16_t newss;
- uint32_t tempflags,flagmask;
- uint32_t newpc;
- uint16_t segdat[4],segdat2[4];
- uint16_t segs[4];
- uint16_t seg = 0;
- uint32_t addr, oaddr;
- uint32_t oldsp=ESP;
- if (is386 && (cpu_state.eflags & VM_FLAG))
- {
- if (IOPL!=3)
- {
- x86gpf(NULL,0);
- return;
- }
- if (is32)
- {
- newpc=POPL();
- seg=POPL();
- tempflags=POPL(); if (cpu_state.abrt) return;
- }
- else
- {
- newpc=POPW();
- seg=POPW();
- tempflags=POPW(); if (cpu_state.abrt) return;
- }
- cpu_state.pc=newpc;
- cpu_state.seg_cs.base=seg<<4;
- cpu_state.seg_cs.limit=0xFFFF;
- cpu_state.seg_cs.limit_low = 0;
- cpu_state.seg_cs.limit_high = 0xffff;
- cpu_state.seg_cs.access |= 0x80;
- cpu_state.seg_cs.ar_high = 0x10;
- CS=seg;
- cpu_state.flags = (cpu_state.flags & 0x3000) | (tempflags & 0xCFD5) | 2;
- cycles -= timing_iret_rm;
- return;
- }
-
- if (cpu_state.flags & NT_FLAG)
- {
- seg=readmemw(tr.base,0);
- addr=seg&~7;
- if (seg&4)
- {
- x86seg_log("TS LDT %04X %04X IRET\n",seg,gdt.limit);
- x86ts(NULL,seg&~3);
- return;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86ts(NULL,seg&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(0,addr+2);
- segdat[2]=readmemw(0,addr+4);
- segdat[3]=readmemw(0,addr+6);
- taskswitch286(seg,segdat,segdat[2] & 0x800);
- cpl_override=0;
- return;
- }
- flagmask=0xFFFF;
- if (CPL) flagmask&=~0x3000;
- if (IOPL>16)&VM_FLAG))
- {
- newsp=POPL();
- newss=POPL();
- segs[0]=POPL();
- segs[1]=POPL();
- segs[2]=POPL();
- segs[3]=POPL(); if (cpu_state.abrt) { ESP = oldsp; return; }
- cpu_state.eflags = tempflags>>16;
- cpu_cur_status |= CPU_STATUS_V86;
- loadseg(segs[0],&cpu_state.seg_es);
- do_seg_v86_init(&cpu_state.seg_es);
- loadseg(segs[1],&cpu_state.seg_ds);
- do_seg_v86_init(&cpu_state.seg_ds);
- cpu_cur_status |= CPU_STATUS_NOTFLATDS;
- loadseg(segs[2],&cpu_state.seg_fs);
- do_seg_v86_init(&cpu_state.seg_fs);
- loadseg(segs[3],&cpu_state.seg_gs);
- do_seg_v86_init(&cpu_state.seg_gs);
-
- cpu_state.pc = newpc & 0xffff;
- cpu_state.seg_cs.base=seg<<4;
- cpu_state.seg_cs.limit=0xFFFF;
- cpu_state.seg_cs.limit_low = 0;
- cpu_state.seg_cs.limit_high = 0xffff;
- CS=seg;
- cpu_state.seg_cs.access=(3<<5) | 2 | 0x80;
- cpu_state.seg_cs.ar_high = 0x10;
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
-
- ESP=newsp;
- loadseg(newss,&cpu_state.seg_ss);
- do_seg_v86_init(&cpu_state.seg_ss);
- cpu_cur_status |= CPU_STATUS_NOTFLATSS;
- use32=0;
- cpu_cur_status &= ~CPU_STATUS_USE32;
- cpu_state.flags = (tempflags&0xFFD5)|2;
- cycles -= timing_iret_v86;
- return;
- }
- }
- else
- {
- newpc=POPW();
- seg=POPW();
- tempflags=POPW(); if (cpu_state.abrt) { ESP = oldsp; return; }
- }
- if (!(seg&~3))
- {
- ESP = oldsp;
- x86gpf(NULL,0);
- return;
- }
-
- addr=seg&~7;
- if (seg&4)
- {
- if (addr>=ldt.limit)
- {
- ESP = oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- ESP = oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- addr+=gdt.base;
- }
- if ((seg&3) < CPL)
- {
- ESP = oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- cpl_override=1;
- segdat[0]=readmemw(0,addr);
- segdat[1]=readmemw(0,addr+2);
- segdat[2]=readmemw(0,addr+4);
- segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP = oldsp; return; }
-
- switch (segdat[2]&0x1F00)
- {
- case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming code*/
- if ((seg&3) != DPL)
- {
- ESP = oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- break;
- case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming code*/
- if ((seg&3) < DPL)
- {
- ESP = oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- break;
- default:
- ESP = oldsp;
- x86gpf(NULL,seg&~3);
- return;
- }
- if (!(segdat[2]&0x8000))
- {
- ESP = oldsp;
- x86np("IRET CS not present\n", seg & 0xfffc);
- return;
- }
- if ((seg&3) == CPL)
- {
- CS=seg;
- do_seg_load(&cpu_state.seg_cs, segdat);
- cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~(3 << 5)) | ((CS & 3) << 5);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- set_use32(segdat[3]&0x40);
-
-#ifdef CS_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat[2] | 0x100); /*Set accessed bit*/
- cpl_override = 0;
-#endif
- cycles -= timing_iret_pm;
- }
- else /*Return to outer level*/
- {
- oaddr = addr;
- x86seg_log("Outer level\n");
- if (is32)
- {
- newsp=POPL();
- newss=POPL(); if (cpu_state.abrt) { ESP = oldsp; return; }
- }
- else
- {
- newsp=POPW();
- newss=POPW(); if (cpu_state.abrt) { ESP = oldsp; return; }
- }
-
- x86seg_log("IRET load stack %04X:%04X\n",newss,newsp);
-
- if (!(newss&~3))
- {
- ESP = oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- addr=newss&~7;
- if (newss&4)
- {
- if (addr>=ldt.limit)
- {
- ESP = oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- ESP = oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- addr+=gdt.base;
- }
- cpl_override=1;
- segdat2[0]=readmemw(0,addr);
- segdat2[1]=readmemw(0,addr+2);
- segdat2[2]=readmemw(0,addr+4);
- segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP = oldsp; return; }
- if ((newss & 3) != (seg & 3))
- {
- ESP = oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- if ((segdat2[2]&0x1A00)!=0x1200)
- {
- ESP = oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- if (DPL2 != (seg & 3))
- {
- ESP = oldsp;
- x86gpf(NULL,newss&~3);
- return;
- }
- if (!(segdat2[2]&0x8000))
- {
- ESP = oldsp;
- x86np("IRET loading SS not present\n", newss & 0xfffc);
- return;
- }
- SS=newss;
- set_stack32((segdat2[3] & 0x40) ? 1 : 0);
- if (stack32) ESP=newsp;
- else SP=newsp;
- do_seg_load(&cpu_state.seg_ss, segdat2);
-
-#ifdef SEL_ACCESSED
- cpl_override = 1;
- writememw(0, addr+4, segdat2[2] | 0x100); /*Set accessed bit*/
-
-#ifdef CS_ACCESSED
- writememw(0, oaddr+4, segdat[2] | 0x100); /*Set accessed bit*/
-#endif
- cpl_override = 0;
-#endif
- /*Conforming segments don't change CPL, so CPL = RPL*/
- if (segdat[2]&0x400)
- segdat[2] = (segdat[2] & ~(3 << (5+8))) | ((seg & 3) << (5+8));
-
- CS=seg;
- do_seg_load(&cpu_state.seg_cs, segdat);
- cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~(3 << 5)) | ((CS & 3) << 5);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- set_use32(segdat[3] & 0x40);
-
- check_seg_valid(&cpu_state.seg_ds);
- check_seg_valid(&cpu_state.seg_es);
- check_seg_valid(&cpu_state.seg_fs);
- check_seg_valid(&cpu_state.seg_gs);
- cycles -= timing_iret_pm_outer;
- }
- cpu_state.pc=newpc;
- cpu_state.flags = (cpu_state.flags&~flagmask) | (tempflags&flagmask&0xFFD5)|2;
- if (is32) cpu_state.eflags = tempflags>>16;
-}
-
-void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
-{
- uint32_t base;
- uint32_t limit;
- uint32_t templ;
- uint16_t tempw;
-
- uint32_t new_cr3=0;
- uint16_t new_es,new_cs,new_ss,new_ds,new_fs,new_gs;
- uint16_t new_ldt;
-
- uint32_t new_eax,new_ebx,new_ecx,new_edx,new_esp,new_ebp,new_esi,new_edi,new_pc,new_flags;
-
- uint32_t addr;
-
- uint16_t segdat2[4];
-
- base=segdat[1]|((segdat[2]&0xFF)<<16);
- limit=segdat[0];
- if(is386)
- {
- base |= (segdat[3]>>8)<<24;
- limit |= (segdat[3]&0xF)<<16;
- }
-
- if (is32)
- {
- if (limit < 103)
- {
- x86ts(NULL, seg);
- return;
- }
-
- if (optype==JMP || optype==CALL || optype==OPTYPE_INT)
- {
- if (tr.seg&4) tempw=readmemw(ldt.base,(seg&~7)+4);
- else tempw=readmemw(gdt.base,(seg&~7)+4);
- if (cpu_state.abrt) return;
- tempw|=0x200;
- if (tr.seg&4) writememw(ldt.base,(seg&~7)+4,tempw);
- else writememw(gdt.base,(seg&~7)+4,tempw);
- }
- if (cpu_state.abrt) return;
-
- if (optype==IRET) cpu_state.flags&=~NT_FLAG;
-
- cpu_386_flags_rebuild();
- writememl(tr.base,0x1C,cr3);
- writememl(tr.base,0x20,cpu_state.pc);
- writememl(tr.base,0x24,cpu_state.flags | (cpu_state.eflags<<16));
-
- writememl(tr.base,0x28,EAX);
- writememl(tr.base,0x2C,ECX);
- writememl(tr.base,0x30,EDX);
- writememl(tr.base,0x34,EBX);
- writememl(tr.base,0x38,ESP);
- writememl(tr.base,0x3C,EBP);
- writememl(tr.base,0x40,ESI);
- writememl(tr.base,0x44,EDI);
-
- writememl(tr.base,0x48,ES);
- writememl(tr.base,0x4C,CS);
- writememl(tr.base,0x50,SS);
- writememl(tr.base,0x54,DS);
- writememl(tr.base,0x58,FS);
- writememl(tr.base,0x5C,GS);
-
- if (optype==JMP || optype==IRET)
- {
- if (tr.seg&4) tempw=readmemw(ldt.base,(tr.seg&~7)+4);
- else tempw=readmemw(gdt.base,(tr.seg&~7)+4);
- if (cpu_state.abrt) return;
- tempw&=~0x200;
- if (tr.seg&4) writememw(ldt.base,(tr.seg&~7)+4,tempw);
- else writememw(gdt.base,(tr.seg&~7)+4,tempw);
- }
- if (cpu_state.abrt) return;
-
- if (optype==OPTYPE_INT || optype==CALL)
- {
- writememl(base,0,tr.seg);
- if (cpu_state.abrt)
- return;
- }
-
-
- new_cr3=readmeml(base,0x1C);
- new_pc=readmeml(base,0x20);
- new_flags=readmeml(base,0x24);
- if (optype == OPTYPE_INT || optype == CALL)
- new_flags |= NT_FLAG;
-
- new_eax=readmeml(base,0x28);
- new_ecx=readmeml(base,0x2C);
- new_edx=readmeml(base,0x30);
- new_ebx=readmeml(base,0x34);
- new_esp=readmeml(base,0x38);
- new_ebp=readmeml(base,0x3C);
- new_esi=readmeml(base,0x40);
- new_edi=readmeml(base,0x44);
-
- new_es=readmemw(base,0x48);
- new_cs=readmemw(base,0x4C);
- new_ss=readmemw(base,0x50);
- new_ds=readmemw(base,0x54);
- new_fs=readmemw(base,0x58);
- new_gs=readmemw(base,0x5C);
- new_ldt=readmemw(base,0x60);
-
- cr0 |= 8;
-
- cr3=new_cr3;
- flushmmucache();
-
- cpu_state.pc=new_pc;
- cpu_state.flags = new_flags;
- cpu_state.eflags = new_flags>>16;
- cpu_386_flags_extract();
-
- ldt.seg=new_ldt;
- templ=(ldt.seg&~7)+gdt.base;
- ldt.limit=readmemw(0,templ);
- if (readmemb(0,templ+6)&0x80)
- {
- ldt.limit<<=12;
- ldt.limit|=0xFFF;
- }
- ldt.base=(readmemw(0,templ+2))|(readmemb(0,templ+4)<<16)|(readmemb(0,templ+7)<<24);
-
- if (cpu_state.eflags & VM_FLAG)
- {
- loadcs(new_cs);
- set_use32(0);
- cpu_cur_status |= CPU_STATUS_V86;
- }
- else
- {
- if (!(new_cs&~3))
- {
- x86ts(NULL,0);
- return;
- }
- addr=new_cs&~7;
- if (new_cs&4)
- {
- if (addr>=ldt.limit)
- {
- x86ts(NULL,new_cs&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86ts(NULL,new_cs&~3);
- return;
- }
- addr+=gdt.base;
- }
- segdat2[0]=readmemw(0,addr);
- segdat2[1]=readmemw(0,addr+2);
- segdat2[2]=readmemw(0,addr+4);
- segdat2[3]=readmemw(0,addr+6);
- if (!(segdat2[2]&0x8000))
- {
- x86np("TS loading CS not present\n", new_cs & 0xfffc);
- return;
- }
- switch (segdat2[2]&0x1F00)
- {
- case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming*/
- if ((new_cs&3) != DPL2)
- {
- x86ts(NULL,new_cs&~3);
- return;
- }
- break;
- case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
- if ((new_cs&3) < DPL2)
- {
- x86ts(NULL,new_cs&~3);
- return;
- }
- break;
- default:
- x86ts(NULL,new_cs&~3);
- return;
- }
-
- CS=new_cs;
- do_seg_load(&cpu_state.seg_cs, segdat2);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- set_use32(segdat2[3] & 0x40);
- cpu_cur_status &= ~CPU_STATUS_V86;
- }
-
- EAX=new_eax;
- ECX=new_ecx;
- EDX=new_edx;
- EBX=new_ebx;
- ESP=new_esp;
- EBP=new_ebp;
- ESI=new_esi;
- EDI=new_edi;
-
- loadseg(new_es,&cpu_state.seg_es);
- loadseg(new_ss,&cpu_state.seg_ss);
- loadseg(new_ds,&cpu_state.seg_ds);
- loadseg(new_fs,&cpu_state.seg_fs);
- loadseg(new_gs,&cpu_state.seg_gs);
- }
- else
- {
- if (limit < 43)
- {
- x86ts(NULL, seg);
- return;
- }
-
- if (optype==JMP || optype==CALL || optype==OPTYPE_INT)
- {
- if (tr.seg&4) tempw=readmemw(ldt.base,(seg&~7)+4);
- else tempw=readmemw(gdt.base,(seg&~7)+4);
- if (cpu_state.abrt) return;
- tempw|=0x200;
- if (tr.seg&4) writememw(ldt.base,(seg&~7)+4,tempw);
- else writememw(gdt.base,(seg&~7)+4,tempw);
- }
- if (cpu_state.abrt) return;
-
- if (optype == IRET)
- cpu_state.flags &= ~NT_FLAG;
-
- cpu_386_flags_rebuild();
- writememw(tr.base,0x0E,cpu_state.pc);
- writememw(tr.base,0x10,cpu_state.flags);
-
- writememw(tr.base,0x12,AX);
- writememw(tr.base,0x14,CX);
- writememw(tr.base,0x16,DX);
- writememw(tr.base,0x18,BX);
- writememw(tr.base,0x1A,SP);
- writememw(tr.base,0x1C,BP);
- writememw(tr.base,0x1E,SI);
- writememw(tr.base,0x20,DI);
-
- writememw(tr.base,0x22,ES);
- writememw(tr.base,0x24,CS);
- writememw(tr.base,0x26,SS);
- writememw(tr.base,0x28,DS);
-
- if (optype==JMP || optype==IRET)
- {
- if (tr.seg&4) tempw=readmemw(ldt.base,(tr.seg&~7)+4);
- else tempw=readmemw(gdt.base,(tr.seg&~7)+4);
- if (cpu_state.abrt) return;
- tempw&=~0x200;
- if (tr.seg&4) writememw(ldt.base,(tr.seg&~7)+4,tempw);
- else writememw(gdt.base,(tr.seg&~7)+4,tempw);
- }
- if (cpu_state.abrt) return;
-
- if (optype==OPTYPE_INT || optype==CALL)
- {
- writememw(base,0,tr.seg);
- if (cpu_state.abrt)
- return;
- }
-
- new_pc=readmemw(base,0x0E);
- new_flags=readmemw(base,0x10);
- if (optype == OPTYPE_INT || optype == CALL)
- new_flags |= NT_FLAG;
-
- new_eax=readmemw(base,0x12);
- new_ecx=readmemw(base,0x14);
- new_edx=readmemw(base,0x16);
- new_ebx=readmemw(base,0x18);
- new_esp=readmemw(base,0x1A);
- new_ebp=readmemw(base,0x1C);
- new_esi=readmemw(base,0x1E);
- new_edi=readmemw(base,0x20);
-
- new_es=readmemw(base,0x22);
- new_cs=readmemw(base,0x24);
- new_ss=readmemw(base,0x26);
- new_ds=readmemw(base,0x28);
- new_ldt=readmemw(base,0x2A);
-
- msw |= 8;
-
- cpu_state.pc=new_pc;
- cpu_state.flags = new_flags;
- cpu_386_flags_extract();
-
- ldt.seg=new_ldt;
- templ=(ldt.seg&~7)+gdt.base;
- ldt.limit=readmemw(0,templ);
- ldt.base=(readmemw(0,templ+2))|(readmemb(0,templ+4)<<16);
- if (is386)
- {
- if (readmemb(0,templ+6)&0x80)
- {
- ldt.limit<<=12;
- ldt.limit|=0xFFF;
- }
- ldt.base|=(readmemb(0,templ+7)<<24);
- }
-
- if (!(new_cs&~3))
- {
- x86ts(NULL,0);
- return;
- }
- addr=new_cs&~7;
- if (new_cs&4)
- {
- if (addr>=ldt.limit)
- {
- x86ts(NULL,new_cs&~3);
- return;
- }
- addr+=ldt.base;
- }
- else
- {
- if (addr>=gdt.limit)
- {
- x86ts(NULL,new_cs&~3);
- return;
- }
- addr+=gdt.base;
- }
- segdat2[0]=readmemw(0,addr);
- segdat2[1]=readmemw(0,addr+2);
- segdat2[2]=readmemw(0,addr+4);
- segdat2[3]=readmemw(0,addr+6);
- if (!(segdat2[2]&0x8000))
- {
- x86np("TS loading CS not present\n", new_cs & 0xfffc);
- return;
- }
- switch (segdat2[2]&0x1F00)
- {
- case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming*/
- if ((new_cs&3) != DPL2)
- {
- x86ts(NULL,new_cs&~3);
- return;
- }
- break;
- case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
- if ((new_cs&3) < DPL2)
- {
- x86ts(NULL,new_cs&~3);
- return;
- }
- break;
- default:
- x86ts(NULL,new_cs&~3);
- return;
- }
-
- CS=new_cs;
- do_seg_load(&cpu_state.seg_cs, segdat2);
- if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
- oldcpl = CPL;
- set_use32(0);
-
- EAX=new_eax | 0xFFFF0000;
- ECX=new_ecx | 0xFFFF0000;
- EDX=new_edx | 0xFFFF0000;
- EBX=new_ebx | 0xFFFF0000;
- ESP=new_esp | 0xFFFF0000;
- EBP=new_ebp | 0xFFFF0000;
- ESI=new_esi | 0xFFFF0000;
- EDI=new_edi | 0xFFFF0000;
-
- loadseg(new_es,&cpu_state.seg_es);
- loadseg(new_ss,&cpu_state.seg_ss);
- loadseg(new_ds,&cpu_state.seg_ds);
- if (is386)
- {
- loadseg(0,&cpu_state.seg_fs);
- loadseg(0,&cpu_state.seg_gs);
- }
- }
-
- tr.seg=seg;
- tr.base=base;
- tr.limit=limit;
- tr.access=segdat[2]>>8;
- tr.ar_high = 0x10;
-}
-
diff --git a/src/cpu/cpu.c b/src/cpu/cpu.c
index 122e0f732..ebb3fbfc4 100644
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -1726,6 +1726,7 @@ cpu_set(void)
x87_timings = x87_timings_387;
break;
+ case FPU_487SX:
default:
x87_timings = x87_timings_486;
}
diff --git a/src/cpu/cpu.h b/src/cpu/cpu.h
index c63aacfc7..1d15bb9c6 100644
--- a/src/cpu/cpu.h
+++ b/src/cpu/cpu.h
@@ -27,6 +27,7 @@ enum {
FPU_287,
FPU_287XL,
FPU_387,
+ FPU_487SX,
FPU_INTERNAL
};
diff --git a/src/cpu/cpu_table.c b/src/cpu/cpu_table.c
index ca84055db..bb4251640 100644
--- a/src/cpu/cpu_table.c
+++ b/src/cpu/cpu_table.c
@@ -73,6 +73,12 @@ FPU fpus_80386[] =
{"387", "387", FPU_387},
{NULL, NULL, 0}
};
+FPU fpus_486sx[] =
+{
+ {"None", "none", FPU_NONE},
+ {"487SX","487sx", FPU_487SX},
+ {NULL, NULL, 0}
+};
FPU fpus_internal[] =
{
{"Internal", "internal", FPU_INTERNAL},
@@ -259,12 +265,12 @@ CPU cpus_486DLC[] = {
CPU cpus_i486S1[] = {
/*i486*/
- {"i486SX/16", CPU_i486SX, fpus_none, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
- {"i486SX/20", CPU_i486SX, fpus_none, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
- {"i486SX/25", CPU_i486SX, fpus_none, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
- {"i486SX/33", CPU_i486SX, fpus_none, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
- {"i486SX2/50", CPU_i486SX2, fpus_none, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
- {"i486SX2/66 (Q0569)", CPU_i486SX2, fpus_none, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
+ {"i486SX/16", CPU_i486SX, fpus_486sx, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
+ {"i486SX/20", CPU_i486SX, fpus_486sx, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
+ {"i486SX/25", CPU_i486SX, fpus_486sx, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
+ {"i486SX/33", CPU_i486SX, fpus_486sx, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
+ {"i486SX2/50", CPU_i486SX2, fpus_486sx, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
+ {"i486SX2/66 (Q0569)", CPU_i486SX2, fpus_486sx, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
{"i486DX/25", CPU_i486DX, fpus_internal, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486DX/33", CPU_i486DX, fpus_internal, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486DX/50", CPU_i486DX, fpus_internal, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
@@ -277,10 +283,10 @@ CPU cpus_i486S1[] = {
};
CPU cpus_Am486S1[] = {
/*Am486*/
- {"Am486SX/33", CPU_Am486SX, fpus_none, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
- {"Am486SX/40", CPU_Am486SX, fpus_none, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
- {"Am486SX2/50", CPU_Am486SX2, fpus_none, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
- {"Am486SX2/66", CPU_Am486SX2, fpus_none, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
+ {"Am486SX/33", CPU_Am486SX, fpus_486sx, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
+ {"Am486SX/40", CPU_Am486SX, fpus_486sx, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
+ {"Am486SX2/50", CPU_Am486SX2, fpus_486sx, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
+ {"Am486SX2/66", CPU_Am486SX2, fpus_486sx, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/
{"Am486DX/33", CPU_Am486DX, fpus_internal, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Am486DX/40", CPU_Am486DX, fpus_internal, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Am486DX2/50", CPU_Am486DX2, fpus_internal, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
@@ -290,9 +296,9 @@ CPU cpus_Am486S1[] = {
};
CPU cpus_Cx486S1[] = {
/*Cyrix 486*/
- {"Cx486S/25", CPU_Cx486S, fpus_none, 25000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
- {"Cx486S/33", CPU_Cx486S, fpus_none, 33333333, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
- {"Cx486S/40", CPU_Cx486S, fpus_none, 40000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
+ {"Cx486S/25", CPU_Cx486S, fpus_486sx, 25000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
+ {"Cx486S/33", CPU_Cx486S, fpus_486sx, 33333333, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
+ {"Cx486S/40", CPU_Cx486S, fpus_486sx, 40000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX/33", CPU_Cx486DX, fpus_internal, 33333333, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486DX/40", CPU_Cx486DX, fpus_internal, 40000000, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX2/50", CPU_Cx486DX2, fpus_internal, 50000000, 2.0, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
@@ -303,12 +309,12 @@ CPU cpus_Cx486S1[] = {
CPU cpus_i486[] = {
/*i486/P24T*/
- {"i486SX/16", CPU_i486SX, fpus_none, 16000000, 1.0, 0x420, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 3, 3, 3, 3, 2},
- {"i486SX/20", CPU_i486SX, fpus_none, 20000000, 1.0, 0x420, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
- {"i486SX/25", CPU_i486SX, fpus_none, 25000000, 1.0, 0x422, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
- {"i486SX/33", CPU_i486SX, fpus_none, 33333333, 1.0, 0x42a, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
- {"i486SX2/50", CPU_i486SX2, fpus_none, 50000000, 2.0, 0x45b, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
- {"i486SX2/66 (Q0569)", CPU_i486SX2, fpus_none, 66666666, 2.0, 0x45b, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 8},
+ {"i486SX/16", CPU_i486SX, fpus_486sx, 16000000, 1.0, 0x420, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 3, 3, 3, 3, 2},
+ {"i486SX/20", CPU_i486SX, fpus_486sx, 20000000, 1.0, 0x420, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
+ {"i486SX/25", CPU_i486SX, fpus_486sx, 25000000, 1.0, 0x422, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
+ {"i486SX/33", CPU_i486SX, fpus_486sx, 33333333, 1.0, 0x42a, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
+ {"i486SX2/50", CPU_i486SX2, fpus_486sx, 50000000, 2.0, 0x45b, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
+ {"i486SX2/66 (Q0569)", CPU_i486SX2, fpus_486sx, 66666666, 2.0, 0x45b, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 8},
{"i486DX/25", CPU_i486DX, fpus_internal, 25000000, 1.0, 0x404, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
{"i486DX/33", CPU_i486DX, fpus_internal, 33333333, 1.0, 0x414, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"i486DX/50", CPU_i486DX, fpus_internal, 50000000, 1.0, 0x411, 0, 0x0000, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 6},
@@ -326,10 +332,10 @@ CPU cpus_i486[] = {
CPU cpus_Am486[] = {
/*Am486/5x86*/
- {"Am486SX/33", CPU_Am486SX, fpus_none, 33333333, 1.0, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
- {"Am486SX/40", CPU_Am486SX, fpus_none, 40000000, 1.0, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
- {"Am486SX2/50", CPU_Am486SX2, fpus_none, 50000000, 2.0, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
- {"Am486SX2/66", CPU_Am486SX2, fpus_none, 66666666, 2.0, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
+ {"Am486SX/33", CPU_Am486SX, fpus_486sx, 33333333, 1.0, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
+ {"Am486SX/40", CPU_Am486SX, fpus_486sx, 40000000, 1.0, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
+ {"Am486SX2/50", CPU_Am486SX2, fpus_486sx, 50000000, 2.0, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/
+ {"Am486SX2/66", CPU_Am486SX2, fpus_486sx, 66666666, 2.0, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
{"Am486DX/33", CPU_Am486DX, fpus_internal, 33333333, 1.0, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Am486DX/40", CPU_Am486DX, fpus_internal, 40000000, 1.0, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Am486DX2/50", CPU_Am486DX2, fpus_internal, 50000000, 2.0, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
@@ -347,9 +353,9 @@ CPU cpus_Am486[] = {
CPU cpus_Cx486[] = {
/*Cyrix 486*/
- {"Cx486S/25", CPU_Cx486S, fpus_none, 25000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
- {"Cx486S/33", CPU_Cx486S, fpus_none, 33333333, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
- {"Cx486S/40", CPU_Cx486S, fpus_none, 40000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
+ {"Cx486S/25", CPU_Cx486S, fpus_486sx, 25000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3},
+ {"Cx486S/33", CPU_Cx486S, fpus_486sx, 33333333, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
+ {"Cx486S/40", CPU_Cx486S, fpus_486sx, 40000000, 1.0, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX/33", CPU_Cx486DX, fpus_internal, 33333333, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4},
{"Cx486DX/40", CPU_Cx486DX, fpus_internal, 40000000, 1.0, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5},
{"Cx486DX2/50", CPU_Cx486DX2, fpus_internal, 50000000, 2.0, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6},
diff --git a/src/codegen/x86_ops_shift.h b/src/cpu/x86_ops_shift.h
similarity index 63%
rename from src/codegen/x86_ops_shift.h
rename to src/cpu/x86_ops_shift.h
index 5cf44943d..b2812d8a7 100644
--- a/src/codegen/x86_ops_shift.h
+++ b/src/cpu/x86_ops_shift.h
@@ -1,3 +1,235 @@
+#ifdef USE_NEW_DYNAREC
+#define OP_SHIFT_b(c, ea32) \
+ { \
+ uint8_t temp_orig = temp; \
+ if (!c) return 0; \
+ flags_rebuild(); \
+ switch (rmdat & 0x38) \
+ { \
+ case 0x00: /*ROL b, c*/ \
+ temp = (temp << (c & 7)) | (temp >> (8-(c & 7))); \
+ seteab(temp); if (cpu_state.abrt) return 1; \
+ set_flags_rotate(FLAGS_ROL8, temp); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x08: /*ROR b,CL*/ \
+ temp = (temp >> (c & 7)) | (temp << (8-(c & 7))); \
+ seteab(temp); if (cpu_state.abrt) return 1; \
+ set_flags_rotate(FLAGS_ROR8, temp); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x10: /*RCL b,CL*/ \
+ temp2 = cpu_state.flags & C_FLAG; \
+ if (is486) CLOCK_CYCLES_ALWAYS(c); \
+ while (c > 0) \
+ { \
+ tempc = temp2 ? 1 : 0; \
+ temp2 = temp & 0x80; \
+ temp = (temp << 1) | tempc; \
+ c--; \
+ } \
+ seteab(temp); if (cpu_state.abrt) return 1; \
+ cpu_state.flags &= ~(C_FLAG | V_FLAG); \
+ if (temp2) cpu_state.flags |= C_FLAG; \
+ if ((cpu_state.flags & C_FLAG) ^ (temp >> 7)) cpu_state.flags |= V_FLAG; \
+ CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
+ PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x18: /*RCR b,CL*/ \
+ temp2 = cpu_state.flags & C_FLAG; \
+ if (is486) CLOCK_CYCLES_ALWAYS(c); \
+ while (c > 0) \
+ { \
+ tempc = temp2 ? 0x80 : 0; \
+ temp2 = temp & 1; \
+ temp = (temp >> 1) | tempc; \
+ c--; \
+ } \
+ seteab(temp); if (cpu_state.abrt) return 1; \
+ cpu_state.flags &= ~(C_FLAG | V_FLAG); \
+ if (temp2) cpu_state.flags |= C_FLAG; \
+ if ((temp ^ (temp >> 1)) & 0x40) cpu_state.flags |= V_FLAG; \
+ CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
+ PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x20: case 0x30: /*SHL b,CL*/ \
+ seteab(temp << c); if (cpu_state.abrt) return 1; \
+ set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x28: /*SHR b,CL*/ \
+ seteab(temp >> c); if (cpu_state.abrt) return 1; \
+ set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x38: /*SAR b,CL*/ \
+ temp = (int8_t)temp >> c; \
+ seteab(temp); if (cpu_state.abrt) return 1; \
+ set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ } \
+ }
+
+#define OP_SHIFT_w(c, ea32) \
+ { \
+ uint16_t temp_orig = temp; \
+ if (!c) return 0; \
+ flags_rebuild(); \
+ switch (rmdat & 0x38) \
+ { \
+ case 0x00: /*ROL w, c*/ \
+ temp = (temp << (c & 15)) | (temp >> (16-(c & 15))); \
+ seteaw(temp); if (cpu_state.abrt) return 1; \
+ set_flags_rotate(FLAGS_ROL16, temp); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x08: /*ROR w,CL*/ \
+ temp = (temp >> (c & 15)) | (temp << (16-(c & 15))); \
+ seteaw(temp); if (cpu_state.abrt) return 1; \
+ set_flags_rotate(FLAGS_ROR16, temp); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x10: /*RCL w, c*/ \
+ temp2 = cpu_state.flags & C_FLAG; \
+ if (is486) CLOCK_CYCLES_ALWAYS(c); \
+ while (c > 0) \
+ { \
+ tempc = temp2 ? 1 : 0; \
+ temp2 = temp & 0x8000; \
+ temp = (temp << 1) | tempc; \
+ c--; \
+ } \
+ seteaw(temp); if (cpu_state.abrt) return 1; \
+ cpu_state.flags &= ~(C_FLAG | V_FLAG); \
+ if (temp2) cpu_state.flags |= C_FLAG; \
+ if ((cpu_state.flags & C_FLAG) ^ (temp >> 15)) cpu_state.flags |= V_FLAG; \
+ CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
+ PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x18: /*RCR w, c*/ \
+ temp2 = cpu_state.flags & C_FLAG; \
+ if (is486) CLOCK_CYCLES_ALWAYS(c); \
+ while (c > 0) \
+ { \
+ tempc = temp2 ? 0x8000 : 0; \
+ temp2 = temp & 1; \
+ temp = (temp >> 1) | tempc; \
+ c--; \
+ } \
+ seteaw(temp); if (cpu_state.abrt) return 1; \
+ cpu_state.flags &= ~(C_FLAG | V_FLAG); \
+ if (temp2) cpu_state.flags |= C_FLAG; \
+ if ((temp ^ (temp >> 1)) & 0x4000) cpu_state.flags |= V_FLAG; \
+ CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
+ PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x20: case 0x30: /*SHL w, c*/ \
+ seteaw(temp << c); if (cpu_state.abrt) return 1; \
+ set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x28: /*SHR w, c*/ \
+ seteaw(temp >> c); if (cpu_state.abrt) return 1; \
+ set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x38: /*SAR w, c*/ \
+ temp = (int16_t)temp >> c; \
+ seteaw(temp); if (cpu_state.abrt) return 1; \
+ set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ } \
+ }
+
+#define OP_SHIFT_l(c, ea32) \
+ { \
+ uint32_t temp_orig = temp; \
+ if (!c) return 0; \
+ flags_rebuild(); \
+ switch (rmdat & 0x38) \
+ { \
+ case 0x00: /*ROL l, c*/ \
+ temp = (temp << c) | (temp >> (32-c)); \
+ seteal(temp); if (cpu_state.abrt) return 1; \
+ set_flags_rotate(FLAGS_ROL32, temp); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x08: /*ROR l,CL*/ \
+ temp = (temp >> c) | (temp << (32-c)); \
+ seteal(temp); if (cpu_state.abrt) return 1; \
+ set_flags_rotate(FLAGS_ROR32, temp); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
+ break; \
+ case 0x10: /*RCL l, c*/ \
+ temp2 = CF_SET(); \
+ if (is486) CLOCK_CYCLES_ALWAYS(c); \
+ while (c > 0) \
+ { \
+ tempc = temp2 ? 1 : 0; \
+ temp2 = temp & 0x80000000; \
+ temp = (temp << 1) | tempc; \
+ c--; \
+ } \
+ seteal(temp); if (cpu_state.abrt) return 1; \
+ cpu_state.flags &= ~(C_FLAG | V_FLAG); \
+ if (temp2) cpu_state.flags |= C_FLAG; \
+ if ((cpu_state.flags & C_FLAG) ^ (temp >> 31)) cpu_state.flags |= V_FLAG; \
+ CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
+ PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
+ break; \
+ case 0x18: /*RCR l, c*/ \
+ temp2 = cpu_state.flags & C_FLAG; \
+ if (is486) CLOCK_CYCLES_ALWAYS(c); \
+ while (c > 0) \
+ { \
+ tempc = temp2 ? 0x80000000 : 0; \
+ temp2 = temp & 1; \
+ temp = (temp >> 1) | tempc; \
+ c--; \
+ } \
+ seteal(temp); if (cpu_state.abrt) return 1; \
+ cpu_state.flags &= ~(C_FLAG | V_FLAG); \
+ if (temp2) cpu_state.flags |= C_FLAG; \
+ if ((temp ^ (temp >> 1)) & 0x40000000) cpu_state.flags |= V_FLAG; \
+ CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
+ PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
+ break; \
+ case 0x20: case 0x30: /*SHL l, c*/ \
+ seteal(temp << c); if (cpu_state.abrt) return 1; \
+ set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
+ break; \
+ case 0x28: /*SHR l, c*/ \
+ seteal(temp >> c); if (cpu_state.abrt) return 1; \
+ set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
+ break; \
+ case 0x38: /*SAR l, c*/ \
+ temp = (int32_t)temp >> c; \
+ seteal(temp); if (cpu_state.abrt) return 1; \
+ set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
+ CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
+ PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
+ break; \
+ } \
+ }
+#else
#define OP_SHIFT_b(c, ea32) \
{ \
uint8_t temp_orig = temp; \
@@ -240,6 +472,7 @@
break; \
} \
}
+#endif
static int opC0_a16(uint32_t fetchdat)
{
@@ -564,7 +797,7 @@ static int opD3_l_a32(uint32_t fetchdat)
if (cpu_mod != 3) \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
count = getbyte() & 31; \
- operation() \
+ operation(); \
\
CLOCK_CYCLES(3); \
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
@@ -578,7 +811,7 @@ static int opD3_l_a32(uint32_t fetchdat)
if (cpu_mod != 3) \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
count = CL & 31; \
- operation() \
+ operation(); \
\
CLOCK_CYCLES(3); \
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0); \
@@ -592,7 +825,7 @@ static int opD3_l_a32(uint32_t fetchdat)
if (cpu_mod != 3) \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
count = getbyte() & 31; \
- operation() \
+ operation(); \
\
CLOCK_CYCLES(3); \
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
@@ -606,7 +839,7 @@ static int opD3_l_a32(uint32_t fetchdat)
if (cpu_mod != 3) \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
count = CL & 31; \
- operation() \
+ operation(); \
\
CLOCK_CYCLES(3); \
PREFETCH_RUN(3, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1); \
diff --git a/src/codegen/x86seg.c b/src/cpu/x86seg.c
similarity index 93%
rename from src/codegen/x86seg.c
rename to src/cpu/x86seg.c
index 17d6f279b..5a69c1ddb 100644
--- a/src/codegen/x86seg.c
+++ b/src/cpu/x86seg.c
@@ -106,11 +106,9 @@ static void seg_reset(x86seg *s)
s->limit = 0xFFFF;
s->limit_low = 0;
s->limit_high = 0xffff;
- if(s == &cpu_state.seg_cs)
+ if (s == &cpu_state.seg_cs)
{
- // TODO - When the PC is reset, initialization of the CS descriptor must be like the annotated line below.
s->base = AT ? (cpu_16bitbus ? 0xFF0000 : 0xFFFF0000) : 0xFFFF0;
- // s->base = AT ? 0xF0000 : 0xFFFF0;
s->seg = AT ? 0xF000 : 0xFFFF;
}
else
@@ -118,7 +116,6 @@ static void seg_reset(x86seg *s)
s->base = 0;
s->seg = 0;
}
-
}
void x86seg_reset()
@@ -133,7 +130,9 @@ void x86seg_reset()
void x86_doabrt(int x86_abrt)
{
+#ifndef USE_NEW_DYNAREC
CS = oldcs;
+#endif
cpu_state.pc = cpu_state.oldpc;
cpu_state.seg_cs.access = (oldcpl << 5) | 0x80;
cpu_state.seg_cs.ar_high = 0x10;
@@ -158,9 +157,11 @@ void x86_doabrt(int x86_abrt)
SP-=6;
}
- cpu_state.flags&=~I_FLAG;
- cpu_state.flags&=~T_FLAG;
- oxpc=cpu_state.pc;
+ cpu_state.flags &= ~I_FLAG;
+ cpu_state.flags &= ~T_FLAG;
+#ifndef USE_NEW_DYNAREC
+ oxpc=cpu_state.pc;
+#endif
cpu_state.pc=readmemw(0,addr);
loadcs(readmemw(0,addr+2));
return;
@@ -249,7 +250,7 @@ void do_seg_load(x86seg *s, uint16_t *segdat)
if (is386)
s->base |= ((segdat[3] >> 8) << 24);
s->access = segdat[2] >> 8;
- s->ar_high = segdat[3] & 0xff;
+ s->ar_high = segdat[3] & 0xff;
if ((segdat[2] & 0x1800) != 0x1000 || !(segdat[2] & (1 << 10))) /*expand-down*/
{
@@ -331,7 +332,11 @@ static void check_seg_valid(x86seg *s)
loadseg(0, s);
}
+#ifdef USE_NEW_DYNAREC
+int loadseg(uint16_t seg, x86seg *s)
+#else
void loadseg(uint16_t seg, x86seg *s)
+#endif
{
uint16_t segdat[4];
uint32_t addr;
@@ -344,7 +349,11 @@ void loadseg(uint16_t seg, x86seg *s)
if (s==&cpu_state.seg_ss)
{
x86ss(NULL,0);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
s->seg = 0;
s->access = 0x80;
@@ -352,32 +361,36 @@ void loadseg(uint16_t seg, x86seg *s)
s->base=-1;
if (s == &cpu_state.seg_ds)
cpu_cur_status |= CPU_STATUS_NOTFLATDS;
+#ifdef USE_NEW_DYNAREC
+ return 0;
+#else
return;
+#endif
}
addr=seg&~7;
if (seg&4)
{
-#if 0
- if (addr>=ldt.limit)
-#else
if ((addr+7)>ldt.limit)
-#endif
{
x86gpf("loadseg(): Bigger than LDT limit",seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
addr+=ldt.base;
}
else
{
-#if 0
- if (addr>=gdt.limit)
-#else
if ((addr+7)>gdt.limit)
-#endif
{
x86gpf("loadseg(): Bigger than GDT limit",seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
addr+=gdt.base;
}
@@ -385,24 +398,40 @@ void loadseg(uint16_t seg, x86seg *s)
segdat[0]=readmemw(0,addr);
segdat[1]=readmemw(0,addr+2);
segdat[2]=readmemw(0,addr+4);
+#ifdef USE_NEW_DYNAREC
+ segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return 1;
+#else
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
+#endif
dpl=(segdat[2]>>13)&3;
if (s==&cpu_state.seg_ss)
{
if (!(seg&~3))
{
- x86gpf("loadseg(): Stack segment is zero",seg&~3);
+ x86gpf("loadseg(): Zero stack segment",seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
if ((seg&3)!=CPL)
{
x86gpf("loadseg(): Stack segment RPL != CPL",seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
if (dpl!=CPL)
{
x86gpf("loadseg(): Stack segment DPL != CPL",seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
switch ((segdat[2]>>8)&0x1F)
{
@@ -410,12 +439,20 @@ void loadseg(uint16_t seg, x86seg *s)
break;
default:
x86gpf("loadseg(): Unknown stack segment type",seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
if (!(segdat[2]&0x8000))
{
x86ss(NULL,seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
set_stack32((segdat[3] & 0x40) ? 1 : 0);
}
@@ -430,33 +467,49 @@ void loadseg(uint16_t seg, x86seg *s)
case 0x1A: case 0x1B: /*Readable non-conforming code*/
if ((seg&3)>dpl)
{
- x86gpf("loadseg(): Normal segment is zero",seg&~3);
+ x86gpf("loadseg(): Normal segment RPL > DPL",seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
if ((CPL)>dpl)
{
x86gpf("loadseg(): Normal segment DPL < CPL",seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
break;
case 0x1E: case 0x1F: /*Readable conforming code*/
break;
default:
x86gpf("loadseg(): Unknown normal segment type",seg&~3);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
}
if (!(segdat[2] & 0x8000))
{
x86np("Load data seg not present", seg & 0xfffc);
+#ifdef USE_NEW_DYNAREC
+ return 1;
+#else
return;
+#endif
}
s->seg = seg;
do_seg_load(s, segdat);
#ifndef CS_ACCESSED
- if (s != &cpu_state.seg_cs)
+ if (s != &_cs)
{
#endif
#ifdef SEL_ACCESSED
@@ -506,6 +559,10 @@ void loadseg(uint16_t seg, x86seg *s)
else
cpu_cur_status |= CPU_STATUS_NOTFLATSS;
}
+
+#ifdef USE_NEW_DYNAREC
+ return cpu_state.abrt;
+#endif
}
#define DPL ((segdat[2]>>13)&3)
@@ -521,7 +578,7 @@ void loadcs(uint16_t seg)
{
if (!(seg&~3))
{
- x86gpf(NULL,0);
+ x86gpf("loadcs(): Protected mode selector is zero",0);
return;
}
addr=seg&~7;
@@ -578,7 +635,10 @@ void loadcs(uint16_t seg)
do_seg_load(&cpu_state.seg_cs, segdat);
use32=(segdat[3]&0x40)?0x300:0;
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
-
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
+
#ifdef CS_ACCESSED
cpl_override = 1;
writememw(0, addr+4, segdat[2] | 0x100); /*Set accessed bit*/
@@ -589,7 +649,7 @@ void loadcs(uint16_t seg)
{
if (!(segdat[2]&0x8000))
{
- x86np("Load CS system seg not present", seg & 0xfffc);
+ x86np("Load CS system seg not present\n", seg & 0xfffc);
return;
}
switch (segdat[2]&0xF00)
@@ -609,8 +669,11 @@ void loadcs(uint16_t seg)
CS=seg & 0xFFFF;
if (cpu_state.eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2 | 0x80;
else cpu_state.seg_cs.access=(0<<5) | 2 | 0x80;
- cpu_state.seg_cs.ar_high = 0x10;
+ cpu_state.seg_cs.ar_high = 0x10;
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
}
}
@@ -690,6 +753,9 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
do_seg_load(&cpu_state.seg_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
cycles -= timing_jmp_pm;
}
else /*System segment*/
@@ -708,7 +774,9 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
case 0xC00:
cgate32=(type&0x800);
cgate16=!cgate32;
+#ifndef USE_NEW_DYNAREC
oldcs=CS;
+#endif
cpu_state.oldpc = cpu_state.pc;
if (DPL < CPL)
{
@@ -720,16 +788,6 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
x86gpf("loadcsjmp(): Call gate DPL< RPL",seg&~3);
return;
}
- if (DPL < CPL)
- {
- x86gpf("loadcsjmp(): ex DPL < CPL",seg&~3);
- return;
- }
- if ((DPL < (seg&3)))
- {
- x86gpf("loadcsjmp(): ex (DPL < (seg&3))",seg&~3);
- return;
- }
if (!(segdat[2]&0x8000))
{
x86np("Load CS JMP call gate not present\n", seg & 0xfffc);
@@ -792,7 +850,9 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
CS=seg2;
do_seg_load(&cpu_state.seg_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
-
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
set_use32(segdat[3]&0x40);
cpu_state.pc=newpc;
@@ -813,7 +873,7 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
case 0x100: /*286 Task gate*/
case 0x900: /*386 Task gate*/
- cpu_state.pc=old_pc;
+ cpu_state.pc = old_pc;
optype=JMP;
cpl_override=1;
taskswitch286(seg,segdat,segdat[2]&0x800);
@@ -836,8 +896,11 @@ void loadcsjmp(uint16_t seg, uint32_t old_pc)
CS=seg;
if (cpu_state.eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2 | 0x80;
else cpu_state.seg_cs.access=(0<<5) | 2 | 0x80;
- cpu_state.seg_cs.ar_high = 0x10;
+ cpu_state.seg_cs.ar_high = 0x10;
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
cycles -= timing_jmp_rm;
}
}
@@ -907,7 +970,11 @@ uint32_t POPL()
return templ;
}
+#ifdef USE_NEW_DYNAREC
+void loadcscall(uint16_t seg, uint32_t old_pc)
+#else
void loadcscall(uint16_t seg)
+#endif
{
uint16_t seg2;
uint16_t segdat[4],segdat2[4],newss;
@@ -917,7 +984,7 @@ void loadcscall(uint16_t seg)
uint32_t oldss,oldsp,newsp, oldsp2;
int type;
uint16_t tempw;
-
+
if (msw&1 && !(cpu_state.eflags&VM_FLAG))
{
x86seg_log("Protected mode CS load! %04X\n", seg);
@@ -999,7 +1066,9 @@ void loadcscall(uint16_t seg)
CS=seg;
do_seg_load(&cpu_state.seg_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
-
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
#ifdef ENABLE_X86SEG_LOG
x86seg_log("Complete\n");
#endif
@@ -1013,10 +1082,12 @@ void loadcscall(uint16_t seg)
{
case 0x400: /*Call gate*/
case 0xC00: /*386 Call gate*/
- x86seg_log("Callgate %08X\n", cpu_state.pc);
+ x86seg_log("Callgate %08X\n", cpu_state.pc);
cgate32=(type&0x800);
cgate16=!cgate32;
+#ifndef USE_NEW_DYNAREC
oldcs=CS;
+#endif
count=segdat[2]&31;
if (DPL < CPL)
{
@@ -1030,7 +1101,6 @@ void loadcscall(uint16_t seg)
}
if (!(segdat[2]&0x8000))
{
- x86seg_log("Call gate not present %04X\n",seg);
x86np("Call gate not present\n", seg & 0xfffc);
return;
}
@@ -1082,12 +1152,14 @@ void loadcscall(uint16_t seg)
return;
}
-
switch (segdat[2]&0x1F00)
{
case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming code*/
if (DPL < CPL)
{
+#ifdef USE_NEW_DYNAREC
+ uint16_t oldcs = CS;
+#endif
oaddr = addr;
/*Load new stack*/
oldss=SS;
@@ -1116,11 +1188,7 @@ void loadcscall(uint16_t seg)
addr=newss&~7;
if (newss&4)
{
-#if 0
- if (addr>=ldt.limit)
-#else
if ((addr+7)>ldt.limit)
-#endif
{
x86abort("Bigger than LDT limit %04X %08X %04X CSC SS\n",newss,addr,ldt.limit);
x86ts(NULL,newss&~3);
@@ -1130,11 +1198,7 @@ void loadcscall(uint16_t seg)
}
else
{
-#if 0
- if (addr>=gdt.limit)
-#else
if ((addr+7)>gdt.limit)
-#endif
{
x86abort("Bigger than GDT limit %04X %04X CSC\n",newss,gdt.limit);
x86ts(NULL,newss&~3);
@@ -1143,12 +1207,12 @@ void loadcscall(uint16_t seg)
addr+=gdt.base;
}
cpl_override=1;
- x86seg_log("Read stack seg\n");
+ x86seg_log("Read stack seg\n");
segdat2[0]=readmemw(0,addr);
segdat2[1]=readmemw(0,addr+2);
segdat2[2]=readmemw(0,addr+4);
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
- x86seg_log("Read stack seg done!\n");
+ x86seg_log("Read stack seg done!\n");
if (((newss & 3) != DPL) || (DPL2 != DPL))
{
x86ts(NULL,newss&~3);
@@ -1172,7 +1236,7 @@ void loadcscall(uint16_t seg)
do_seg_load(&cpu_state.seg_ss, segdat2);
- x86seg_log("Set access 1\n");
+ x86seg_log("Set access 1\n");
#ifdef SEL_ACCESSED
cpl_override = 1;
@@ -1183,19 +1247,21 @@ void loadcscall(uint16_t seg)
CS=seg2;
do_seg_load(&cpu_state.seg_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
-
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
set_use32(segdat[3]&0x40);
cpu_state.pc=newpc;
-
- x86seg_log("Set access 2\n");
+
+ x86seg_log("Set access 2\n");
#ifdef CS_ACCESSED
cpl_override = 1;
writememw(0, oaddr+4, segdat[2] | 0x100); /*Set accessed bit*/
cpl_override = 0;
#endif
-
- x86seg_log("Type %04X\n",type);
+
+ x86seg_log("Type %04X\n",type);
if (type==0xC00)
{
PUSHL(oldss);
@@ -1204,6 +1270,9 @@ void loadcscall(uint16_t seg)
{
SS = oldss;
ESP = oldsp2;
+#ifdef USE_NEW_DYNAREC
+ CS = oldcs;
+#endif
return;
}
if (count)
@@ -1216,6 +1285,9 @@ void loadcscall(uint16_t seg)
{
SS = oldss;
ESP = oldsp2;
+#ifdef USE_NEW_DYNAREC
+ CS = oldcs;
+#endif
return;
}
}
@@ -1231,21 +1303,27 @@ void loadcscall(uint16_t seg)
{
SS = oldss;
ESP = oldsp2;
+#ifdef USE_NEW_DYNAREC
+ CS = oldcs;
+#endif
return;
}
- x86seg_log("Write SP to %04X:%04X\n",SS,SP);
+ x86seg_log("Write SP to %04X:%04X\n",SS,SP);
if (count)
{
while (count)
{
count--;
tempw=readmemw(oldssbase,(oldsp&0xFFFF)+(count*2));
- x86seg_log("PUSH %04X\n",tempw);
+ x86seg_log("PUSH %04X\n",tempw);
PUSHW(tempw);
if (cpu_state.abrt)
{
SS = oldss;
ESP = oldsp2;
+#ifdef USE_NEW_DYNAREC
+ CS = oldcs;
+#endif
return;
}
}
@@ -1264,6 +1342,9 @@ void loadcscall(uint16_t seg)
CS=seg2;
do_seg_load(&cpu_state.seg_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
set_use32(segdat[3]&0x40);
cpu_state.pc=newpc;
@@ -1283,7 +1364,11 @@ void loadcscall(uint16_t seg)
case 0x100: /*286 Task gate*/
case 0x900: /*386 Task gate*/
- cpu_state.pc=oxpc;
+#ifdef USE_NEW_DYNAREC
+ cpu_state.pc = old_pc;
+#else
+ cpu_state.pc = oxpc;
+#endif
cpl_override=1;
taskswitch286(seg,segdat,segdat[2]&0x800);
cpl_override=0;
@@ -1304,8 +1389,11 @@ void loadcscall(uint16_t seg)
CS=seg;
if (cpu_state.eflags&VM_FLAG) cpu_state.seg_cs.access=(3<<5) | 2 | 0x80;
else cpu_state.seg_cs.access=(0<<5) | 2 | 0x80;
- cpu_state.seg_cs.ar_high = 0x10;
+ cpu_state.seg_cs.ar_high = 0x10;
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
}
}
@@ -1417,6 +1505,9 @@ void pmoderetf(int is32, uint16_t off)
do_seg_load(&cpu_state.seg_cs, segdat);
cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~(3 << 5)) | ((CS & 3) << 5);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
set_use32(segdat[3] & 0x40);
cycles -= timing_retf_pm;
@@ -1432,7 +1523,7 @@ void pmoderetf(int is32, uint16_t off)
x86gpf("pmoderetf(): Non-conforming RPL != DPL",seg&~3);
return;
}
- x86seg_log("RETF non-conforming, %i %i\n",seg&3, DPL);
+ x86seg_log("RETF non-conforming, %i %i\n",seg&3, DPL);
break;
case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
if ((seg&3) < DPL)
@@ -1441,7 +1532,7 @@ void pmoderetf(int is32, uint16_t off)
x86gpf("pmoderetf(): Conforming RPL < DPL",seg&~3);
return;
}
- x86seg_log("RETF conforming, %i %i\n",seg&3, DPL);
+ x86seg_log("RETF conforming, %i %i\n",seg&3, DPL);
break;
default:
ESP=oldsp;
@@ -1499,7 +1590,7 @@ void pmoderetf(int is32, uint16_t off)
segdat2[1]=readmemw(0,addr+2);
segdat2[2]=readmemw(0,addr+4);
segdat2[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP=oldsp; return; }
- x86seg_log("Segment data %04X %04X %04X %04X\n", segdat2[0], segdat2[1], segdat2[2], segdat2[3]);
+ x86seg_log("Segment data %04X %04X %04X %04X\n", segdat2[0], segdat2[1], segdat2[2], segdat2[3]);
if ((newss & 3) != (seg & 3))
{
ESP=oldsp;
@@ -1539,14 +1630,17 @@ void pmoderetf(int is32, uint16_t off)
#endif
cpl_override = 0;
#endif
- /*Conforming segments don't change CPL, so CPL = RPL*/
- if (segdat[2]&0x400)
- segdat[2] = (segdat[2] & ~(3 << (5+8))) | ((seg & 3) << (5+8));
+ /*Conforming segments don't change CPL, so CPL = RPL*/
+ if (segdat[2]&0x400)
+ segdat[2] = (segdat[2] & ~(3 << (5+8))) | ((seg & 3) << (5+8));
cpu_state.pc=newpc;
CS=seg;
do_seg_load(&cpu_state.seg_cs, segdat);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
set_use32(segdat[3] & 0x40);
if (stack32) ESP+=off;
@@ -1560,11 +1654,6 @@ void pmoderetf(int is32, uint16_t off)
}
}
-void restore_stack()
-{
- ss=oldss; cpu_state.seg_ss.limit=oldsslimit;
-}
-
void pmodeint(int num, int soft)
{
uint16_t segdat[4],segdat2[4],segdat3[4];
@@ -1575,10 +1664,10 @@ void pmodeint(int num, int soft)
uint32_t newsp;
uint16_t seg = 0;
int new_cpl;
-
+
if (cpu_state.eflags&VM_FLAG && IOPL!=3 && soft)
{
- x86seg_log("V86 banned int\n");
+ x86seg_log("V86 banned int\n");
x86gpf("pmodeint(): V86 banned int",0);
return;
}
@@ -1589,7 +1678,7 @@ void pmodeint(int num, int soft)
{
/*Triple fault - reset!*/
softresetx86();
- cpu_set_edx();
+ cpu_set_edx();
}
else if (num==0xD)
{
@@ -1607,7 +1696,11 @@ void pmodeint(int num, int soft)
segdat[0]=readmemw(0,addr);
segdat[1]=readmemw(2,addr);
segdat[2]=readmemw(4,addr);
- segdat[3]=readmemw(6,addr); cpl_override=0; if (cpu_state.abrt) { /* x86seg_log("Abrt reading from %08X\n",addr); */ return; }
+ segdat[3]=readmemw(6,addr); cpl_override=0;
+ if (cpu_state.abrt) {
+ x86seg_log("Abrt reading from %08X\n",addr);
+ return;
+ }
oaddr = addr;
x86seg_log("Addr %08X seg %04X %04X %04X %04X\n",addr,segdat[0],segdat[1],segdat[2],segdat[3]);
@@ -1675,7 +1768,7 @@ void pmodeint(int num, int soft)
x86np("Int gate CS not present\n", segdat[1] & 0xfffc);
return;
}
- if ((cpu_state.eflags&VM_FLAG) && DPL2)
+ if ((cpu_state.eflags & VM_FLAG) && DPL2)
{
x86gpf("pmodeint(): Interrupt or trap gate non-zero DPL in V86 mode",segdat[1]&0xFFFC);
return;
@@ -1770,7 +1863,7 @@ void pmodeint(int num, int soft)
}
PUSHL(oldss);
PUSHL(oldsp);
- PUSHL(cpu_state.flags|(cpu_state.eflags<<16));
+ PUSHL(cpu_state.flags | (cpu_state.eflags << 16));
PUSHL(CS);
PUSHL(cpu_state.pc); if (cpu_state.abrt) return;
}
@@ -1806,7 +1899,7 @@ void pmodeint(int num, int soft)
}
if (type>0x800)
{
- PUSHL(cpu_state.flags|(cpu_state.eflags<<16));
+ PUSHL(cpu_state.flags | (cpu_state.eflags << 16));
PUSHL(CS);
PUSHL(cpu_state.pc); if (cpu_state.abrt) return;
}
@@ -1826,6 +1919,9 @@ void pmodeint(int num, int soft)
CS = (seg & ~3) | new_cpl;
cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~(3 << 5)) | (new_cpl << 5);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
if (type>0x800) cpu_state.pc=segdat[0]|(segdat[3]<<16);
else cpu_state.pc=segdat[0];
set_use32(segdat2[3]&0x40);
@@ -1836,13 +1932,11 @@ void pmodeint(int num, int soft)
cpl_override = 0;
#endif
- cpu_state.eflags&=~VM_FLAG;
+ cpu_state.eflags &= ~VM_FLAG;
cpu_cur_status &= ~CPU_STATUS_V86;
if (!(type&0x100))
- {
- cpu_state.flags&=~I_FLAG;
- }
- cpu_state.flags&=~(T_FLAG|NT_FLAG);
+ cpu_state.flags &= ~I_FLAG;
+ cpu_state.flags &= ~(T_FLAG|NT_FLAG);
cycles -= timing_int_pm;
break;
@@ -1898,17 +1992,19 @@ void pmodeiret(int is32)
uint32_t newpc;
uint16_t segdat[4],segdat2[4];
uint16_t segs[4];
- uint16_t seg;
+ uint16_t seg = 0;
uint32_t addr, oaddr;
uint32_t oldsp=ESP;
- if (is386 && (cpu_state.eflags&VM_FLAG))
+ if (is386 && (cpu_state.eflags & VM_FLAG))
{
if (IOPL!=3)
{
x86gpf(NULL,0);
return;
}
- oxpc=cpu_state.pc;
+#ifndef USE_NEW_DYNAREC
+ oxpc=cpu_state.pc;
+#endif
if (is32)
{
newpc=POPL();
@@ -1926,15 +2022,15 @@ void pmodeiret(int is32)
cpu_state.seg_cs.limit=0xFFFF;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit_high = 0xffff;
- cpu_state.seg_cs.access |= 0x80;
- cpu_state.seg_cs.ar_high = 0x10;
+ cpu_state.seg_cs.access |= 0x80;
+ cpu_state.seg_cs.ar_high = 0x10;
CS=seg;
- cpu_state.flags=(cpu_state.flags&0x3000)|(tempflags&0xCFD5)|2;
+ cpu_state.flags = (cpu_state.flags & 0x3000) | (tempflags & 0xCFD5) | 2;
cycles -= timing_iret_rm;
return;
}
- if (cpu_state.flags&NT_FLAG)
+ if (cpu_state.flags & NT_FLAG)
{
seg=readmemw(tr.base,0);
addr=seg&~7;
@@ -1962,7 +2058,9 @@ void pmodeiret(int is32)
cpl_override=0;
return;
}
- oxpc=cpu_state.pc;
+#ifndef USE_NEW_DYNAREC
+ oxpc=cpu_state.pc;
+#endif
flagmask=0xFFFF;
if (CPL) flagmask&=~0x3000;
if (IOPL>16;
+ cpu_state.eflags = tempflags>>16;
cpu_cur_status |= CPU_STATUS_V86;
loadseg(segs[0],&cpu_state.seg_es);
do_seg_v86_init(&cpu_state.seg_es);
@@ -1989,25 +2087,28 @@ void pmodeiret(int is32)
loadseg(segs[2],&cpu_state.seg_fs);
do_seg_v86_init(&cpu_state.seg_fs);
loadseg(segs[3],&cpu_state.seg_gs);
- do_seg_v86_init(&cpu_state.seg_gs);
-
- cpu_state.pc=newpc;
+ do_seg_v86_init(&cpu_state.seg_gs);
+
+ cpu_state.pc = newpc & 0xffff;
cpu_state.seg_cs.base=seg<<4;
cpu_state.seg_cs.limit=0xFFFF;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit_high = 0xffff;
CS=seg;
cpu_state.seg_cs.access=(3<<5) | 2 | 0x80;
- cpu_state.seg_cs.ar_high=0x10;
+ cpu_state.seg_cs.ar_high = 0x10;
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
-
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
+
ESP=newsp;
loadseg(newss,&cpu_state.seg_ss);
do_seg_v86_init(&cpu_state.seg_ss);
cpu_cur_status |= CPU_STATUS_NOTFLATSS;
use32=0;
cpu_cur_status &= ~CPU_STATUS_USE32;
- cpu_state.flags=(tempflags&0xFFD5)|2;
+ cpu_state.flags = (tempflags&0xFFD5)|2;
cycles -= timing_iret_v86;
return;
}
@@ -2057,7 +2158,7 @@ void pmodeiret(int is32)
segdat[1]=readmemw(0,addr+2);
segdat[2]=readmemw(0,addr+4);
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) { ESP = oldsp; return; }
-
+
switch (segdat[2]&0x1F00)
{
case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming code*/
@@ -2093,6 +2194,9 @@ void pmodeiret(int is32)
do_seg_load(&cpu_state.seg_cs, segdat);
cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~(3 << 5)) | ((CS & 3) << 5);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
set_use32(segdat[3]&0x40);
#ifdef CS_ACCESSED
@@ -2198,8 +2302,11 @@ void pmodeiret(int is32)
do_seg_load(&cpu_state.seg_cs, segdat);
cpu_state.seg_cs.access = (cpu_state.seg_cs.access & ~(3 << 5)) | ((CS & 3) << 5);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
set_use32(segdat[3] & 0x40);
-
+
check_seg_valid(&cpu_state.seg_ds);
check_seg_valid(&cpu_state.seg_es);
check_seg_valid(&cpu_state.seg_fs);
@@ -2207,8 +2314,8 @@ void pmodeiret(int is32)
cycles -= timing_iret_pm_outer;
}
cpu_state.pc=newpc;
- cpu_state.flags=(cpu_state.flags&~flagmask)|(tempflags&flagmask&0xFFD5)|2;
- if (is32) cpu_state.eflags=tempflags>>16;
+ cpu_state.flags = (cpu_state.flags&~flagmask) | (tempflags&flagmask&0xFFD5)|2;
+ if (is32) cpu_state.eflags = tempflags>>16;
}
void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
@@ -2260,7 +2367,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
cpu_386_flags_rebuild();
writememl(tr.base,0x1C,cr3);
writememl(tr.base,0x20,cpu_state.pc);
- writememl(tr.base,0x24,cpu_state.flags|(cpu_state.eflags<<16));
+ writememl(tr.base,0x24,cpu_state.flags | (cpu_state.eflags<<16));
writememl(tr.base,0x28,EAX);
writememl(tr.base,0x2C,ECX);
@@ -2326,8 +2433,8 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
flushmmucache();
cpu_state.pc=new_pc;
- cpu_state.flags=new_flags;
- cpu_state.eflags=new_flags>>16;
+ cpu_state.flags = new_flags;
+ cpu_state.eflags = new_flags>>16;
cpu_386_flags_extract();
ldt.seg=new_ldt;
@@ -2405,6 +2512,9 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
CS=new_cs;
do_seg_load(&cpu_state.seg_cs, segdat2);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
set_use32(segdat2[3] & 0x40);
cpu_cur_status &= ~CPU_STATUS_V86;
}
@@ -2443,7 +2553,8 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
}
if (cpu_state.abrt) return;
- if (optype==IRET) cpu_state.flags&=~NT_FLAG;
+ if (optype == IRET)
+ cpu_state.flags &= ~NT_FLAG;
cpu_386_flags_rebuild();
writememw(tr.base,0x0E,cpu_state.pc);
@@ -2504,7 +2615,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
msw |= 8;
cpu_state.pc=new_pc;
- cpu_state.flags=new_flags;
+ cpu_state.flags = new_flags;
cpu_386_flags_extract();
ldt.seg=new_ldt;
@@ -2578,6 +2689,9 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
CS=new_cs;
do_seg_load(&cpu_state.seg_cs, segdat2);
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
+#ifdef USE_NEW_DYNAREC
+ oldcpl = CPL;
+#endif
set_use32(0);
EAX=new_eax | 0xFFFF0000;
@@ -2603,5 +2717,5 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
tr.base=base;
tr.limit=limit;
tr.access=segdat[2]>>8;
- tr.ar_high = segdat[3] & 0xff;
+ tr.ar_high = segdat[3] & 0xff;
}
diff --git a/src/win/win_sdl.c b/src/win/win_sdl.c
index b71595c58..11bb948b2 100644
--- a/src/win/win_sdl.c
+++ b/src/win/win_sdl.c
@@ -157,8 +157,8 @@ sdl_stretch(int *w, int *h, int *x, int *y)
}
dx = (hw - dw) / 2.0;
dy = (hh - dh) / 2.0;
- *w = (int) hw;
- *h = (int) hh;
+ *w = (int) dw;
+ *h = (int) dh;
*x = (int) dx;
*y = (int) dy;
break;
diff --git a/src/win/win_settings.c b/src/win/win_settings.c
index ebf20dbd3..32ebc3aee 100644
--- a/src/win/win_settings.c
+++ b/src/win/win_settings.c
@@ -584,6 +584,8 @@ win_settings_machine_recalc_fpu(HWND hdlg)
EnableWindow(h, TRUE);
else
EnableWindow(h, FALSE);
+
+ temp_fpu = fpu_get_type_from_index(temp_machine, temp_cpu_m, temp_cpu, SendMessage(h, CB_GETCURSEL, 0, 0));
}