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Fixes to the S3 911/924 of the night (May 4th, 2025)

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1. Actually mostly workarounds to make it render normally without a hitch (I hope) using the Diamond Stealth VRAM 911-based 15bpp driver.
2. Updated logs.
This commit is contained in:
TC1995
2025-05-04 02:01:34 +02:00
parent db842cf545
commit b1d409471c
1 changed files with 156 additions and 84 deletions
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240
src/video/vid_s3.c
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@@ -234,6 +234,8 @@ typedef struct s3_t {
uint8_t advfunc_cntl;
uint16_t cur_y, cur_y2;
uint16_t cur_x, cur_x2;
uint16_t cur_x_overflow;
uint16_t destx_overflow;
uint16_t x2, ropmix;
uint16_t pat_x, pat_y;
int16_t desty_axstp, desty_axstp2;
@@ -288,6 +290,7 @@ typedef struct s3_t {
int16_t minus;
int rd_mask_16bit_check;
int start;
int mix_dat_upper;
/*For non-threaded FIFO*/
int setup_fifo_slot;
@@ -657,22 +660,29 @@ s3_accel_out_pixtrans_w(s3_t *s3, uint16_t val)
val = (val >> 8) | (val << 8);
s3->accel_start(16, 1, val | (val << 16), 0, s3);
} else
s3->accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
} else {
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.cmd == 0x53f1) {
} else {
if ((s3->accel.cmd == 0x53f1) || (s3->accel.cmd == 0x53b1)) {
if (s3->accel.cur_x & 0x400)
val = (val >> 8) | (val << 8);
s3->accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
val = (val >> 8) | (val << 8);
s3->accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
} else
s3->accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
} else
}
s3->accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
}
} else {
if (s3->accel.rd_mask_16bit_check) {
if ((s3->accel.cmd == 0x53f1) || (s3->accel.cmd == 0x53b1)) {
if (s3->accel.cur_x & 0x400)
val = (val >> 8) | (val << 8);
s3->accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
val = (val >> 8) | (val << 8);
}
}
s3->accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
}
break;
case 0x400:
@@ -808,12 +818,14 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
case 0x8548:
case 0x86e8:
s3->accel.cur_x = (s3->accel.cur_x & 0xf00) | val;
s3->accel.cur_x_overflow = (s3->accel.cur_x_overflow & 0xff00) | val;
s3->accel.poly_cx = s3->accel.cur_x << 20;
s3->accel.poly_x = s3->accel.poly_cx >> 20;
break;
case 0x8549:
case 0x86e9:
s3->accel.cur_x = (s3->accel.cur_x & 0xff) | ((val & 0x0f) << 8);
s3->accel.cur_x_overflow = (s3->accel.cur_x_overflow & 0xff) | (val << 8);
s3->accel.poly_cx = s3->accel.poly_x = s3->accel.cur_x << 20;
s3->accel.poly_x = s3->accel.poly_cx >> 20;
s3_log("[%04X:%08X] OUT PORTB=%04x, val=%04x.\n", CS, cpu_state.pc, port - 1, s3->accel.cur_x);
@@ -859,11 +871,13 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
case 0x8d48:
case 0x8ee8:
s3->accel.destx_distp = (s3->accel.destx_distp & 0x3f00) | val;
s3->accel.destx_overflow = (s3->accel.destx_overflow & 0xff00) | val;
s3->accel.point_1_updated = 1;
break;
case 0x8d49:
case 0x8ee9:
s3->accel.destx_distp = (s3->accel.destx_distp & 0xff) | ((val & 0x3f) << 8);
s3->accel.destx_overflow = (s3->accel.destx_overflow & 0xff) | (val << 8);
if (val & 0x20)
s3->accel.destx_distp |= ~0x3fff;
s3->accel.point_1_updated = 1;
@@ -5763,6 +5777,8 @@ s3_accel_in_w(uint16_t port, void *priv)
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
uint16_t temp = 0x0000;
uint16_t temp1 = 0x0000;
uint16_t temp2 = 0x0000;
const uint16_t *vram_w = (uint16_t *) svga->vram;
if (!s3->enable_8514)
@@ -5774,7 +5790,7 @@ s3_accel_in_w(uint16_t port, void *priv)
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 0x02)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
temp = (temp >> 8) | (temp << 8);
@@ -5800,15 +5816,31 @@ s3_accel_in_w(uint16_t port, void *priv)
}
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 0x02)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
temp = (temp >> 8) | (temp << 8);
s3->accel_start(16, 1, temp | (temp << 16), 0, s3);
} else
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 16), s3);
} else {
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 16), s3);
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.cmd == 0x53b0) {
temp1 = vram_w[dword_remap_w(svga, s3->accel.dest + s3->accel.cx - s3->accel.minus) & (s3->vram_mask >> 1)];
temp2 = vram_w[dword_remap_w(svga, s3->accel.dest + s3->accel.cx - s3->accel.minus + 1) & (s3->vram_mask >> 1)];
if (s3->accel.cur_x & 0x400) {
temp = temp1 >> 8;
temp |= (temp2 >> 8) << 8;
} else {
temp = temp1 & 0xff;
temp |= ((temp2 & 0xff) << 8);
}
s3->accel_start(4, 1, 0xffffffff, temp | (temp << 16), s3);
} else
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 16), s3);
} else
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 16), s3);
}
break;
@@ -7878,7 +7910,7 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
/*Bit 4 of the Command register is the draw yes bit, which enables writing to memory/reading from memory when enabled.
When this bit is disabled, no writing to memory/reading from memory is allowed. (This bit is almost meaningless on
the NOP command)*/
s3_log("CMD=%d, full=%04x, s3bpp=%x, clr=%d, clb=%d, sourcedisplay=%x, mmio=%02x, srcbase=%08x, dstbase=%08x, cpu=%04x, mix=%04x, count=%d, rd_mask=%04x, wrt_mask=%04x, width=%d, s=%d,%d, c=%d,%d, d=%d,%d, 16bitcolor=%x, frgdcolor=%04x, bkgdcolor=%04x, frgdsel=%d, bkgdsel=%d, frgdmix=%02x, curx=%d, cury=%d, cll=%d, b2e8pix=%x.\n", cmd, s3->accel.cmd, s3->bpp, clip_r, clip_b, vram_mask, svga->crtc[0x53] & 0x18, srcbase, dstbase, cpu_dat & 0xffff, mix_dat & 0xffff, count, rd_mask, wrt_mask, s3->width, s3->accel.sx, s3->accel.sy, s3->accel.cx, s3->accel.cy, s3->accel.dx, s3->accel.dy, s3->color_16bit, frgd_color, bkgd_color, frgd_mix, bkgd_mix, s3->accel.frgd_mix & 0x0f, s3->accel.cur_x, s3->accel.cur_y, clip_l, s3->accel.b2e8_pix);
s3_log("CMD=%d, full=%04x, s3bpp=%x, clr=%d, clb=%d, sourcedisplay=%02x, mmio=%02x, srcbase=%08x, dstbase=%08x, cpu=%04x, mix=%04x, count=%d, rd_mask=%04x, wrt_mask=%04x, width=%d, s=%d,%d, c=%d,%d, d=%d,%d, 16bitcolor=%x, frgdcolor=%04x, bkgdcolor=%04x, frgdsel=%d, bkgdsel=%d, frgdmix=%02x, curx=%d, cury=%d, cll=%d, b2e8pix=%x.\n", cmd, s3->accel.cmd, s3->bpp, clip_r, clip_b, s3->accel.multifunc[0x0a] & 0xc4, svga->crtc[0x53] & 0x18, srcbase, dstbase, cpu_dat & 0xffff, mix_dat & 0xffff, count, rd_mask, wrt_mask, s3->width, s3->accel.sx, s3->accel.sy, s3->accel.cx, s3->accel.cy, s3->accel.dx, s3->accel.dy, s3->color_16bit, frgd_color, bkgd_color, frgd_mix, bkgd_mix, s3->accel.frgd_mix & 0x0f, s3->accel.cur_x, s3->accel.cur_y, clip_l, s3->accel.b2e8_pix);
switch (cmd) {
case 0: /*NOP (Short Stroke Vectors)*/
@@ -8279,8 +8311,8 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
case 2: /*Rectangle fill*/
if (!cpu_input) /*!cpu_input is trigger to start operation*/
{
s3->accel.start = 0;
s3->accel.minus = 0;
s3->accel.mix_dat_upper = 0;
s3->accel.color_16bit_check_pixtrans = 0;
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
s3->accel.sy = s3->accel.multifunc[0] & 0xfff;
@@ -8292,11 +8324,37 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
if ((s3->bpp == 0) && s3->color_16bit) {
s3->accel.rd_mask_16bit_check = ((rd_mask & 0xff00) != 0xff00);
if (s3->accel.rd_mask_16bit_check) {
s3->accel.start = 1;
if (s3->accel.cur_x & 0x400) {
s3->accel.minus = 0x400;
if ((s3->accel.cmd == 0x41b3) && (frgd_mix == 0))
s3->accel.minus = 0;
if (s3->accel.cmd == 0x41b3) {
if (frgd_mix == 0) {
if (!(s3->accel.cur_x & 0x400))
s3->accel.color_16bit_check = 0;
} else {
if ((s3->accel.cur_x_overflow & 0xc00) == 0xc00)
s3->accel.start = 1;
else {
if (s3->accel.start) {
s3->accel.start = 0;
s3->accel.minus = 0x400;
} else {
s3->accel.start = 0;
if (s3->accel.cur_x_overflow & 0x400)
s3->accel.minus = 0x400;
}
}
}
} else {
if ((s3->accel.cur_x_overflow & 0xc00) == 0xc00)
s3->accel.start = 1;
else {
if (s3->accel.start) {
s3->accel.start = 0;
s3->accel.minus = 0x400;
} else {
s3->accel.start = 0;
if (s3->accel.cur_x_overflow & 0x400)
s3->accel.minus = 0x400;
}
}
}
} else {
if (s3->accel.cmd & 0x100) {
@@ -8330,19 +8388,11 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
count = s3->accel.maj_axis_pcnt + 1;
s3->accel.temp_cnt = 16;
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.cur_x & 0x400) {
if (s3->accel.start) {
s3->accel.minus = 0x400;
s3->accel.start = 0;
}
if (s3->accel.minus) {
wrt_mask = (s3->accel.wrt_mask_actual[1] << 8);
frgd_color = (s3->accel.frgd_color_actual[1] << 8);
bkgd_color = (s3->accel.bkgd_color_actual[1] << 8);
} else {
if (s3->accel.start) {
s3->accel.minus = 0;
s3->accel.start = 0;
}
wrt_mask = s3->accel.wrt_mask_actual[0];
frgd_color = s3->accel.frgd_color_actual[0];
bkgd_color = s3->accel.bkgd_color_actual[0];
@@ -8355,7 +8405,7 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
if (s3->accel.cmd == 0x41b3) {
if (frgd_mix != 0) {
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.cur_x & 0x400) {
if (s3->accel.minus) {
wrt_mask = (s3->accel.wrt_mask_actual[1] << 8);
frgd_color = (s3->accel.frgd_color_actual[1] << 8);
bkgd_color = (s3->accel.bkgd_color_actual[1] << 8);
@@ -8367,39 +8417,33 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
rd_mask &= 0x00ff;
} else if (!s3->accel.rd_mask_16bit_check && (s3->accel.cur_x & 0x400))
break;
} else {
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.minus) {
wrt_mask = (s3->accel.wrt_mask_actual[1] << 8);
frgd_color = (s3->accel.frgd_color_actual[1] << 8);
bkgd_color = (s3->accel.bkgd_color_actual[1] << 8);
} else {
wrt_mask = s3->accel.wrt_mask_actual[0];
frgd_color = s3->accel.frgd_color_actual[0];
bkgd_color = s3->accel.bkgd_color_actual[0];
s3->accel.mix_dat_upper = !!(mix_dat & 0xff00);
}
rd_mask &= 0x00ff;
}
}
} else {
if (s3->accel.rd_mask_16bit_check) {
rd_mask &= 0x00ff;
if (s3->accel.cmd == 0x53b3) {
if (clip_l & 0x400) {
if (s3->accel.start) {
s3->accel.minus = 0x400;
s3->accel.start = 0;
}
wrt_mask = (s3->accel.wrt_mask_actual[1] << 8);
frgd_color = (s3->accel.frgd_color_actual[1] << 8);
bkgd_color = (s3->accel.bkgd_color_actual[1] << 8);
} else {
if (s3->accel.start) {
s3->accel.minus = 0;
s3->accel.start = 0;
}
wrt_mask = s3->accel.wrt_mask_actual[0];
frgd_color = s3->accel.frgd_color_actual[0];
bkgd_color = s3->accel.bkgd_color_actual[0];
}
if (s3->accel.minus) {
wrt_mask = (s3->accel.wrt_mask_actual[1] << 8);
frgd_color = (s3->accel.frgd_color_actual[1] << 8);
bkgd_color = (s3->accel.bkgd_color_actual[1] << 8);
} else {
if (s3->accel.cur_x & 0x400) {
wrt_mask = (s3->accel.wrt_mask_actual[1] << 8);
frgd_color = (s3->accel.frgd_color_actual[1] << 8);
bkgd_color = (s3->accel.bkgd_color_actual[1] << 8);
} else {
wrt_mask = s3->accel.wrt_mask_actual[0];
frgd_color = s3->accel.frgd_color_actual[0];
bkgd_color = s3->accel.bkgd_color_actual[0];
}
wrt_mask = s3->accel.wrt_mask_actual[0];
frgd_color = s3->accel.frgd_color_actual[0];
bkgd_color = s3->accel.bkgd_color_actual[0];
}
rd_mask &= 0x00ff;
} else {
if ((s3_cpu_src(s3)) && !(s3->accel.cmd & 0x200)) {
s3_log("FIXME: S3 911/924 15/16bpp documentation needed.\n");
@@ -8414,6 +8458,9 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
}
}
if (s3->accel.mix_dat_upper)
s3_log("CMDFULL=%04x, FRGDMIX=%x, BKGDCOLR=%04x, RDMASK=%04x, MINUS=%d, WRTMASK=%04X, MIX=%04x, CX=%d, CY=%d, SX=%d, SY=%d, PIXCNTL=%02x, 16BITCOLOR=%x, RDCHECK=%x, OVERFLOW=%d.\n", s3->accel.cmd, s3->accel.frgd_mix & 0x0f, s3->accel.bkgd_color, rd_mask, s3->accel.minus, wrt_mask, mix_dat & 0xffff, s3->accel.cx, s3->accel.cy, s3->accel.sx, s3->accel.sy, s3->accel.multifunc[0x0a] & 0xc4, s3->accel.color_16bit_check, s3->accel.rd_mask_16bit_check, (s3->accel.cur_x_overflow & 0xc00) == 0xc00);
while (count-- && (s3->accel.sy >= 0)) {
if (s3->accel.b2e8_pix && s3_cpu_src(s3) && !s3->accel.temp_cnt) {
mix_dat >>= 16;
@@ -8535,15 +8582,13 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
if (cpu_input) {
if (s3->accel.sy < 0) {
if ((s3->bpp == 0) && s3->color_16bit) {
if ((s3->accel.cmd == 0x53b3) && !s3->accel.b2e8_pix) {
if (!(clip_l & 0x400))
s3->accel.color_16bit_check = 1;
else
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.minus)
s3->accel.color_16bit_check = 0;
} else {
if (!(s3->accel.cur_x & 0x400))
s3->accel.color_16bit_check = 1;
else
s3->accel.color_16bit_check = 1;
if ((s3->accel.cmd == 0x41b3) && (frgd_mix == 0))
s3->accel.color_16bit_check = 0;
}
}
@@ -8556,10 +8601,12 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
}
if (s3->accel.sy < 0) {
if ((s3->bpp == 0) && s3->color_16bit) {
if (!(s3->accel.cur_x & 0x400))
s3->accel.color_16bit_check = 1;
else
s3->accel.color_16bit_check = 0;
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.minus)
s3->accel.color_16bit_check = 0;
else
s3->accel.color_16bit_check = 1;
}
}
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
@@ -8674,10 +8721,24 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
s3->accel.dx = s3->accel.destx_distp & 0xfff;
s3->accel.dy = s3->accel.desty_axstp & 0xfff;
s3->accel.rd_mask_16bit_check = ((rd_mask & 0xff00) != 0xff00);
if ((s3->bpp == 0) && s3->color_16bit && (s3->accel.destx_distp & 0x400) && s3->accel.rd_mask_16bit_check)
s3->accel.minus = 0x400;
if ((s3->bpp == 0) && s3->color_16bit) {
s3->accel.rd_mask_16bit_check = ((rd_mask & 0xff00) != 0xff00);
if (s3->accel.rd_mask_16bit_check) {
if (!(s3->accel.cmd & 0x40) && !(clip_r & 0x400))
s3->accel.start = 1;
else {
if (s3->accel.start) {
s3->accel.start = 0;
s3->accel.minus = 0x400;
} else {
s3->accel.start = 0;
if (s3->accel.destx_distp & 0x400)
s3->accel.minus = 0x400;
}
}
}
}
if (s3->accel.destx_distp & 0x400) {
s3_log("BitBLT + 1024 FULLCMD=%04x: frgdcolor=%04x, s=%d,%d, d=%d,%d, frmix=%x, bkmix=%x, pixcntl=%02x.\n", s3->accel.cmd, frgd_color, s3->accel.sx, s3->accel.sy, s3->accel.dx, s3->accel.dy, frgd_mix, bkgd_mix, s3->accel.multifunc[0xa] & 0xc0);
@@ -8698,7 +8759,7 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
if ((s3->bpp == 0) && s3->color_16bit) {
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.destx_distp & 0x400) {
if (s3->accel.minus) {
wrt_mask = (s3->accel.wrt_mask_actual[1] << 8);
frgd_color = (s3->accel.frgd_color_actual[1] << 8);
bkgd_color = (s3->accel.bkgd_color_actual[1] << 8);
@@ -8712,6 +8773,9 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
break;
}
if (!vram_mask && (frgd_mix == 3))
s3_log("CMDFULL=%04x, FRGDMIX=%x, BKGDMIX=%x, RDMASK=%04x, MINUS=%d, WRTMASK=%04X, MIX=%04x, CX=%d, CY=%d, DX=%d, DY=%d, SX=%d, SY=%d, PIXCNTL=%02x, 16BITCOLOR=%x, RDCHECK=%x, CLIPL=%d, CLIPR=%d, OVERFLOW=%d.\n", s3->accel.cmd, frgd_mix, bkgd_mix, rd_mask, s3->accel.minus, wrt_mask, mix_dat & 0xffff, s3->accel.cx, s3->accel.cy, s3->accel.dx, s3->accel.dy, s3->accel.sx, s3->accel.sy, s3->accel.multifunc[0x0a] & 0xc4, s3->accel.color_16bit_check, s3->accel.rd_mask_16bit_check, clip_l, clip_r, (s3->accel.destx_overflow & 0xc00) == 0xc00);
if (!cpu_input && (frgd_mix == 3) && !vram_mask && !(s3->accel.multifunc[0xe] & 0x100) && ((s3->accel.cmd & 0xa0) == 0xa0) && ((s3->accel.frgd_mix & 0xf) == 7) && ((s3->accel.bkgd_mix & 0xf) == 7)) {
while (1) {
if ((s3->accel.dx >= clip_l) && (s3->accel.dx <= clip_r) && (s3->accel.dy >= clip_t) && (s3->accel.dy <= clip_b)) {
@@ -8728,6 +8792,7 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
s3->accel.dx++;
s3->accel.sx--;
s3->accel.dx &= 0xfff;
if (s3->accel.sx < 0) {
s3->accel.cx -= (s3->accel.maj_axis_pcnt & 0xfff) + 1;
s3->accel.dx -= (s3->accel.maj_axis_pcnt & 0xfff) + 1;
@@ -8742,11 +8807,11 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
s3->accel.sy--;
if (s3->accel.sy < 0) {
if ((s3->bpp == 0) && s3->color_16bit) {
if (!(s3->accel.destx_distp & 0x400))
s3->accel.color_16bit_check = 1;
else
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.minus)
s3->accel.color_16bit_check = 0;
else
s3->accel.color_16bit_check = 1;
}
s3->accel.destx_distp = s3->accel.dx;
s3->accel.desty_axstp = s3->accel.dy;
@@ -8824,7 +8889,11 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
s3->accel.cx--;
s3->accel.dx--;
}
s3->accel.dx &= 0xfff;
if (s3->accel.rd_mask_16bit_check)
s3->accel.dx &= 0x7ff;
else
s3->accel.dx &= 0xfff;
s3->accel.sx--;
if (s3->accel.sx < 0) {
if (s3->accel.cmd & 0x20) {
@@ -8850,21 +8919,24 @@ s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, voi
if (cpu_input) {
if (s3->accel.sy < 0) {
if ((s3->bpp == 0) && s3->color_16bit) {
if (!(s3->accel.destx_distp & 0x400))
s3->accel.color_16bit_check = 1;
else
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.minus)
s3->accel.color_16bit_check = 0;
else
s3->accel.color_16bit_check = 1;
}
}
return;
}
if (s3->accel.sy < 0) {
if ((s3->bpp == 0) && s3->color_16bit) {
if (!(s3->accel.destx_distp & 0x400))
s3->accel.color_16bit_check = 1;
if (s3->accel.rd_mask_16bit_check) {
if (s3->accel.minus)
s3->accel.color_16bit_check = 0;
else
s3->accel.color_16bit_check = 1;
if (s3->accel.mix_dat_upper && !vram_mask && (frgd_mix == 3))
s3->accel.color_16bit_check = 0;
}
s3->accel.destx_distp = s3->accel.dx;