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386DX: Fix cache defaults to be the equivalent of 0 wait states.

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OBattler
2025-09-02 16:41:30 +02:00
parent 766734eb3a
commit b825aed242
1 changed files with 28 additions and 28 deletions
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56
src/cpu/cpu_table.c
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@@ -1367,8 +1367,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 3, .mem_read_cycles = 3,
.mem_write_cycles = 3, .mem_write_cycles = 3,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 2 .atclk_div = 2
}, },
{ {
@@ -1384,8 +1384,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 4, .mem_read_cycles = 4,
.mem_write_cycles = 4, .mem_write_cycles = 4,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 3 .atclk_div = 3
}, },
{ {
@@ -1401,8 +1401,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 4, .mem_read_cycles = 4,
.mem_write_cycles = 4, .mem_write_cycles = 4,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 3 .atclk_div = 3
}, },
{ {
@@ -1418,8 +1418,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 6, .mem_read_cycles = 6,
.mem_write_cycles = 6, .mem_write_cycles = 6,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 4 .atclk_div = 4
}, },
{ {
@@ -1435,8 +1435,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 7, .mem_read_cycles = 7,
.mem_write_cycles = 7, .mem_write_cycles = 7,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 5 .atclk_div = 5
}, },
{ .name = "", 0 } { .name = "", 0 }
@@ -1461,8 +1461,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 3, .mem_read_cycles = 3,
.mem_write_cycles = 3, .mem_write_cycles = 3,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 2 .atclk_div = 2
}, },
{ {
@@ -1478,8 +1478,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 4, .mem_read_cycles = 4,
.mem_write_cycles = 4, .mem_write_cycles = 4,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 3 .atclk_div = 3
}, },
{ {
@@ -1495,8 +1495,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 4, .mem_read_cycles = 4,
.mem_write_cycles = 4, .mem_write_cycles = 4,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 3 .atclk_div = 3
}, },
{ .name = "", 0 } { .name = "", 0 }
@@ -1521,8 +1521,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = CPU_SUPPORTS_DYNAREC, .cpu_flags = CPU_SUPPORTS_DYNAREC,
.mem_read_cycles = 4, .mem_read_cycles = 4,
.mem_write_cycles = 4, .mem_write_cycles = 4,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 3 .atclk_div = 3
}, },
{ {
@@ -1538,8 +1538,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = CPU_SUPPORTS_DYNAREC, .cpu_flags = CPU_SUPPORTS_DYNAREC,
.mem_read_cycles = 6, .mem_read_cycles = 6,
.mem_write_cycles = 6, .mem_write_cycles = 6,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 4 .atclk_div = 4
}, },
{ {
@@ -1555,8 +1555,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = CPU_SUPPORTS_DYNAREC, .cpu_flags = CPU_SUPPORTS_DYNAREC,
.mem_read_cycles = 7, .mem_read_cycles = 7,
.mem_write_cycles = 7, .mem_write_cycles = 7,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 5 .atclk_div = 5
}, },
{ .name = "", 0 } { .name = "", 0 }
@@ -1581,8 +1581,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 4, .mem_read_cycles = 4,
.mem_write_cycles = 4, .mem_write_cycles = 4,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 3 .atclk_div = 3
}, },
{ {
@@ -1598,8 +1598,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 6, .mem_read_cycles = 6,
.mem_write_cycles = 6, .mem_write_cycles = 6,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 4 .atclk_div = 4
}, },
{ {
@@ -1615,8 +1615,8 @@ const cpu_family_t cpu_families[] = {
.cpu_flags = 0, .cpu_flags = 0,
.mem_read_cycles = 7, .mem_read_cycles = 7,
.mem_write_cycles = 7, .mem_write_cycles = 7,
.cache_read_cycles = 3, .cache_read_cycles = 2,
.cache_write_cycles = 3, .cache_write_cycles = 2,
.atclk_div = 5 .atclk_div = 5
}, },
{ .name = "", 0 } { .name = "", 0 }