Move MTRR feature away from master branch

src/cpu_common/cpu.c

@@ -2855,7 +2855,7 @@ i686_invalid_rdmsr:
 
 void cpu_WRMSR()
 {
-	uint64_t temp, temp2;
+	uint64_t temp;
 
 	cpu_log("WRMSR %08X %08X%08X\n", ECX, EDX, EAX);
         switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
@@ -2924,23 +2924,10 @@ void cpu_WRMSR()
                         break;
                         case 0x200: case 0x201: case 0x202: case 0x203: case 0x204: case 0x205: case 0x206: case 0x207:
                         case 0x208: case 0x209: case 0x20A: case 0x20B: case 0x20C: case 0x20D: case 0x20E: case 0x20F:
-                        temp = EAX | ((uint64_t)EDX << 32);
+                        if (ECX & 1)
-                        temp2 = (ECX - 0x200) >> 1;
+                                mtrr_physmask_msr[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32);
-                        if (ECX & 1) {
+                        else
-                        	cpu_log("MTRR physmask[%d] = %08llx\n", temp2, temp);
+                                mtrr_physbase_msr[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32);
-
-                        	if ((mtrr_physmask_msr[temp2] >> 11) & 0x1)
-                                	mem_del_mtrr(mtrr_physbase_msr[temp2] & ~(0xFFF), mtrr_physmask_msr[temp2] & ~(0xFFF));
-
-                                if ((temp >> 11) & 0x1)
-                                	mem_add_mtrr(mtrr_physbase_msr[temp2] & ~(0xFFF), temp & ~(0xFFF), mtrr_physbase_msr[temp2] & 0xFF);
-
-                                mtrr_physmask_msr[temp2] = temp;
-                        } else {
-                        	cpu_log("MTRR physbase[%d] = %08llx\n", temp2, temp);
-
-                                mtrr_physbase_msr[temp2] = temp;
-                        }
                         break;
                         case 0x250:
                         mtrr_fix64k_8000_msr = EAX | ((uint64_t)EDX << 32);
@@ -3236,24 +3223,11 @@ void cpu_WRMSR()
 			break;			
 			case 0x200: case 0x201: case 0x202: case 0x203: case 0x204: case 0x205: case 0x206: case 0x207:
 			case 0x208: case 0x209: case 0x20A: case 0x20B: case 0x20C: case 0x20D: case 0x20E: case 0x20F:
-                        temp = EAX | ((uint64_t)EDX << 32);
+			if (ECX & 1)
-                        temp2 = (ECX - 0x200) >> 1;
+				mtrr_physmask_msr[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32);
-                        if (ECX & 1) {
+			else
-                        	cpu_log("MTRR physmask[%d] = %08llx\n", temp2, temp);
+				mtrr_physbase_msr[(ECX - 0x200) >> 1] = EAX | ((uint64_t)EDX << 32);
-
+			break;
-                        	if ((mtrr_physmask_msr[temp2] >> 11) & 0x1)
-                                	mem_del_mtrr(mtrr_physbase_msr[temp2] & ~(0xFFF), mtrr_physmask_msr[temp2] & ~(0xFFF));
-
-                                if ((temp >> 11) & 0x1)
-                                	mem_add_mtrr(mtrr_physbase_msr[temp2] & ~(0xFFF), temp & ~(0xFFF), mtrr_physbase_msr[temp2] & 0xFF);
-
-                                mtrr_physmask_msr[temp2] = temp;
-                        } else {
-                        	cpu_log("MTRR physbase[%d] = %08llx\n", temp2, temp);
-
-                                mtrr_physbase_msr[temp2] = temp;
-                        }
-                        break;
 			case 0x250:
 			mtrr_fix64k_8000_msr = EAX | ((uint64_t)EDX << 32);
 			break;
@@ -3285,11 +3259,6 @@ i686_invalid_wrmsr:
         }
 }
 
-void cpu_INVD(uint8_t wb)
-{
-	mem_invalidate_mtrr(wb);
-}
-
 static int cyrix_addr;
 
 static void cpu_write(uint16_t addr, uint8_t val, void *priv)

src/cpu_common/cpu.h

@@ -515,7 +515,6 @@ extern void	cpu_set(void);
 extern void	cpu_CPUID(void);
 extern void	cpu_RDMSR(void);
 extern void	cpu_WRMSR(void);
-extern void	cpu_INVD(uint8_t wb);
 
 extern int      checkio(int port);
 extern void	codegen_block_end(void);

src/cpu_common/x86_ops_misc.h

@@ -743,14 +743,12 @@ static int opCLTS(uint32_t fetchdat)
 
 static int opINVD(uint32_t fetchdat)
 {
-        cpu_INVD(0);
         CLOCK_CYCLES(1000);
         CPU_BLOCK_END();
         return 0;
 }
 static int opWBINVD(uint32_t fetchdat)
 {
-        cpu_INVD(1);
         CLOCK_CYCLES(10000);
         CPU_BLOCK_END();
         return 0;

src/floppy/fdd.c

@@ -407,13 +407,6 @@ fdd_is_dd(int drive)
 }
 
 
-int
-fdd_is_hd(int drive)
-{
-    return drive_types[fdd[drive].type].flags & FLAG_HOLE1;
-}
-
-
 int
 fdd_is_ed(int drive)
 {

src/include/86box/fdd.h

@@ -43,7 +43,6 @@ extern int	fdd_can_read_medium(int drive);
 extern int	fdd_doublestep_40(int drive);
 extern int	fdd_is_525(int drive);
 extern int	fdd_is_dd(int drive);
-extern int	fdd_is_hd(int drive);
 extern int	fdd_is_ed(int drive);
 extern int	fdd_is_double_sided(int drive);
 extern void	fdd_set_head(int drive, int head);

src/include/86box/machine.h

@@ -39,7 +39,6 @@
 #define MACHINE_VIDEO_FIXED	0x004000	/* sys has ONLY int video */
 #define MACHINE_MOUSE		0x008000	/* sys has int mouse */
 #define MACHINE_NONMI		0x010000	/* sys does not have NMI's */
-#define MACHINE_COREBOOT	0x020000	/* sys has coreboot BIOS */
 #else
 #define MACHINE_PC		0x000000	/* PC architecture */
 #define MACHINE_AT		0x000001	/* PC/AT architecture */
@@ -56,7 +55,6 @@
 #define MACHINE_VIDEO_FIXED	0x004000	/* sys has ONLY int video */
 #define MACHINE_MOUSE		0x008000	/* sys has int mouse */
 #define MACHINE_NONMI		0x010000	/* sys does not have NMI's */
-#define MACHINE_COREBOOT	0x020000	/* sys has coreboot BIOS */
 #endif
 
 #define IS_ARCH(m, a)		(machines[(m)].flags & (a)) ? 1 : 0;

src/include/86box/mem.h

@@ -330,10 +330,6 @@ extern void	mem_init(void);
 extern void	mem_reset(void);
 extern void	mem_remap_top(int kb);
 
-extern void	mem_add_mtrr(uint64_t base, uint64_t mask, uint8_t type);
-extern void	mem_del_mtrr(uint64_t base, uint64_t mask);
-extern void	mem_invalidate_mtrr(uint8_t wb);
-
 
 #ifdef EMU_CPU_H
 static __inline uint32_t get_phys(uint32_t addr)

src/machine/m_at_slot1.c

@@ -105,12 +105,8 @@ machine_at_p2bls_init(const machine_t *model)
 {
     int ret;
 
-    if (model->flags & MACHINE_COREBOOT)
+    ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003",
-    	ret = bios_load_linear(L"roms/machines/p2bls/coreboot.rom",
+			   0x000c0000, 262144, 0);
-			       0x000c0000, 262144, 0);
-    else
-    	ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003",
-			       0x000c0000, 262144, 0);
 
     if (bios_only || !ret)
 	return ret;
@@ -169,12 +165,8 @@ machine_at_p3bf_init(const machine_t *model)
 {
     int ret;
 
-    if (model->flags & MACHINE_COREBOOT)
+    ret = bios_load_linear(L"roms/machines/p3bf/bx3f1006.awd",
-    	ret = bios_load_linear(L"roms/machines/p3bf/coreboot.rom",
+			   0x000c0000, 262144, 0);
-			       0x000c0000, 262144, 0);
-    else
-    	ret = bios_load_linear(L"roms/machines/p3bf/bx3f1006.awd",
-			       0x000c0000, 262144, 0);
 
     if (bios_only || !ret)
 	return ret;

src/machine/machine_table.c

@@ -270,9 +270,7 @@ const machine_t machines[] = {
 
     { "[Slot 1 BX] Gigabyte GA-6BXC",		"6bxc",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  768,   8, 255,		 machine_at_6bxc_init, NULL			},
     { "[Slot 1 BX] ASUS P2B-LS",		"p2bls",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		machine_at_p2bls_init, NULL			},
-    { "[Slot 1 BX] ASUS P2B-LS (coreboot BIOS)","p2bls_cb",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"",      NULL},     {"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_COREBOOT, 		  8, 1024,   8, 255,		machine_at_p2bls_init, NULL			},
     { "[Slot 1 BX] ASUS P3B-F",			"p3bf",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8, 1024,   8, 255,		 machine_at_p3bf_init, NULL			},
-    { "[Slot 1 BX] ASUS P3B-F (coreboot BIOS)",	"p3bf_cb",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"",      NULL},     {"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_COREBOOT, 		  8, 1024,   8, 255,		 machine_at_p3bf_init, NULL			},
     { "[Slot 1 BX] ABit BF6",			"bf6",			{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			  		  8,  768,   8, 255,		  machine_at_bf6_init, NULL			},
 
     { "[Slot 1 ZX] Packard Bell Bora Pro",	"borapro",		{{"Intel", cpus_PentiumII},   {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"",      NULL},{"",      NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC,			 		  8,  512,   8, 255,	      machine_at_borapro_init, NULL			},

src/mem.c

@@ -121,8 +121,6 @@ static mem_mapping_t	*read_mapping[MEM_MAPPINGS_NO];
 static mem_mapping_t	*write_mapping[MEM_MAPPINGS_NO];
 static uint8_t		*_mem_exec[MEM_MAPPINGS_NO];
 static int		_mem_state[MEM_MAPPINGS_NO];
-static uint8_t		*mtrr_areas[MEM_MAPPINGS_NO];
-static uint8_t		mtrr_area_refcounts[MEM_MAPPINGS_NO];
 
 #if FIXME
 #if (MEM_GRANULARITY_BITS >= 12)
@@ -652,8 +650,6 @@ uint8_t
 readmembl(uint32_t addr)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -667,12 +663,7 @@ readmembl(uint32_t addr)
     }
     addr = (uint32_t) (addr64 & rammask);
 
-    page = (addr >> MEM_GRANULARITY_BITS);
+    map = read_mapping[addr >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr)
-    	return mtrr[addr & MEM_GRANULARITY_MASK];
-
-    map = read_mapping[page];
     if (map && map->read_b)
 	return map->read_b(addr, map->p);
 
@@ -684,8 +675,6 @@ void
 writemembl(uint32_t addr, uint8_t val)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
     mem_logical_addr = addr;
 
@@ -703,14 +692,7 @@ writemembl(uint32_t addr, uint8_t val)
     }
     addr = (uint32_t) (addr64 & rammask);
 
-    page = (addr >> MEM_GRANULARITY_BITS);
+    map = write_mapping[addr >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr) {
-    	mtrr[addr & MEM_GRANULARITY_MASK] = val;
-    	return;
-    }
-
-    map = write_mapping[page];
     if (map && map->write_b)
 	map->write_b(addr, val, map->p);
 }
@@ -721,8 +703,6 @@ uint16_t
 readmemwl(uint32_t addr)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -751,12 +731,7 @@ readmemwl(uint32_t addr)
 
     addr = (uint32_t) (addr64 & rammask);
 
-    page = (addr >> MEM_GRANULARITY_BITS);
+    map = read_mapping[addr >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr)
-    	return mtrr[addr & MEM_GRANULARITY_MASK] | ((uint16_t) (mtrr[(addr + 1) & MEM_GRANULARITY_MASK]) << 8);
-
-    map = read_mapping[page];
 
     if (map && map->read_w)
 	return map->read_w(addr, map->p);
@@ -772,8 +747,6 @@ void
 writememwl(uint32_t addr, uint16_t val)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -811,15 +784,7 @@ writememwl(uint32_t addr, uint16_t val)
 
     addr = (uint32_t) (addr64 & rammask);
 
-    page = (addr >> MEM_GRANULARITY_BITS);
+    map = write_mapping[addr >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr) {
-    	mtrr[addr & MEM_GRANULARITY_MASK] = val;
-    	mtrr[(addr + 1) & MEM_GRANULARITY_MASK] = val >> 8;
-    	return;
-    }
-
-    map = write_mapping[page];
     if (map) {
 	if (map->write_w)
 		map->write_w(addr, val, map->p);
@@ -835,8 +800,6 @@ uint32_t
 readmemll(uint32_t addr)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -866,12 +829,7 @@ readmemll(uint32_t addr)
 
     addr = (uint32_t) (addr64 & rammask);
 
-    page = (addr >> MEM_GRANULARITY_BITS);
+    map = read_mapping[addr >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr)
-    	return mtrr[addr & MEM_GRANULARITY_MASK] | ((uint32_t) (mtrr[(addr + 1) & MEM_GRANULARITY_MASK]) << 8) | ((uint32_t) (mtrr[(addr + 2) & MEM_GRANULARITY_MASK]) << 16) | ((uint32_t) (mtrr[(addr + 3) & MEM_GRANULARITY_MASK]) << 24);
-
-    map = read_mapping[page];
     if (map) {
 	if (map->read_l)
 		return map->read_l(addr, map->p);
@@ -892,8 +850,6 @@ void
 writememll(uint32_t addr, uint32_t val)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -930,17 +886,7 @@ writememll(uint32_t addr, uint32_t val)
 
     addr = (uint32_t) (addr64 & rammask);
 
-    page = (addr >> MEM_GRANULARITY_BITS);
+    map = write_mapping[addr >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr) {
-    	mtrr[addr & MEM_GRANULARITY_MASK] = val;
-    	mtrr[(addr + 1) & MEM_GRANULARITY_MASK] = val >> 8;
-    	mtrr[(addr + 2) & MEM_GRANULARITY_MASK] = val >> 16;
-    	mtrr[(addr + 3) & MEM_GRANULARITY_MASK] = val >> 24;
-    	return;
-    }
-
-    map = write_mapping[page];
     if (map) {
 	if (map->write_l)
 		map->write_l(addr, val, map->p);
@@ -961,8 +907,6 @@ uint64_t
 readmemql(uint32_t addr)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -991,12 +935,7 @@ readmemql(uint32_t addr)
 
     addr  = (uint32_t) (addr64 & rammask);
 
-    page = (addr >> MEM_GRANULARITY_BITS);
+    map = read_mapping[addr >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr)
-    	return readmemll(addr) | ((uint64_t)readmemll(addr+4)<<32);
-
-    map = read_mapping[page];
     if (map && map->read_l)
 	return map->read_l(addr, map->p) | ((uint64_t)map->read_l(addr + 4, map->p) << 32);
 
@@ -1008,8 +947,6 @@ void
 writememql(uint32_t addr, uint64_t val)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
 
     mem_logical_addr = addr;
@@ -1046,21 +983,7 @@ writememql(uint32_t addr, uint64_t val)
 
     addr = (uint32_t) (addr64 & rammask);
 
-    page = (addr >> MEM_GRANULARITY_BITS);
+    map = write_mapping[addr >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr) {
-    	mtrr[addr & MEM_GRANULARITY_MASK] = val;
-    	mtrr[(addr + 1) & MEM_GRANULARITY_MASK] = val >> 8;
-    	mtrr[(addr + 2) & MEM_GRANULARITY_MASK] = val >> 16;
-    	mtrr[(addr + 3) & MEM_GRANULARITY_MASK] = val >> 24;
-    	mtrr[(addr + 4) & MEM_GRANULARITY_MASK] = val >> 32;
-    	mtrr[(addr + 5) & MEM_GRANULARITY_MASK] = val >> 40;
-    	mtrr[(addr + 6) & MEM_GRANULARITY_MASK] = val >> 48;
-    	mtrr[(addr + 7) & MEM_GRANULARITY_MASK] = val >> 56;
-    	return;
-    }
-
-    map = write_mapping[page];
     if (map) {
 	if (map->write_l) {
 		map->write_l(addr, val, map->p);
@@ -1101,8 +1024,6 @@ uint16_t
 readmemwl(uint32_t seg, uint32_t addr)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -1134,12 +1055,7 @@ readmemwl(uint32_t seg, uint32_t addr)
 
     addr2 = (uint32_t) (addr64 & rammask);
 
-    page = (addr2 >> MEM_GRANULARITY_BITS);
+    map = read_mapping[addr2 >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr)
-    	return mtrr[addr2 & MEM_GRANULARITY_MASK] | ((uint16_t) (mtrr[(addr2 + 1) & MEM_GRANULARITY_MASK]) << 8);
-
-    map = read_mapping[page];
 
     if (map && map->read_w)
 	return map->read_w(addr2, map->p);
@@ -1161,8 +1077,6 @@ void
 writememwl(uint32_t seg, uint32_t addr, uint16_t val)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -1204,15 +1118,7 @@ writememwl(uint32_t seg, uint32_t addr, uint16_t val)
 
     addr2 = (uint32_t) (addr64 & rammask);
 
-    page = (addr2 >> MEM_GRANULARITY_BITS);
+    map = write_mapping[addr2 >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr) {
-    	mtrr[addr2 & MEM_GRANULARITY_MASK] = val;
-    	mtrr[(addr2 + 1) & MEM_GRANULARITY_MASK] = val >> 8;
-    	return;
-    }
-
-    map = write_mapping[page];
 
     if (map && map->write_w) {
 	map->write_w(addr2, val, map->p);
@@ -1231,8 +1137,6 @@ uint32_t
 readmemll(uint32_t seg, uint32_t addr)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -1260,12 +1164,7 @@ readmemll(uint32_t seg, uint32_t addr)
 
     addr2 = (uint32_t) (addr64 & rammask);
 
-    page = (addr2 >> MEM_GRANULARITY_BITS);
+    map = read_mapping[addr2 >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr)
-    	return mtrr[addr2 & MEM_GRANULARITY_MASK] | ((uint32_t) (mtrr[(addr2 + 1) & MEM_GRANULARITY_MASK]) << 8) | ((uint32_t) (mtrr[(addr2 + 2) & MEM_GRANULARITY_MASK]) << 16) | ((uint32_t) (mtrr[(addr2 + 3) & MEM_GRANULARITY_MASK]) << 24);
-
-    map = read_mapping[page];
 
     if (map && map->read_l)
 	return map->read_l(addr2, map->p);
@@ -1288,8 +1187,6 @@ void
 writememll(uint32_t seg, uint32_t addr, uint32_t val)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -1326,17 +1223,7 @@ writememll(uint32_t seg, uint32_t addr, uint32_t val)
 
     addr2 = (uint32_t) (addr64 & rammask);
 
-    page = (addr2 >> MEM_GRANULARITY_BITS);
+    map = write_mapping[addr2 >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr) {
-    	mtrr[addr2 & MEM_GRANULARITY_MASK] = val;
-    	mtrr[(addr2 + 1) & MEM_GRANULARITY_MASK] = val >> 8;
-    	mtrr[(addr2 + 2) & MEM_GRANULARITY_MASK] = val >> 16;
-    	mtrr[(addr2 + 3) & MEM_GRANULARITY_MASK] = val >> 24;
-    	return;
-    }
-
-    map = write_mapping[page];
 
     if (map && map->write_l) {
 	map->write_l(addr2, val,	   map->p);
@@ -1361,8 +1248,6 @@ uint64_t
 readmemql(uint32_t seg, uint32_t addr)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -1389,12 +1274,7 @@ readmemql(uint32_t seg, uint32_t addr)
 
     addr2 = (uint32_t) (addr64 & rammask);
 
-    page = (addr2 >> MEM_GRANULARITY_BITS);
+    map = read_mapping[addr2 >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr)
-    	return readmemll(seg,addr) | ((uint64_t)readmemll(seg,addr+4)<<32);
-
-    map = read_mapping[page];
     if (map && map->read_l)
 	return map->read_l(addr2, map->p) | ((uint64_t)map->read_l(addr2 + 4, map->p) << 32);
 
@@ -1406,8 +1286,6 @@ void
 writememql(uint32_t seg, uint32_t addr, uint64_t val)
 {
     uint64_t addr64 = (uint64_t) addr;
-    uint32_t page;
-    uint8_t *mtrr;
     mem_mapping_t *map;
     uint32_t addr2 = mem_logical_addr = seg + addr;
 
@@ -1444,21 +1322,7 @@ writememql(uint32_t seg, uint32_t addr, uint64_t val)
 
     addr2 = (uint32_t) (addr64 & rammask);
 
-    page = (addr2 >> MEM_GRANULARITY_BITS);
+    map = write_mapping[addr2 >> MEM_GRANULARITY_BITS];
-    mtrr = mtrr_areas[page];
-    if (mtrr) {
-    	mtrr[addr2 & MEM_GRANULARITY_MASK] = val;
-    	mtrr[(addr2 + 1) & MEM_GRANULARITY_MASK] = val >> 8;
-    	mtrr[(addr2 + 2) & MEM_GRANULARITY_MASK] = val >> 16;
-    	mtrr[(addr2 + 3) & MEM_GRANULARITY_MASK] = val >> 24;
-    	mtrr[(addr2 + 4) & MEM_GRANULARITY_MASK] = val >> 32;
-    	mtrr[(addr2 + 5) & MEM_GRANULARITY_MASK] = val >> 40;
-    	mtrr[(addr2 + 6) & MEM_GRANULARITY_MASK] = val >> 48;
-    	mtrr[(addr2 + 7) & MEM_GRANULARITY_MASK] = val >> 56;
-    	return;
-    }
-
-    map = write_mapping[page];
 
     if (map && map->write_l) {
 	map->write_l(addr2,   val,       map->p);
@@ -2456,37 +2320,20 @@ mem_log("MEM: reset: new pages=%08lx, pages_sz=%i\n", pages, pages_sz);
 
     memset(pages, 0x00, pages_sz*sizeof(page_t));
 
-    for (c = 0; c < MEM_MAPPINGS_NO; c++) {
-    	if (mtrr_areas[c]) {
-    		free(mtrr_areas[c]);
-    		mtrr_areas[c] = 0;
-    	}
-    	mtrr_area_refcounts[c] = 0;
-    }
-
 #ifdef USE_NEW_DYNAREC
-    if (machines[machine].flags & MACHINE_COREBOOT) {
-    	/* coreboot executes code from the BIOS area, thus
-    	   requiring byte_*_mask for the entire address space,
-    	   which significantly increases memory usage. */
-    	c = ((uint64_t) (pages_sz) * MEM_GRANULARITY_SIZE) / 8;
-    } else {
-    	c = (mem_size * 1024) / 8;
-    }
-
     if (byte_dirty_mask) {
 	free(byte_dirty_mask);
 	byte_dirty_mask = NULL;
     }
-    byte_dirty_mask = malloc(c);
+    byte_dirty_mask = malloc((mem_size * 1024) / 8);
-    memset(byte_dirty_mask, 0, c);
+    memset(byte_dirty_mask, 0, (mem_size * 1024) / 8);
 
     if (byte_code_present_mask) {
 	free(byte_code_present_mask);
 	byte_code_present_mask = NULL;
     }
-    byte_code_present_mask = malloc(c);
+    byte_code_present_mask = malloc((mem_size * 1024) / 8);
-    memset(byte_code_present_mask, 0, c);
+    memset(byte_code_present_mask, 0, (mem_size * 1024) / 8);
 #endif
 
     for (c = 0; c < pages_sz; c++) {
@@ -2589,8 +2436,6 @@ mem_init(void)
     writelookup2 = malloc((1<<20)*sizeof(uintptr_t));
 #endif
 
-    memset(mtrr_areas, 0x00, MEM_MAPPINGS_NO*sizeof(uint8_t *));
-
 #if FIXME
     memset(ff_array, 0xff, sizeof(ff_array));
 #endif
@@ -2688,118 +2533,3 @@ mem_a20_recalc(void)
 
     mem_a20_state = state;
 }
-
-
-void
-mem_add_mtrr(uint64_t base, uint64_t mask, uint8_t type)
-{
-    uint64_t size = ((~mask) & 0xffffffff) + 1;
-    uint64_t page_base, page, addr;
-    uint8_t *mtrr;
-
-    mem_log("Adding MTRR base=%08llx mask=%08llx size=%08llx type=%d\n", base, mask, size, type);
-
-    if (size > 0x8000) {
-    	mem_log("Ignoring MTRR, size too big\n");
-    	return;
-    }
-
-    if (mem_addr_is_ram(base)) {
-    	mem_log("Ignoring MTRR, base is in RAM\n");
-    	return;
-    }
-
-    for (page_base = base; page_base < base + size; page_base += MEM_GRANULARITY_SIZE) {
-    	page = (page_base >> MEM_GRANULARITY_BITS);
-    	if (mtrr_areas[page]) {
-    		/* area already allocated, increase refcount and don't allocate it again */
-    		mtrr_area_refcounts[page]++;
-    		continue;
-    	}
-
-    	/* allocate area */
-    	mtrr = malloc(MEM_GRANULARITY_SIZE);
-    	if (!mtrr)
-    		fatal("Failed to allocate page for MTRR page %08llx (errno=%d)\n", page_base, errno);
-
-
-    	/* populate area with data from RAM */
-    	for (addr = 0; addr < MEM_GRANULARITY_SIZE; addr++) {
-    		mtrr[addr] = readmembl(page_base | addr);
-    	}
-
-    	/* enable area */
-    	mtrr_areas[page] = mtrr;
-    }
-}
-
-
-void
-mem_del_mtrr(uint64_t base, uint64_t mask)
-{
-    uint64_t size = ((~mask) & 0xffffffff) + 1;
-    uint64_t page_base, page;
-
-    mem_log("Deleting MTRR base=%08llx mask=%08llx size=%08llx\n", base, mask, size);
-
-    if (size > 0x8000) {
-    	mem_log("Ignoring MTRR, size too big\n");
-    	return;
-    }
-
-    if (mem_addr_is_ram(base)) {
-    	mem_log("Ignoring MTRR, base is in RAM\n");
-    	return;
-    }
-
-    for (page_base = base; page_base < base + size; page_base += MEM_GRANULARITY_SIZE) {
-    	page = (page_base >> MEM_GRANULARITY_BITS);
-        if (mtrr_areas[page]) {
-        	/* decrease reference count */
-        	if (mtrr_area_refcounts[page] > 0)
-        		mtrr_area_refcounts[page]--;
-
-        	/* if no references are left, de-allocate area */
-        	if (mtrr_area_refcounts[page] == 0) {
-        		free(mtrr_areas[page]);
-        		mtrr_areas[page] = 0;
-        	}
-        }
-    }
-}
-
-
-void
-mem_invalidate_mtrr(uint8_t wb)
-{
-    uint64_t page, page_base, addr;
-    uint8_t *mtrr;
-
-    mem_log("Invalidating cache (writeback=%d)\n", wb);
-    for (page = 0; page < MEM_MAPPINGS_NO; page++) {
-    	mtrr = mtrr_areas[page];
-    	if (mtrr) {
-    		page_base = (page << MEM_GRANULARITY_BITS);
-    		if (!mem_addr_is_ram(page_base))
-    			continue; /* don't invalidate pages not backed by RAM */
-
-    		/* temporarily set area aside */
-    		mtrr_areas[page] = 0;
-
-    		/* write data back to memory if requested */
-    		if (wb && write_mapping[page]) { /* don't write back to a page which can't be written to */
-    			for (addr = 0; addr < MEM_GRANULARITY_SIZE; addr++) {
-    				writemembl(page_base | addr, mtrr[addr]);
-    			}
-    		}
-
-    		/* re-populate area with data from memory */
-    		for (addr = 0; addr < MEM_GRANULARITY_SIZE; addr++) {
-    			mtrr[addr] = readmembl(page_base | addr);
-    		}
-
-    		/* re-enable area */
-    		mtrr_areas[page] = mtrr;
-    	}
-    }
-}

src/nvr_at.c

@@ -237,7 +237,6 @@
 #include <86box/rom.h>
 #include <86box/device.h>
 #include <86box/nvr.h>
-#include <86box/fdd.h>
 
 
 /* RTC registers and bit definitions. */
@@ -280,8 +279,6 @@
 # define REGC_UF	0x10
 #define RTC_REGD	13
 # define REGD_VRT	0x80
-#define RTC_FDD_TYPES	0x10
-#define RTC_INST_EQUIP	0x14
 #define RTC_CENTURY_AT	0x32		/* century register for AT etc */
 #define RTC_CENTURY_PS	0x37		/* century register for PS/1 PS/2 */
 #define RTC_ALDAY	0x7D		/* VIA VT82C586B - alarm day */
@@ -756,7 +753,7 @@ nvr_reset(nvr_t *nvr)
 static void
 nvr_start(nvr_t *nvr)
 {
-    int i, fdd;
+    int i;
     local_t *local = (local_t *) nvr->data;
 
     struct tm tm;
@@ -771,50 +768,6 @@ nvr_start(nvr_t *nvr)
 	nvr->regs[0x0e] = 0xff;		/* If load failed or it loaded an uninitialized NVR,
 					   mark everything as bad. */
 
-    if (machines[machine].flags & MACHINE_COREBOOT) {
-    	/* Sync floppy drive types on coreboot machines, as SeaBIOS lacks a setup
-    	   utility and just leaves these untouched. */
-
-    	nvr->regs[RTC_FDD_TYPES] = 0x00;
-    	nvr->regs[RTC_INST_EQUIP] |= 0xc0;
-
-    	for (i = 0; i <= 1; i++) {
-    		fdd = fdd_get_type(i);
-    		if (fdd) {
-    			if (fdd_is_525(i)) {
-    				if (fdd_is_hd(i))
-    					fdd = 2;
-    				else if (fdd_doublestep_40(i))
-    					fdd = 3;
-    				else
-    					fdd = 1;
-    			} else {
-    				if (fdd_is_hd(i))
-    					fdd = 4;
-    				else if (fdd_is_double_sided(i))
-    					fdd = 3;
-    				else
-    					fdd = 1;
-    			}
-
-    			nvr->regs[RTC_FDD_TYPES] |= (fdd << ((1 - i) * 4));
-    			nvr->regs[RTC_INST_EQUIP] &= 0x3f; /* At least one drive installed. */
-    		}
-    	}
-
-    	if ((nvr->regs[RTC_FDD_TYPES] >> 4) && (nvr->regs[RTC_FDD_TYPES] & 0xf))
-    		nvr->regs[RTC_INST_EQUIP] |= 0x40; /* Two drives installed. */
-
-    	/* Re-compute CMOS checksum. SeaBIOS also doesn't care about the checksum,
-    	   but Windows does. */
-    	uint16_t checksum = 0;
-    	for (i = 0x10; i <= 0x2d; i++) {
-	    	checksum += nvr->regs[i];
-    	}
-    	nvr->regs[0x2e] = checksum >> 8;
-    	nvr->regs[0x2f] = checksum;
-    }
-
     /* Initialize the internal and chip times. */
     if (time_sync & TIME_SYNC_ENABLED) {
 	/* Use the internal clock's time. */

src/spd.c

@@ -271,8 +271,8 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
     			sprintf(sdram_data->part_no, "86Box-SDR-%03dM", vslots[vslot]);
     			for (i = strlen(sdram_data->part_no); i < sizeof(sdram_data->part_no); i++)
     				sdram_data->part_no[i] = ' ';
-    			sdram_data->mfg_year = 20;
+    			sdram_data->mfg_year = 0x20;
-    			sdram_data->mfg_week = 13;
+    			sdram_data->mfg_week = 0x13;
     			sdram_data->freq = 100;
     			sdram_data->features = 0xFF;