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Phase 2.

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This commit is contained in:
OBattler
2022-04-13 02:07:23 +02:00
parent 3a40d9a807
commit ba40831002
2 changed files with 58 additions and 0 deletions
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4
src/cpu/386_ops.h
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@@ -195,7 +195,11 @@ extern void x386_dynarec_log(const char *fmt, ...);
#include "x86_ops_mul.h" #include "x86_ops_mul.h"
#include "x86_ops_pmode.h" #include "x86_ops_pmode.h"
#include "x86_ops_prefix.h" #include "x86_ops_prefix.h"
#ifdef IS_DYNAREC
#include "x86_ops_rep_dyn.h"
#else
#include "x86_ops_rep.h" #include "x86_ops_rep.h"
#endif
#include "x86_ops_ret.h" #include "x86_ops_ret.h"
#include "x86_ops_set.h" #include "x86_ops_set.h"
#include "x86_ops_stack.h" #include "x86_ops_stack.h"

54
src/cpu/x86_ops_bitscan.h
View File

@@ -1,3 +1,24 @@
#ifdef IS_DYNAREC
#define BS_common(start, end, dir, dest, time) \
flags_rebuild(); \
if (temp) \
{ \
int c; \
cpu_state.flags &= ~Z_FLAG; \
for (c = start; c != end; c += dir) \
{ \
CLOCK_CYCLES(time); \
instr_cycles += time; \
if (temp & (1 << c)) \
{ \
dest = c; \
break; \
} \
} \
} \
else \
cpu_state.flags |= Z_FLAG;
#else
#define BS_common(start, end, dir, dest, time) \ #define BS_common(start, end, dir, dest, time) \
flags_rebuild(); \ flags_rebuild(); \
instr_cycles = 0; \ instr_cycles = 0; \
@@ -18,11 +39,14 @@
} \ } \
else \ else \
cpu_state.flags |= Z_FLAG; cpu_state.flags |= Z_FLAG;
#endif
static int opBSF_w_a16(uint32_t fetchdat) static int opBSF_w_a16(uint32_t fetchdat)
{ {
uint16_t temp; uint16_t temp;
#ifndef IS_DYNAREC
int instr_cycles = 0; int instr_cycles = 0;
#endif
fetch_ea_16(fetchdat); fetch_ea_16(fetchdat);
if (cpu_mod != 3) if (cpu_mod != 3)
@@ -32,14 +56,18 @@ static int opBSF_w_a16(uint32_t fetchdat)
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3); BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10); CLOCK_CYCLES((is486) ? 6 : 10);
#ifndef IS_DYNAREC
instr_cycles += ((is486) ? 6 : 10); instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0); PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
#enif
return 0; return 0;
} }
static int opBSF_w_a32(uint32_t fetchdat) static int opBSF_w_a32(uint32_t fetchdat)
{ {
uint16_t temp; uint16_t temp;
#ifndef IS_DYNAREC
int instr_cycles = 0; int instr_cycles = 0;
#endif
fetch_ea_32(fetchdat); fetch_ea_32(fetchdat);
if (cpu_mod != 3) if (cpu_mod != 3)
@@ -49,14 +77,18 @@ static int opBSF_w_a32(uint32_t fetchdat)
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3); BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10); CLOCK_CYCLES((is486) ? 6 : 10);
#ifndef IS_DYNAREC
instr_cycles += ((is486) ? 6 : 10); instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1); PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
#endif
return 0; return 0;
} }
static int opBSF_l_a16(uint32_t fetchdat) static int opBSF_l_a16(uint32_t fetchdat)
{ {
uint32_t temp; uint32_t temp;
#ifndef IS_DYNAREC
int instr_cycles = 0; int instr_cycles = 0;
#endif
fetch_ea_16(fetchdat); fetch_ea_16(fetchdat);
if (cpu_mod != 3) if (cpu_mod != 3)
@@ -66,14 +98,18 @@ static int opBSF_l_a16(uint32_t fetchdat)
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3); BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10); CLOCK_CYCLES((is486) ? 6 : 10);
#ifndef IS_DYNAREC
instr_cycles += ((is486) ? 6 : 10); instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0); PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
#endif
return 0; return 0;
} }
static int opBSF_l_a32(uint32_t fetchdat) static int opBSF_l_a32(uint32_t fetchdat)
{ {
uint32_t temp; uint32_t temp;
#ifndef IS_DYNAREC
int instr_cycles = 0; int instr_cycles = 0;
#endif
fetch_ea_32(fetchdat); fetch_ea_32(fetchdat);
if (cpu_mod != 3) if (cpu_mod != 3)
@@ -83,15 +119,19 @@ static int opBSF_l_a32(uint32_t fetchdat)
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3); BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10); CLOCK_CYCLES((is486) ? 6 : 10);
#ifndef IS_DYNAREC
instr_cycles += ((is486) ? 6 : 10); instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1); PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
#endif
return 0; return 0;
} }
static int opBSR_w_a16(uint32_t fetchdat) static int opBSR_w_a16(uint32_t fetchdat)
{ {
uint16_t temp; uint16_t temp;
#ifndef IS_DYNAREC
int instr_cycles = 0; int instr_cycles = 0;
#endif
fetch_ea_16(fetchdat); fetch_ea_16(fetchdat);
if (cpu_mod != 3) if (cpu_mod != 3)
@@ -101,14 +141,18 @@ static int opBSR_w_a16(uint32_t fetchdat)
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3); BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
CLOCK_CYCLES((is486) ? 6 : 10); CLOCK_CYCLES((is486) ? 6 : 10);
#ifndef IS_DYNAREC
instr_cycles += ((is486) ? 6 : 10); instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0); PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
#endif
return 0; return 0;
} }
static int opBSR_w_a32(uint32_t fetchdat) static int opBSR_w_a32(uint32_t fetchdat)
{ {
uint16_t temp; uint16_t temp;
#ifndef IS_DYNAREC
int instr_cycles = 0; int instr_cycles = 0;
#endif
fetch_ea_32(fetchdat); fetch_ea_32(fetchdat);
if (cpu_mod != 3) if (cpu_mod != 3)
@@ -118,14 +162,18 @@ static int opBSR_w_a32(uint32_t fetchdat)
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3); BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
CLOCK_CYCLES((is486) ? 6 : 10); CLOCK_CYCLES((is486) ? 6 : 10);
#ifndef IS_DYNAREC
instr_cycles += ((is486) ? 6 : 10); instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1); PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
#endif
return 0; return 0;
} }
static int opBSR_l_a16(uint32_t fetchdat) static int opBSR_l_a16(uint32_t fetchdat)
{ {
uint32_t temp; uint32_t temp;
#ifndef IS_DYNAREC
int instr_cycles = 0; int instr_cycles = 0;
#enif
fetch_ea_16(fetchdat); fetch_ea_16(fetchdat);
if (cpu_mod != 3) if (cpu_mod != 3)
@@ -135,14 +183,18 @@ static int opBSR_l_a16(uint32_t fetchdat)
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3); BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
CLOCK_CYCLES((is486) ? 6 : 10); CLOCK_CYCLES((is486) ? 6 : 10);
#ifndef IS_DYNAREC
instr_cycles += ((is486) ? 6 : 10); instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0); PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
#endif
return 0; return 0;
} }
static int opBSR_l_a32(uint32_t fetchdat) static int opBSR_l_a32(uint32_t fetchdat)
{ {
uint32_t temp; uint32_t temp;
#ifndef IS_DYNAREC
int instr_cycles = 0; int instr_cycles = 0;
#endif
fetch_ea_32(fetchdat); fetch_ea_32(fetchdat);
if (cpu_mod != 3) if (cpu_mod != 3)
@@ -152,7 +204,9 @@ static int opBSR_l_a32(uint32_t fetchdat)
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3); BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
CLOCK_CYCLES((is486) ? 6 : 10); CLOCK_CYCLES((is486) ? 6 : 10);
#ifndef IS_DYNAREC
instr_cycles += ((is486) ? 6 : 10); instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1); PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
#enif
return 0; return 0;
} }