More cleanups.
Split Compaq Deskpro off to separae file. Renamed PIIX files to intel_ prefix. Re-enabled Compaq machines; the Portable II works fine now.
This commit is contained in:
waltje
736
src/intel_piix.c
Normal file
736
src/intel_piix.c
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@@ -0,0 +1,736 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* Emulation of the Intel PIIX and PIIX3 Xcelerators.
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*
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* PRD format :
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* word 0 - base address
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* word 1 - bits 1-15 = byte count, bit 31 = end of transfer
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*
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* Version: @(#)intel_piix.c 1.0.9 2017/11/11
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2008-2017 Sarah Walker.
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* Copyright 2016,2017 Miran Grca.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <wchar.h>
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#include "86box.h"
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#include "dma.h"
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#include "io.h"
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#include "device.h"
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#include "keyboard.h"
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#include "mem.h"
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#include "pci.h"
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#include "disk/hdc.h"
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#include "disk/hdc_ide.h"
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#include "piix.h"
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uint8_t piix_33 = 0;
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static uint8_t piix_type = 1;
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static uint8_t card_piix[256], card_piix_ide[256];
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uint8_t piix_bus_master_read(uint16_t port, void *priv);
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void piix_bus_master_write(uint16_t port, uint8_t val, void *priv);
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void piix_write(int func, int addr, uint8_t val, void *priv)
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{
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uint16_t old_base = (card_piix_ide[0x20] & 0xf0) | (card_piix_ide[0x21] << 8);
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if (func > 1)
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return;
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if (func == 1) /*IDE*/
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{
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/* pclog("PIIX IDE write: %02X %02X\n", addr, val); */
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switch (addr)
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{
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case 0x04:
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card_piix_ide[0x04] = (val & 5) | 2;
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break;
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case 0x07:
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card_piix_ide[0x07] = val & 0x3e;
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break;
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case 0x0d:
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card_piix_ide[0x0d] = val;
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break;
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case 0x20:
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card_piix_ide[0x20] = (val & ~0x0f) | 1;
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break;
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case 0x21:
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card_piix_ide[0x21] = val;
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break;
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case 0x40:
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card_piix_ide[0x40] = val;
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break;
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case 0x41:
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if ((val ^ card_piix_ide[0x41]) & 0x80)
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{
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ide_pri_disable();
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if (val & 0x80)
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ide_pri_enable();
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}
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card_piix_ide[0x41] = val;
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break;
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case 0x42:
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card_piix_ide[0x42] = val;
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break;
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case 0x43:
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if ((val ^ card_piix_ide[0x43]) & 0x80)
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{
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ide_sec_disable();
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if (val & 0x80)
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ide_sec_enable();
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}
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card_piix_ide[0x43] = val;
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break;
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case 0x44:
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if (piix_type >= 3) card_piix_ide[0x44] = val;
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break;
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}
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if (addr == 4 || (addr & ~3) == 0x20) /*Bus master base address*/
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{
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uint16_t base = (card_piix_ide[0x20] & 0xf0) | (card_piix_ide[0x21] << 8);
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io_removehandler(old_base, 0x10, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL);
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if (card_piix_ide[0x04] & 1)
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{
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io_sethandler(base, 0x10, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL);
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}
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}
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}
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else
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{
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/* pclog("PIIX writing value %02X to register %02X\n", val, addr); */
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if ((addr >= 0x0f) && (addr < 0x4c))
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return;
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switch (addr)
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{
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0e:
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return;
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case 0x60:
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/* pclog("Set IRQ routing: INT A -> %02X\n", val); */
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTA, val & 0xf);
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break;
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case 0x61:
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/* pclog("Set IRQ routing: INT B -> %02X\n", val); */
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTB, val & 0xf);
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break;
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case 0x62:
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/* pclog("Set IRQ routing: INT C -> %02X\n", val); */
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTC, val & 0xf);
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break;
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case 0x63:
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/* pclog("Set IRQ routing: INT D -> %02X\n", val); */
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if (val & 0x80)
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pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
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else
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pci_set_irq_routing(PCI_INTD, val & 0xf);
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break;
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case 0x70:
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/* pclog("Set MIRQ routing: MIRQ0 -> %02X\n", val); */
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if (val & 0x80)
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pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
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else
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pci_set_mirq_routing(PCI_MIRQ0, val & 0xf);
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break;
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pclog("MIRQ0 is %s\n", (val & 0x20) ? "disabled" : "enabled");
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case 0x71:
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if (piix_type == 1)
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{
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/* pclog("Set MIRQ routing: MIRQ1 -> %02X\n", val); */
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if (val & 0x80)
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pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
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else
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pci_set_mirq_routing(PCI_MIRQ1, val & 0xf);
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}
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#if 0
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else
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{
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pclog("Set unused MIRQ routing: MIRQ1 -> %02X\n", val);
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}
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#endif
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break;
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}
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if (addr == 0x4C)
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{
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if (!((val ^ card_piix[addr]) & 0x80))
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{
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card_piix[addr] = val;
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return;
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}
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card_piix[addr] = val;
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if (val & 0x80)
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{
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if (piix_type == 3)
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{
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dma_alias_remove();
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}
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else
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{
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dma_alias_remove_piix();
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}
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}
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else
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{
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dma_alias_set();
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}
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}
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else if (addr == 0x4E)
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{
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keyboard_at_set_mouse_scan((val & 0x10) ? 1 : 0);
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card_piix[addr] = val;
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}
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else if (addr == 0x6A)
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{
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if (piix_type == 1)
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card_piix[addr] = (val & 0xFC) | (card_piix[addr] | 3);
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else if (piix_type == 3)
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card_piix[addr] = (val & 0xFD) | (card_piix[addr] | 2);
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}
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else
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card_piix[addr] = val;
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}
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}
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uint8_t piix_read(int func, int addr, void *priv)
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{
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if (func > 1)
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return 0xff;
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if (func == 1) /*IDE*/
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{
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if (addr == 4)
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{
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return (card_piix_ide[addr] & 5) | 2;
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}
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else if (addr == 5)
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{
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return 0;
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}
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else if (addr == 6)
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{
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return 0x80;
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}
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else if (addr == 7)
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{
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return card_piix_ide[addr] & 0x3E;
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}
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else if (addr == 0xD)
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{
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return card_piix_ide[addr] & 0xF0;
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}
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else if (addr == 0x20)
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{
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return (card_piix_ide[addr] & 0xF0) | 1;
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}
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else if (addr == 0x22)
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{
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return 0;
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}
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else if (addr == 0x23)
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{
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return 0;
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}
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else if (addr == 0x41)
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{
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if (piix_type == 1)
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return card_piix_ide[addr] & 0xB3;
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else if (piix_type == 3)
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return card_piix_ide[addr] & 0xF3;
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}
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else if (addr == 0x43)
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{
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if (piix_type == 1)
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return card_piix_ide[addr] & 0xB3;
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else if (piix_type == 3)
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return card_piix_ide[addr] & 0xF3;
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}
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else
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{
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return card_piix_ide[addr];
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}
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}
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else
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{
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if ((addr & 0xFC) == 0x60)
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{
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return card_piix[addr] & 0x8F;
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}
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if (addr == 4)
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{
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return (card_piix[addr] & 0x80) | 7;
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}
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else if (addr == 5)
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{
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if (piix_type == 1)
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return 0;
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else if (piix_type == 3)
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return card_piix[addr] & 1;
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}
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else if (addr == 6)
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{
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return card_piix[addr] & 0x80;
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}
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else if (addr == 7)
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{
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if (piix_type == 1)
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return card_piix[addr] & 0x3E;
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else if (piix_type == 3)
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return card_piix[addr];
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}
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else if (addr == 0x4E)
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{
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return (card_piix[addr] & 0xEF) | keyboard_at_get_mouse_scan();
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}
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else if (addr == 0x69)
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{
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return card_piix[addr] & 0xFE;
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}
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else if (addr == 0x6A)
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{
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if (piix_type == 1)
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return card_piix[addr] & 0x07;
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else if (piix_type == 3)
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return card_piix[addr] & 0xD1;
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}
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else if (addr == 0x6B)
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{
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if (piix_type == 1)
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return 0;
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else if (piix_type == 3)
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return card_piix[addr] & 0x80;
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}
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else if (addr == 0x70)
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{
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if (piix_type == 1)
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return card_piix[addr] & 0xCF;
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else if (piix_type == 3)
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return card_piix[addr] & 0xEF;
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}
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else if (addr == 0x71)
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{
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if (piix_type == 1)
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return card_piix[addr] & 0xCF;
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else if (piix_type == 3)
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return 0;
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}
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else if (addr == 0x76)
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{
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if (piix_type == 1)
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return card_piix[addr] & 0x8F;
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else if (piix_type == 3)
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return card_piix[addr] & 0x87;
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}
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else if (addr == 0x77)
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{
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if (piix_type == 1)
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return card_piix[addr] & 0x8F;
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else if (piix_type == 3)
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return card_piix[addr] & 0x87;
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}
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else if (addr == 0x80)
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{
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if (piix_type == 1)
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return 0;
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else if (piix_type == 3)
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return card_piix[addr] & 0x7F;
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}
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else if (addr == 0x82)
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{
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if (piix_type == 1)
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return 0;
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else if (piix_type == 3)
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return card_piix[addr] & 0x0F;
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}
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else if (addr == 0xA0)
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{
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return card_piix[addr] & 0x1F;
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}
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else if (addr == 0xA3)
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{
|
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if (piix_type == 1)
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return 0;
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else if (piix_type == 3)
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return card_piix[addr] & 1;
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}
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else if (addr == 0xA7)
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{
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if (piix_type == 1)
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return card_piix[addr] & 0xEF;
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else if (piix_type == 3)
|
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return card_piix[addr];
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}
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else if (addr == 0xAB)
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{
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if (piix_type == 1)
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return card_piix[addr] & 0xFE;
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else if (piix_type == 3)
|
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return card_piix[addr];
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}
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else
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return card_piix[addr];
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}
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return 0;
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}
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|
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struct
|
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{
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uint8_t command;
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uint8_t status;
|
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uint32_t ptr, ptr_cur;
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int count;
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uint32_t addr;
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int eot;
|
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uint8_t ptr0;
|
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} piix_busmaster[2];
|
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|
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static void piix_bus_master_next_addr(int channel)
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{
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DMAPageRead(piix_busmaster[channel].ptr_cur, (char *) &(piix_busmaster[channel].addr), 4);
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DMAPageRead(piix_busmaster[channel].ptr_cur + 4, (char *) &(piix_busmaster[channel].count), 4);
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pclog("PIIX Bus master DWORDs: %08X %08X\n", piix_busmaster[channel].addr, piix_busmaster[channel].count);
|
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piix_busmaster[channel].eot = piix_busmaster[channel].count >> 31;
|
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piix_busmaster[channel].count &= 0xfffe;
|
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if (!piix_busmaster[channel].count)
|
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piix_busmaster[channel].count = 65536;
|
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piix_busmaster[channel].addr &= 0xfffffffe;
|
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piix_busmaster[channel].ptr_cur += 8;
|
||||
}
|
||||
|
||||
void piix_bus_master_write(uint16_t port, uint8_t val, void *priv)
|
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{
|
||||
/* pclog("PIIX Bus master write: %04X %02X\n", port, val); */
|
||||
int channel = (port & 8) ? 1 : 0;
|
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switch (port & 7) {
|
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case 0:
|
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if ((val & 1) && !(piix_busmaster[channel].command & 1)) { /*Start*/
|
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piix_busmaster[channel].ptr_cur = piix_busmaster[channel].ptr;
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piix_bus_master_next_addr(channel);
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piix_busmaster[channel].status |= 1;
|
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}
|
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if (!(val & 1) && (piix_busmaster[channel].command & 1)) /*Stop*/
|
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piix_busmaster[channel].status &= ~1;
|
||||
|
||||
piix_busmaster[channel].command = val;
|
||||
break;
|
||||
case 2:
|
||||
piix_busmaster[channel].status &= 0x07;
|
||||
piix_busmaster[channel].status |= (val & 0x60);
|
||||
if (val & 0x04)
|
||||
piix_busmaster[channel].status &= ~0x04;
|
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if (val & 0x02)
|
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piix_busmaster[channel].status &= ~0x02;
|
||||
/* piix_busmaster[channel].status = (val & 0x60) | ((piix_busmaster[channel].status & ~val) & 6) | (piix_busmaster[channel].status & 1); */
|
||||
break;
|
||||
case 4:
|
||||
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xffffff00) | (val & 0xfc);
|
||||
piix_busmaster[channel].ptr %= (mem_size * 1024);
|
||||
piix_busmaster[channel].ptr0 = val;
|
||||
break;
|
||||
case 5:
|
||||
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xffff00fc) | (val << 8);
|
||||
piix_busmaster[channel].ptr %= (mem_size * 1024);
|
||||
break;
|
||||
case 6:
|
||||
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xff00fffc) | (val << 16);
|
||||
piix_busmaster[channel].ptr %= (mem_size * 1024);
|
||||
break;
|
||||
case 7:
|
||||
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0x00fffffc) | (val << 24);
|
||||
piix_busmaster[channel].ptr %= (mem_size * 1024);
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t piix_bus_master_read(uint16_t port, void *priv)
|
||||
{
|
||||
/* pclog("PIIX Bus master read: %04X\n", port); */
|
||||
int channel = (port & 8) ? 1 : 0;
|
||||
switch (port & 7) {
|
||||
case 0:
|
||||
return piix_busmaster[channel].command;
|
||||
case 2:
|
||||
return piix_busmaster[channel].status & 0x67;
|
||||
case 4:
|
||||
return piix_busmaster[channel].ptr0;
|
||||
case 5:
|
||||
return piix_busmaster[channel].ptr >> 8;
|
||||
case 6:
|
||||
return piix_busmaster[channel].ptr >> 16;
|
||||
case 7:
|
||||
return piix_busmaster[channel].ptr >> 24;
|
||||
}
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
int piix_bus_master_get_count(int channel)
|
||||
{
|
||||
return piix_busmaster[channel].count;
|
||||
}
|
||||
|
||||
int piix_bus_master_get_eot(int channel)
|
||||
{
|
||||
return piix_busmaster[channel].eot;
|
||||
}
|
||||
|
||||
int piix_bus_master_dma_read(int channel, uint8_t *data, int transfer_length)
|
||||
{
|
||||
int force_end = 0;
|
||||
int buffer_pos = 0;
|
||||
|
||||
if (!(piix_busmaster[channel].status & 1))
|
||||
return 1; /*DMA disabled*/
|
||||
|
||||
pclog("PIIX Bus master read: %i bytes\n", transfer_length);
|
||||
|
||||
while (1) {
|
||||
if (piix_busmaster[channel].count <= transfer_length) {
|
||||
pclog("Writing %i bytes to %08X\n", piix_busmaster[channel].count, piix_busmaster[channel].addr);
|
||||
DMAPageWrite(piix_busmaster[channel].addr, (char *) (data + buffer_pos), piix_busmaster[channel].count);
|
||||
transfer_length -= piix_busmaster[channel].count;
|
||||
buffer_pos += piix_busmaster[channel].count;
|
||||
} else {
|
||||
pclog("Writing %i bytes to %08X\n", piix_busmaster[channel].count, piix_busmaster[channel].addr);
|
||||
DMAPageWrite(piix_busmaster[channel].addr, (char *) (data + buffer_pos), transfer_length);
|
||||
transfer_length = 0;
|
||||
force_end = 1;
|
||||
}
|
||||
|
||||
if (force_end) {
|
||||
pclog("Total transfer length smaller than sum of all blocks, partial block\n");
|
||||
piix_busmaster[channel].status &= ~2;
|
||||
return 0; /* This block has exhausted the data to transfer and it was smaller than the count, break. */
|
||||
} else {
|
||||
if (!transfer_length && !piix_busmaster[channel].eot) {
|
||||
pclog("Total transfer length smaller than sum of all blocks, full block\n");
|
||||
piix_busmaster[channel].status &= ~2;
|
||||
return 0; /* We have exhausted the data to transfer but there's more blocks left, break. */
|
||||
} else if (transfer_length && piix_busmaster[channel].eot) {
|
||||
pclog("Total transfer length greater than sum of all blocks\n");
|
||||
piix_busmaster[channel].status |= 2;
|
||||
return 1; /* There is data left to transfer but we have reached EOT - return with error. */
|
||||
} else if (piix_busmaster[channel].eot) {
|
||||
pclog("Regular EOT\n");
|
||||
piix_busmaster[channel].status &= ~3;
|
||||
return 0; /* We have regularly reached EOT - clear status and break. */
|
||||
} else {
|
||||
/* We have more to transfer and there are blocks left, get next block. */
|
||||
piix_bus_master_next_addr(channel);
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int piix_bus_master_dma_write(int channel, uint8_t *data, int transfer_length)
|
||||
{
|
||||
int force_end = 0;
|
||||
int buffer_pos = 0;
|
||||
|
||||
if (!(piix_busmaster[channel].status & 1))
|
||||
return 1; /*DMA disabled*/
|
||||
|
||||
pclog("PIIX Bus master write: %i bytes\n", transfer_length);
|
||||
|
||||
while (1) {
|
||||
if (piix_busmaster[channel].count <= transfer_length) {
|
||||
pclog("Reading %i bytes from %08X\n", piix_busmaster[channel].count, piix_busmaster[channel].addr);
|
||||
DMAPageRead(piix_busmaster[channel].addr, (char *) (data + buffer_pos), piix_busmaster[channel].count);
|
||||
transfer_length -= piix_busmaster[channel].count;
|
||||
buffer_pos += piix_busmaster[channel].count;
|
||||
} else {
|
||||
pclog("Reading %i bytes from %08X\n", piix_busmaster[channel].count, piix_busmaster[channel].addr);
|
||||
DMAPageRead(piix_busmaster[channel].addr, (char *) (data + buffer_pos), transfer_length);
|
||||
transfer_length = 0;
|
||||
force_end = 1;
|
||||
}
|
||||
|
||||
if (force_end) {
|
||||
pclog("Total transfer length smaller than sum of all blocks, partial block\n");
|
||||
piix_busmaster[channel].status &= ~2;
|
||||
return 0; /* This block has exhausted the data to transfer and it was smaller than the count, break. */
|
||||
} else {
|
||||
if (!transfer_length && !piix_busmaster[channel].eot) {
|
||||
pclog("Total transfer length smaller than sum of all blocks, full block\n");
|
||||
piix_busmaster[channel].status &= ~2;
|
||||
return 0; /* We have exhausted the data to transfer but there's more blocks left, break. */
|
||||
} else if (transfer_length && piix_busmaster[channel].eot) {
|
||||
pclog("Total transfer length greater than sum of all blocks\n");
|
||||
piix_busmaster[channel].status |= 2;
|
||||
return 1; /* There is data left to transfer but we have reached EOT - return with error. */
|
||||
} else if (piix_busmaster[channel].eot) {
|
||||
pclog("Regular EOT\n");
|
||||
piix_busmaster[channel].status &= ~3;
|
||||
return 0; /* We have regularly reached EOT - clear status and break. */
|
||||
} else {
|
||||
/* We have more to transfer and there are blocks left, get next block. */
|
||||
piix_bus_master_next_addr(channel);
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void piix_bus_master_set_irq(int channel)
|
||||
{
|
||||
// piix_busmaster[channel].status |= 4;
|
||||
piix_busmaster[channel & 0x0F].status &= ~4;
|
||||
piix_busmaster[channel & 0x0F].status |= (channel >> 4);
|
||||
}
|
||||
|
||||
|
||||
void piix_reset(void)
|
||||
{
|
||||
memset(card_piix, 0, 256);
|
||||
card_piix[0x00] = 0x86; card_piix[0x01] = 0x80; /*Intel*/
|
||||
card_piix[0x02] = 0x2e; card_piix[0x03] = 0x12; /*82371FB (PIIX)*/
|
||||
card_piix[0x04] = 0x07; card_piix[0x05] = 0x00;
|
||||
card_piix[0x06] = 0x80; card_piix[0x07] = 0x02;
|
||||
card_piix[0x08] = 0x00; /*A0 stepping*/
|
||||
card_piix[0x09] = 0x00; card_piix[0x0a] = 0x01; card_piix[0x0b] = 0x06;
|
||||
card_piix[0x0e] = 0x80; /*Multi-function device*/
|
||||
card_piix[0x4c] = 0x4d;
|
||||
card_piix[0x4e] = 0x03;
|
||||
card_piix[0x60] = card_piix[0x61] = card_piix[0x62] = card_piix[0x63] = 0x80;
|
||||
card_piix[0x69] = 0x02;
|
||||
card_piix[0x70] = card_piix[0x71] = 0xc0;
|
||||
card_piix[0x76] = card_piix[0x77] = 0x0c;
|
||||
card_piix[0x78] = 0x02; card_piix[0x79] = 0x00;
|
||||
card_piix[0xa0] = 0x08;
|
||||
card_piix[0xa2] = card_piix[0xa3] = 0x00;
|
||||
card_piix[0xa4] = card_piix[0xa5] = card_piix[0xa6] = card_piix[0xa7] = 0x00;
|
||||
card_piix[0xa8] = 0x0f;
|
||||
card_piix[0xaa] = card_piix[0xab] = 0x00;
|
||||
card_piix[0xac] = 0x00;
|
||||
card_piix[0xae] = 0x00;
|
||||
|
||||
card_piix_ide[0x00] = 0x86; card_piix_ide[0x01] = 0x80; /*Intel*/
|
||||
card_piix_ide[0x02] = 0x30; card_piix_ide[0x03] = 0x12; /*82371FB (PIIX)*/
|
||||
card_piix_ide[0x04] = 0x07; card_piix_ide[0x05] = 0x00;
|
||||
card_piix_ide[0x06] = 0x80; card_piix_ide[0x07] = 0x02;
|
||||
card_piix_ide[0x08] = 0x00;
|
||||
card_piix_ide[0x09] = 0x80; card_piix_ide[0x0a] = 0x01; card_piix_ide[0x0b] = 0x01;
|
||||
card_piix_ide[0x0d] = 0x00;
|
||||
card_piix_ide[0x0e] = 0x00;
|
||||
card_piix_ide[0x20] = 0x01; card_piix_ide[0x21] = card_piix_ide[0x22] = card_piix_ide[0x23] = 0x00; /*Bus master interface base address*/
|
||||
card_piix_ide[0x40] = card_piix_ide[0x42] = 0x00;
|
||||
card_piix_ide[0x41] = card_piix_ide[0x43] = 0x80;
|
||||
|
||||
pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
|
||||
pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
|
||||
}
|
||||
|
||||
void piix3_reset(void)
|
||||
{
|
||||
memset(card_piix, 0, 256);
|
||||
card_piix[0x00] = 0x86; card_piix[0x01] = 0x80; /*Intel*/
|
||||
card_piix[0x02] = 0x00; card_piix[0x03] = 0x70; /*82371SB (PIIX3)*/
|
||||
card_piix[0x04] = 0x07; card_piix[0x05] = 0x00;
|
||||
card_piix[0x06] = 0x80; card_piix[0x07] = 0x02;
|
||||
card_piix[0x08] = 0x00; /*A0 stepping*/
|
||||
card_piix[0x09] = 0x00; card_piix[0x0a] = 0x01; card_piix[0x0b] = 0x06;
|
||||
card_piix[0x0e] = 0x80; /*Multi-function device*/
|
||||
card_piix[0x4c] = 0x4d;
|
||||
card_piix[0x4e] = 0x03;
|
||||
card_piix[0x4f] = 0x00;
|
||||
card_piix[0x60] = card_piix[0x61] = card_piix[0x62] = card_piix[0x63] = 0x80;
|
||||
card_piix[0x69] = 0x02;
|
||||
card_piix[0x70] = 0xc0;
|
||||
card_piix[0x76] = card_piix[0x77] = 0x0c;
|
||||
card_piix[0x78] = 0x02; card_piix[0x79] = 0x00;
|
||||
card_piix[0x80] = card_piix[0x82] = 0x00;
|
||||
card_piix[0xa0] = 0x08;
|
||||
card_piix[0xa2] = card_piix[0xa3] = 0x00;
|
||||
card_piix[0xa4] = card_piix[0xa5] = card_piix[0xa6] = card_piix[0xa7] = 0x00;
|
||||
card_piix[0xa8] = 0x0f;
|
||||
card_piix[0xaa] = card_piix[0xab] = 0x00;
|
||||
card_piix[0xac] = 0x00;
|
||||
card_piix[0xae] = 0x00;
|
||||
|
||||
card_piix_ide[0x00] = 0x86; card_piix_ide[0x01] = 0x80; /*Intel*/
|
||||
card_piix_ide[0x02] = 0x10; card_piix_ide[0x03] = 0x70; /*82371SB (PIIX3)*/
|
||||
card_piix_ide[0x04] = 0x07; card_piix_ide[0x05] = 0x00;
|
||||
card_piix_ide[0x06] = 0x80; card_piix_ide[0x07] = 0x02;
|
||||
card_piix_ide[0x08] = 0x00;
|
||||
card_piix_ide[0x09] = 0x80; card_piix_ide[0x0a] = 0x01; card_piix_ide[0x0b] = 0x01;
|
||||
card_piix_ide[0x0d] = 0x00;
|
||||
card_piix_ide[0x0e] = 0x00;
|
||||
card_piix_ide[0x20] = 0x01; card_piix_ide[0x21] = card_piix_ide[0x22] = card_piix_ide[0x23] = 0x00; /*Bus master interface base address*/
|
||||
card_piix_ide[0x40] = card_piix_ide[0x42] = 0x00;
|
||||
card_piix_ide[0x41] = card_piix_ide[0x43] = 0x80;
|
||||
card_piix_ide[0x44] = 0x00;
|
||||
|
||||
pci_set_mirq_routing(PCI_MIRQ0, PCI_IRQ_DISABLED);
|
||||
}
|
||||
|
||||
void piix_init(int card)
|
||||
{
|
||||
pci_add_card(card, piix_read, piix_write, NULL);
|
||||
|
||||
piix_reset();
|
||||
|
||||
piix_type = 1;
|
||||
|
||||
ide_set_bus_master(piix_bus_master_dma_read, piix_bus_master_dma_write, piix_bus_master_set_irq);
|
||||
|
||||
port_92_reset();
|
||||
|
||||
port_92_add();
|
||||
|
||||
dma_alias_set();
|
||||
|
||||
pci_reset_handler.pci_set_reset = piix_reset;
|
||||
|
||||
pci_enable_mirq(0);
|
||||
pci_enable_mirq(1);
|
||||
}
|
||||
|
||||
void piix3_init(int card)
|
||||
{
|
||||
pci_add_card(card, piix_read, piix_write, NULL);
|
||||
|
||||
piix3_reset();
|
||||
|
||||
piix_type = 3;
|
||||
|
||||
ide_set_bus_master(piix_bus_master_dma_read, piix_bus_master_dma_write, piix_bus_master_set_irq);
|
||||
|
||||
port_92_reset();
|
||||
|
||||
port_92_add();
|
||||
|
||||
dma_alias_set();
|
||||
|
||||
pci_reset_handler.pci_set_reset = piix3_reset;
|
||||
|
||||
pci_enable_mirq(0);
|
||||
}
|
||||
Reference in New Issue
Block a user